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Searched refs:__BIT3 (Results 1 – 25 of 101) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6lite/hwi2c/
H A DregHWI2C.h127 #define CHIP_MIIC1_PAD_2 (__BIT3)
128 #define CHIP_MIIC1_PAD_3 (__BIT2|__BIT3)
129 #define CHIP_MIIC1_PAD_MSK (__BIT2|__BIT3)
144 #define CHIP_REG_HWI2C_MIIC0_CLL_36M (__BIT3)
145 #define CHIP_REG_HWI2C_MIIC0_CLK_54M (__BIT2 | __BIT3)
146 #define CHIP_REG_HWI2C_MIIC0_CLK_MSK (__BIT0 | __BIT1 | __BIT2 | __BIT3)
172 #define _MIIC_CFG_EN_CLKSTR (__BIT3)
191 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
196 #define _INT_TXDONE (__BIT3)
213 #define _DMA_CFG_MIURST (__BIT3)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/kano/hwi2c/
H A DregHWI2C.h127 #define CHIP_MIIC1_PAD_2 (__BIT3)
128 #define CHIP_MIIC1_PAD_3 (__BIT2|__BIT3)
129 #define CHIP_MIIC1_PAD_MSK (__BIT2|__BIT3)
144 #define CHIP_REG_HWI2C_MIIC0_CLL_36M (__BIT3)
145 #define CHIP_REG_HWI2C_MIIC0_CLK_54M (__BIT2 | __BIT3)
146 #define CHIP_REG_HWI2C_MIIC0_CLK_MSK (__BIT0 | __BIT1 | __BIT2 | __BIT3)
172 #define _MIIC_CFG_EN_CLKSTR (__BIT3)
191 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
196 #define _INT_TXDONE (__BIT3)
213 #define _DMA_CFG_MIURST (__BIT3)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6/hwi2c/
H A DregHWI2C.h127 #define CHIP_MIIC1_PAD_2 (__BIT3)
128 #define CHIP_MIIC1_PAD_3 (__BIT2|__BIT3)
129 #define CHIP_MIIC1_PAD_MSK (__BIT2|__BIT3)
144 #define CHIP_REG_HWI2C_MIIC0_CLL_36M (__BIT3)
145 #define CHIP_REG_HWI2C_MIIC0_CLK_54M (__BIT2 | __BIT3)
146 #define CHIP_REG_HWI2C_MIIC0_CLK_MSK (__BIT0 | __BIT1 | __BIT2 | __BIT3)
172 #define _MIIC_CFG_EN_CLKSTR (__BIT3)
191 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
196 #define _INT_TXDONE (__BIT3)
213 #define _DMA_CFG_MIURST (__BIT3)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/curry/hwi2c/
H A DregHWI2C.h127 #define CHIP_MIIC1_PAD_2 (__BIT3)
128 #define CHIP_MIIC1_PAD_3 (__BIT2|__BIT3)
129 #define CHIP_MIIC1_PAD_MSK (__BIT2|__BIT3)
144 #define CHIP_REG_HWI2C_MIIC0_CLL_36M (__BIT3)
145 #define CHIP_REG_HWI2C_MIIC0_CLK_54M (__BIT2 | __BIT3)
146 #define CHIP_REG_HWI2C_MIIC0_CLK_MSK (__BIT0 | __BIT1 | __BIT2 | __BIT3)
172 #define _MIIC_CFG_EN_CLKSTR (__BIT3)
191 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
196 #define _INT_TXDONE (__BIT3)
213 #define _DMA_CFG_MIURST (__BIT3)
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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mustang/hwi2c/
H A DregHWI2C.h123 #define CHIP_MIIC1_PAD_2 (__BIT3)
124 #define CHIP_MIIC1_PAD_MSK (__BIT2|__BIT3)
148 #define CHIP_MIIC5_PAD_1 (__BIT3)
149 #define CHIP_MIIC5_PAD_MSK (__BIT3)
167 #define _MIIC_CFG_EN_CLKSTR (__BIT3)
186 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
191 #define _INT_TXDONE (__BIT3)
209 #define _DMA_CFG_MIURST (__BIT3)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maldives/hwi2c/
H A DregHWI2C.h123 #define CHIP_MIIC1_PAD_2 (__BIT3)
124 #define CHIP_MIIC1_PAD_MSK (__BIT2|__BIT3)
148 #define CHIP_MIIC5_PAD_1 (__BIT3)
149 #define CHIP_MIIC5_PAD_MSK (__BIT3)
167 #define _MIIC_CFG_EN_CLKSTR (__BIT3)
186 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
191 #define _INT_TXDONE (__BIT3)
209 #define _DMA_CFG_MIURST (__BIT3)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/manhattan/hwi2c/
H A DregHWI2C.h138 #define CHIP_MIIC3_PAD_1 (__BIT3) //PAD_GPIO36/PAD_GPIO37
139 #define CHIP_MIIC3_PAD_MSK (__BIT3)
169 #define _MIIC_CFG_EN_CLKSTR (__BIT3)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
193 #define _INT_TXDONE (__BIT3)
209 #define _ADV_BYTE2BYTE_DELAY (__BIT3)
229 #define _DMA_CFG_MIURST (__BIT3)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mooney/hwi2c/
H A DregHWI2C.h138 #define CHIP_MIIC3_PAD_1 (__BIT3) //PAD_GPIO36/PAD_GPIO37
139 #define CHIP_MIIC3_PAD_MSK (__BIT3)
169 #define _MIIC_CFG_EN_CLKSTR (__BIT3)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
193 #define _INT_TXDONE (__BIT3)
211 #define _DMA_CFG_MIURST (__BIT3)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/messi/hwi2c/
H A DregHWI2C.h138 #define CHIP_MIIC3_PAD_1 (__BIT3) //PAD_GPIO36/PAD_GPIO37
139 #define CHIP_MIIC3_PAD_MSK (__BIT3)
169 #define _MIIC_CFG_EN_CLKSTR (__BIT3)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
193 #define _INT_TXDONE (__BIT3)
211 #define _DMA_CFG_MIURST (__BIT3)
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/macan/hwi2c/
H A DregHWI2C.h138 #define CHIP_MIIC3_PAD_1 (__BIT3) //PAD_GPIO36/PAD_GPIO37
139 #define CHIP_MIIC3_PAD_MSK (__BIT3)
169 #define _MIIC_CFG_EN_CLKSTR (__BIT3)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
193 #define _INT_TXDONE (__BIT3)
211 #define _DMA_CFG_MIURST (__BIT3)
/utopia/UTPA2-700.0.x/modules/pm/hal/mainz/pm/
H A DhalPM.c356 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
539 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
601 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSRAMOffsetForMCU()
649 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetDRAMOffsetForMCU()
734 HAL_PM_WriteByte(0x0e38UL, HAL_PM_ReadByte(0x0e38UL)&(~__BIT3)); in HAL_PM_Disable51()
740 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_Disable51()
756 #define ACTIVE_MASK (__BIT3|__BIT2|__BIT1|__BIT0)
/utopia/UTPA2-700.0.x/modules/pm/hal/maserati/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
537 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
599 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSRAMOffsetForMCU()
647 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetDRAMOffsetForMCU()
732 HAL_PM_WriteByte(0x0e38UL, HAL_PM_ReadByte(0x0e38UL)&(~__BIT3)); in HAL_PM_Disable51()
738 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_Disable51()
754 #define ACTIVE_MASK (__BIT3|__BIT2|__BIT1|__BIT0)
/utopia/UTPA2-700.0.x/modules/pm/hal/manhattan/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
537 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
599 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSRAMOffsetForMCU()
647 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetDRAMOffsetForMCU()
732 HAL_PM_WriteByte(0x0e38UL, HAL_PM_ReadByte(0x0e38UL)&(~__BIT3)); in HAL_PM_Disable51()
738 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_Disable51()
754 #define ACTIVE_MASK (__BIT3|__BIT2|__BIT1|__BIT0)
/utopia/UTPA2-700.0.x/modules/pm/hal/M7621/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
537 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
599 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSRAMOffsetForMCU()
647 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetDRAMOffsetForMCU()
732 HAL_PM_WriteByte(0x0e38UL, HAL_PM_ReadByte(0x0e38UL)&(~__BIT3)); in HAL_PM_Disable51()
738 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_Disable51()
754 #define ACTIVE_MASK (__BIT3|__BIT2|__BIT1|__BIT0)
/utopia/UTPA2-700.0.x/modules/pm/hal/maxim/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
537 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
599 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSRAMOffsetForMCU()
647 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetDRAMOffsetForMCU()
732 HAL_PM_WriteByte(0x0e38UL, HAL_PM_ReadByte(0x0e38UL)&(~__BIT3)); in HAL_PM_Disable51()
738 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_Disable51()
754 #define ACTIVE_MASK (__BIT3|__BIT2|__BIT1|__BIT0)
/utopia/UTPA2-700.0.x/modules/pm/hal/mooney/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
537 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
599 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSRAMOffsetForMCU()
647 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetDRAMOffsetForMCU()
732 HAL_PM_WriteByte(0x0e38UL, HAL_PM_ReadByte(0x0e38UL)&(~__BIT3)); in HAL_PM_Disable51()
738 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_Disable51()
754 #define ACTIVE_MASK (__BIT3|__BIT2|__BIT1|__BIT0)
/utopia/UTPA2-700.0.x/modules/pm/hal/M7821/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
537 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
599 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSRAMOffsetForMCU()
647 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetDRAMOffsetForMCU()
732 HAL_PM_WriteByte(0x0e38UL, HAL_PM_ReadByte(0x0e38UL)&(~__BIT3)); in HAL_PM_Disable51()
738 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_Disable51()
754 #define ACTIVE_MASK (__BIT3|__BIT2|__BIT1|__BIT0)
/utopia/UTPA2-700.0.x/modules/pm/hal/macan/pm/
H A DhalPM.c354 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
539 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
601 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSRAMOffsetForMCU()
649 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetDRAMOffsetForMCU()
734 HAL_PM_WriteByte(0x0e38UL, HAL_PM_ReadByte(0x0e38UL)&(~__BIT3)); in HAL_PM_Disable51()
740 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_Disable51()
756 #define ACTIVE_MASK (__BIT3|__BIT2|__BIT1|__BIT0)
/utopia/UTPA2-700.0.x/modules/pm/hal/messi/pm/
H A DhalPM.c356 …(HAL_PM_Read2Byte(REG_PM_CKG_RTC)&(~(__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)))|(1<<2)); //RTC clock sw… in HAL_PM_RtcInit()
539 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSPIOffsetForMCU()
601 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetSRAMOffsetForMCU()
649 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_SetDRAMOffsetForMCU()
734 HAL_PM_WriteByte(0x0e38UL, HAL_PM_ReadByte(0x0e38UL)&(~__BIT3)); in HAL_PM_Disable51()
740 HAL_PM_WriteRegBit(0x001018UL, DISABLE, __BIT3); // i_cache rstz in HAL_PM_Disable51()
756 #define ACTIVE_MASK (__BIT3|__BIT2|__BIT1|__BIT0)
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/
H A DregEMMflt.h109 #define __BIT3 __BIT(3) macro
209 #define EMM_DMA_FLUSH_EN __BIT3
229 #define EMM_STR2MIU_DATA_SWAP __BIT3
253 #define REG_MI2STR_WD_EN __BIT3
269 #define REG_SIM_C1_CONFIG __BIT3
/utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/nsk2/
H A DregEMMflt.h109 #define __BIT3 __BIT(3) macro
209 #define EMM_DMA_FLUSH_EN __BIT3
229 #define EMM_STR2MIU_DATA_SWAP __BIT3
253 #define REG_MI2STR_WD_EN __BIT3
269 #define REG_SIM_C1_CONFIG __BIT3
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/
H A DregEMMflt.h109 #define __BIT3 __BIT(3) macro
209 #define EMM_DMA_FLUSH_EN __BIT3
229 #define EMM_STR2MIU_DATA_SWAP __BIT3
253 #define REG_MI2STR_WD_EN __BIT3
269 #define REG_SIM_C1_CONFIG __BIT3
/utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/
H A DregEMMflt.h109 #define __BIT3 __BIT(3) macro
209 #define EMM_DMA_FLUSH_EN __BIT3
229 #define EMM_STR2MIU_DATA_SWAP __BIT3
253 #define REG_MI2STR_WD_EN __BIT3
269 #define REG_SIM_C1_CONFIG __BIT3
/utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/
H A DregEMMflt.h109 #define __BIT3 __BIT(3) macro
209 #define EMM_DMA_FLUSH_EN __BIT3
229 #define EMM_STR2MIU_DATA_SWAP __BIT3
253 #define REG_MI2STR_WD_EN __BIT3
269 #define REG_SIM_C1_CONFIG __BIT3
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7821/hwi2c/
H A DregHWI2C.h169 #define _MIIC_CFG_EN_CLKSTR (__BIT3)
188 #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0)
193 #define _INT_TXDONE (__BIT3)
209 #define _ADV_BYTE2BYTE_DELAY (__BIT3)
229 #define _DMA_CFG_MIURST (__BIT3)

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