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Searched refs:WriteRegMFE (Results 1 – 25 of 30) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/mfe/drv/mfe/cModel/
H A Dmfe_common.c105 void WriteRegMFE(MFE_U32 u32Address, MFE_U16 val, char *str1, int num, char *str3) in WriteRegMFE() function
158 WriteRegMFE(0x3c, mfe_reg.reg3c, "", 0, ""); in SetObufAddr()
159 WriteRegMFE(0x3d, mfe_reg.reg3d, "", 0, ""); in SetObufAddr()
160 WriteRegMFE(0x3e, mfe_reg.reg3e, "", 0, ""); in SetObufAddr()
161 WriteRegMFE(0x3f, mfe_reg.reg3f, "", 0, ""); in SetObufAddr()
166 WriteRegMFE(0x3b, mfe_reg.reg3b, "", 0, ""); in SetObufAddr()
173 WriteRegMFE(0x1d, mfe_reg.reg1d, "", 0, ""); in ClearBsfFullIRQ()
190 WriteRegMFE(0x1d, mfe_reg.reg1d, "", 0, ""); in ClearIRQ()
208 WriteRegMFE(0x00, mfe_reg.reg00, "", 0, ""); in Enable_HW()
218 WriteRegMFE(0x0, mfe_reg.reg00, "[%d] reg00", nRegWriteCount++, "SW reset 1"); in ResetAllRegs()
[all …]
H A Dmfe_reg_264e.c577 WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "tbc_mode=0"); in OutputSwCfg1_H264()
580 WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "tbc_mode=1"); in OutputSwCfg1_H264()
607 WriteRegMFE(0x0, mfe_reg.reg00, "[%d] reg00", nRegWriteCount++, "SW reset 0"); in OutputSwCfg1_H264()
609 WriteRegMFE(0x0, mfe_reg.reg00, "[%d] reg00", nRegWriteCount++, "SW reset 1"); in OutputSwCfg1_H264()
610 WriteRegMFE(0x1, mfe_reg.reg01, "[%d] reg01", nRegWriteCount++, "picture width"); in OutputSwCfg1_H264()
611 WriteRegMFE(0x2, mfe_reg.reg02, "[%d] reg02", nRegWriteCount++, "picture height"); in OutputSwCfg1_H264()
612 WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "value"); in OutputSwCfg1_H264()
613 WriteRegMFE(0x4, mfe_reg.reg04, "[%d] reg04", nRegWriteCount++, "er_bs mode threshold"); in OutputSwCfg1_H264()
614 WriteRegMFE(0x5, mfe_reg.reg05, "[%d] reg05", nRegWriteCount++, "inter prediction preference"); in OutputSwCfg1_H264()
616 WriteRegMFE(0x20, mfe_reg.reg20, "[%d] reg20", nRegWriteCount++, "ME partition setting"); in OutputSwCfg1_H264()
[all …]
H A Dmfe_reg_m4ve.c777 WriteRegMFE(0x0, mfe_reg.reg00, "[%d] reg00", nRegWriteCount++, "SW reset 0"); in OutputSwCfg1_Mp4()
779 WriteRegMFE(0x0, mfe_reg.reg00, "[%d] reg00", nRegWriteCount++, "SW reset 1"); in OutputSwCfg1_Mp4()
780 WriteRegMFE(0x1, mfe_reg.reg01, "[%d] reg01", nRegWriteCount++, "picture width"); in OutputSwCfg1_Mp4()
781 WriteRegMFE(0x2, mfe_reg.reg02, "[%d] reg02", nRegWriteCount++, "picture height"); in OutputSwCfg1_Mp4()
782 WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "value"); in OutputSwCfg1_Mp4()
783 WriteRegMFE(0x4, mfe_reg.reg04, "[%d] reg04", nRegWriteCount++, "er_bs mode threshold"); in OutputSwCfg1_Mp4()
784 WriteRegMFE(0x5, mfe_reg.reg05, "[%d] reg05", nRegWriteCount++, "inter prediction preference"); in OutputSwCfg1_Mp4()
786 WriteRegMFE(0x20, mfe_reg.reg20, "[%d] reg20", nRegWriteCount++, "ME partition setting"); in OutputSwCfg1_Mp4()
787 WriteRegMFE(0x21, mfe_reg.reg21, "[%d] reg21", nRegWriteCount++, "value"); in OutputSwCfg1_Mp4()
788 WriteRegMFE(0x22, mfe_reg.reg22, "[%d] reg22", nRegWriteCount++, "me search range max depth"); in OutputSwCfg1_Mp4()
[all …]
H A Dmfe_reg_jpge.c208 WriteRegMFE(0x0, mfe_reg.reg00, "[%d] reg00", nRegWriteCount++, "SW reset 0"); in OutputSwCfg1_Jpg()
210 WriteRegMFE(0x0, mfe_reg.reg00, "[%d] reg00", nRegWriteCount++, "SW reset 1"); in OutputSwCfg1_Jpg()
213 WriteRegMFE(0x18, mfe_reg.reg18, "[%d] reg18", nRegWriteCount++, "VIU reset 0"); in OutputSwCfg1_Jpg()
215 WriteRegMFE(0x18, mfe_reg.reg18, "[%d] reg18", nRegWriteCount++, "VIU reset 1"); in OutputSwCfg1_Jpg()
218 WriteRegMFE(0x1, mfe_reg.reg01, "[%d] reg01", nRegWriteCount++, "picture width"); in OutputSwCfg1_Jpg()
219 WriteRegMFE(0x2, mfe_reg.reg02, "[%d] reg02", nRegWriteCount++, "picture height"); in OutputSwCfg1_Jpg()
220 WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "value"); in OutputSwCfg1_Jpg()
222 WriteRegMFE(0x16, mfe_reg.reg16, "[%d] reg16", nRegWriteCount++, "Clock gating"); in OutputSwCfg1_Jpg()
226 WriteRegMFE(0x06, mfe_reg.reg06, "[%d] reg06", nRegWriteCount++, "current luma base address"); in OutputSwCfg1_Jpg()
227 WriteRegMFE(0x07, mfe_reg.reg07, "[%d] reg07", nRegWriteCount++, "current luma base address high"); in OutputSwCfg1_Jpg()
[all …]
/utopia/UTPA2-700.0.x/modules/mfe/drv/mfe_ex/cModel/
H A Dmfe_common.c105 void WriteRegMFE(MS_U32 u32Address, MS_U16 val, MS_S8 *str1, MS_S32 num, MS_S8 *str3) in WriteRegMFE() function
211 …WriteRegMFE(0x3e, mfe_reg->reg3e, (MS_S8*)("[%d] reg3e"), nRegWriteCount++, (MS_S8*)("write_id_adr… in SetObufAddr()
212 …WriteRegMFE(0x3e, mfe_reg->reg3e, (MS_S8*)("[%d] reg3e"), nRegWriteCount++, (MS_S8*)("write_id_adr… in SetObufAddr()
217 …WriteRegMFE(0x3c, mfe_reg->reg3c, (MS_S8*)("[%d] reg3c"), nRegWriteCount++, (MS_S8*)("bsp obuf add… in SetObufAddr()
218 …WriteRegMFE(0x3d, mfe_reg->reg3d, (MS_S8*)("[%d] reg3d"), nRegWriteCount++, (MS_S8*)("bsp obuf add… in SetObufAddr()
220 …WriteRegMFE(0x3e, mfe_reg->reg3e, (MS_S8*)("[%d] reg3e"), nRegWriteCount++, (MS_S8*)("write_id_adr… in SetObufAddr()
225 …WriteRegMFE(0x3e, mfe_reg->reg3e, (MS_S8*)("[%d] reg3e"), nRegWriteCount++, (MS_S8*)("write_id_adr… in SetObufAddr()
226 …WriteRegMFE(0x3e, mfe_reg->reg3e, (MS_S8*)("[%d] reg3e"), nRegWriteCount++, (MS_S8*)("write_id_adr… in SetObufAddr()
231 …WriteRegMFE(0x3c, mfe_reg->reg3c, (MS_S8*)("[%d] reg3c"), nRegWriteCount++, (MS_S8*)("bsp obuf add… in SetObufAddr()
232 …WriteRegMFE(0x3d, mfe_reg->reg3d, (MS_S8*)("[%d] reg3d"), nRegWriteCount++, (MS_S8*)("bsp obuf add… in SetObufAddr()
[all …]
H A Dmfe_reg_264e.c1004 …WriteRegMFE(0x3, mfe_reg->reg03, (MS_S8*)("[%d] reg03"), nRegWriteCount++, (MS_S8*)("tbc_mode=0")); in OutputSwCfg1_H264()
1007 …WriteRegMFE(0x3, mfe_reg->reg03, (MS_S8*)("[%d] reg03"), nRegWriteCount++, (MS_S8*)("tbc_mode=1")); in OutputSwCfg1_H264()
1039 …WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)("[%d] reg00"), nRegWriteCount++, (MS_S8*)("SW reset 0")); in OutputSwCfg1_H264()
1041 …WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)("[%d] reg00"), nRegWriteCount++, (MS_S8*)("SW reset 1")); in OutputSwCfg1_H264()
1042 …WriteRegMFE(0x1, mfe_reg->reg01, (MS_S8*)("[%d] reg01"), nRegWriteCount++, (MS_S8*)("picture width… in OutputSwCfg1_H264()
1043 …WriteRegMFE(0x2, mfe_reg->reg02, (MS_S8*)("[%d] reg02"), nRegWriteCount++, (MS_S8*)("picture heigh… in OutputSwCfg1_H264()
1044 WriteRegMFE(0x3, mfe_reg->reg03, (MS_S8*)("[%d] reg03"), nRegWriteCount++, (MS_S8*)("value")); in OutputSwCfg1_H264()
1045 …WriteRegMFE(0x4, mfe_reg->reg04, (MS_S8*)("[%d] reg04"), nRegWriteCount++, (MS_S8*)("er_bs mode th… in OutputSwCfg1_H264()
1046 …WriteRegMFE(0x5, mfe_reg->reg05, (MS_S8*)("[%d] reg05"), nRegWriteCount++, (MS_S8*)("inter predict… in OutputSwCfg1_H264()
1048 …WriteRegMFE(0x20, mfe_reg->reg20, (MS_S8*)("[%d] reg20"), nRegWriteCount++, (MS_S8*)("ME partition… in OutputSwCfg1_H264()
[all …]
H A Dmfe_reg_m4ve.c712 … WriteRegMFE(0x68, mfe_reg->reg68, (MS_S8*)("[%d] reg68"), nRegWriteCount, (MS_S8*)("IMI enable")); in OutputSwCfg1_Mp4()
935 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)("[%d] reg00"), nRegWriteCount++, (MS_S8*)("SW reset 0")); in OutputSwCfg1_Mp4()
937 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)("[%d] reg00"), nRegWriteCount++, (MS_S8*)("SW reset 1")); in OutputSwCfg1_Mp4()
938 …WriteRegMFE(0x1, mfe_reg->reg01, (MS_S8*)("[%d] reg01"), nRegWriteCount++, (MS_S8*)("picture width… in OutputSwCfg1_Mp4()
939 …WriteRegMFE(0x2, mfe_reg->reg02, (MS_S8*)("[%d] reg02"), nRegWriteCount++, (MS_S8*)("picture heigh… in OutputSwCfg1_Mp4()
940 WriteRegMFE(0x3, mfe_reg->reg03, (MS_S8*)("[%d] reg03"), nRegWriteCount++, (MS_S8*)("value")); in OutputSwCfg1_Mp4()
941 …WriteRegMFE(0x4, mfe_reg->reg04, (MS_S8*)("[%d] reg04"), nRegWriteCount++, (MS_S8*)("er_bs mode th… in OutputSwCfg1_Mp4()
942 …WriteRegMFE(0x5, mfe_reg->reg05, (MS_S8*)("[%d] reg05"), nRegWriteCount++, (MS_S8*)("inter predict… in OutputSwCfg1_Mp4()
944 …WriteRegMFE(0x20, mfe_reg->reg20, (MS_S8*)("[%d] reg20"), nRegWriteCount++, (MS_S8*)("ME partition… in OutputSwCfg1_Mp4()
945 WriteRegMFE(0x21, mfe_reg->reg21, (MS_S8*)("[%d] reg21"), nRegWriteCount++, (MS_S8*)("value")); in OutputSwCfg1_Mp4()
[all …]
H A Dmfe_reg_jpge.c_277 WriteRegMFE(0x0, mfe_reg->reg00, "[%d] reg00", nRegWriteCount++, "SW reset 0");
279 WriteRegMFE(0x0, mfe_reg->reg00, "[%d] reg00", nRegWriteCount++, "SW reset 1");
281 WriteRegMFE(0x1, mfe_reg->reg01, "[%d] reg01", nRegWriteCount++, "picture width");
282 WriteRegMFE(0x2, mfe_reg->reg02, "[%d] reg02", nRegWriteCount++, "picture height");
283 WriteRegMFE(0x3, mfe_reg->reg03, "[%d] reg03", nRegWriteCount++, "value");
285 WriteRegMFE(0x16, mfe_reg->reg16, "[%d] reg16", nRegWriteCount++, "Clock gating");
288 WriteRegMFE(0x06, mfe_reg->reg06, "[%d] reg06", nRegWriteCount++, "current luma base address");
289 …WriteRegMFE(0x07, mfe_reg->reg07, "[%d] reg07", nRegWriteCount++, "current luma base address high"…
290 WriteRegMFE(0x08, mfe_reg->reg08, "[%d] reg08", nRegWriteCount++, "current chroma base address");
291 …WriteRegMFE(0x09, mfe_reg->reg09, "[%d] reg09", nRegWriteCount++, "current chroma base address hig…
[all …]
/utopia/UTPA2-700.0.x/modules/mfe/hal/maxim/mfe/Aeon/
H A Dmhal_mfe.c225 WriteRegMFE(0x0, mfe_reg.reg00, "", 0, ""); in MHal_MFE_SWReset()
256 WriteRegMFE(0x1d, irq_bits, "", 0, ""); in MHal_MFE_ClearIRQ()
278 WriteRegMFE(0x0a, (MFE_U16)mfe_reg.reg0a, "", 0, ""); in MHal_MFE_SetCLKCTL()
293 WriteRegMFE(0x73, u16Reg1, "", 0, ""); in MHal_MFE_GetCRC()
304 WriteRegMFE(0x73, u16Reg1, "", 0, ""); in MHal_MFE_GetCRC()
392 WriteRegMFE(0x58, mfe_reg.reg58, "", 1, "bsp ubound"); in MHal_MFE_Enable_MIU_Protection()
393 WriteRegMFE(0x59, mfe_reg.reg59, "[%d]", 1, "en & bsp ubound"); in MHal_MFE_Enable_MIU_Protection()
394 WriteRegMFE(0x5a, mfe_reg.reg5a, "", 1, "bsp lbound"); in MHal_MFE_Enable_MIU_Protection()
395 WriteRegMFE(0x5b, mfe_reg.reg5b, "", 1, "bsp lbound"); in MHal_MFE_Enable_MIU_Protection()
397 WriteRegMFE(0x5c, mfe_reg.reg5c, "", 1, "rec ubound"); in MHal_MFE_Enable_MIU_Protection()
[all …]
/utopia/UTPA2-700.0.x/modules/mfe/hal/M7821/mfe/Aeon/
H A Dmhal_mfe.c225 WriteRegMFE(0x0, mfe_reg.reg00, "", 0, ""); in MHal_MFE_SWReset()
256 WriteRegMFE(0x1d, irq_bits, "", 0, ""); in MHal_MFE_ClearIRQ()
278 WriteRegMFE(0x0a, (MFE_U16)mfe_reg.reg0a, "", 0, ""); in MHal_MFE_SetCLKCTL()
293 WriteRegMFE(0x73, u16Reg1, "", 0, ""); in MHal_MFE_GetCRC()
304 WriteRegMFE(0x73, u16Reg1, "", 0, ""); in MHal_MFE_GetCRC()
392 WriteRegMFE(0x58, mfe_reg.reg58, "", 1, "bsp ubound"); in MHal_MFE_Enable_MIU_Protection()
393 WriteRegMFE(0x59, mfe_reg.reg59, "[%d]", 1, "en & bsp ubound"); in MHal_MFE_Enable_MIU_Protection()
394 WriteRegMFE(0x5a, mfe_reg.reg5a, "", 1, "bsp lbound"); in MHal_MFE_Enable_MIU_Protection()
395 WriteRegMFE(0x5b, mfe_reg.reg5b, "", 1, "bsp lbound"); in MHal_MFE_Enable_MIU_Protection()
397 WriteRegMFE(0x5c, mfe_reg.reg5c, "", 1, "rec ubound"); in MHal_MFE_Enable_MIU_Protection()
[all …]
/utopia/UTPA2-700.0.x/modules/mfe/hal/maserati/mfe/Aeon/
H A Dmhal_mfe.c225 WriteRegMFE(0x0, mfe_reg.reg00, "", 0, ""); in MHal_MFE_SWReset()
256 WriteRegMFE(0x1d, irq_bits, "", 0, ""); in MHal_MFE_ClearIRQ()
278 WriteRegMFE(0x0a, (MFE_U16)mfe_reg.reg0a, "", 0, ""); in MHal_MFE_SetCLKCTL()
293 WriteRegMFE(0x73, u16Reg1, "", 0, ""); in MHal_MFE_GetCRC()
304 WriteRegMFE(0x73, u16Reg1, "", 0, ""); in MHal_MFE_GetCRC()
392 WriteRegMFE(0x58, mfe_reg.reg58, "", 1, "bsp ubound"); in MHal_MFE_Enable_MIU_Protection()
393 WriteRegMFE(0x59, mfe_reg.reg59, "[%d]", 1, "en & bsp ubound"); in MHal_MFE_Enable_MIU_Protection()
394 WriteRegMFE(0x5a, mfe_reg.reg5a, "", 1, "bsp lbound"); in MHal_MFE_Enable_MIU_Protection()
395 WriteRegMFE(0x5b, mfe_reg.reg5b, "", 1, "bsp lbound"); in MHal_MFE_Enable_MIU_Protection()
397 WriteRegMFE(0x5c, mfe_reg.reg5c, "", 1, "rec ubound"); in MHal_MFE_Enable_MIU_Protection()
[all …]
/utopia/UTPA2-700.0.x/modules/mfe/hal/macan/mfe/Aeon/
H A Dmhal_mfe.c225 WriteRegMFE(0x0, mfe_reg.reg00, "", 0, ""); in MHal_MFE_SWReset()
256 WriteRegMFE(0x1d, irq_bits, "", 0, ""); in MHal_MFE_ClearIRQ()
278 WriteRegMFE(0x0a, (MFE_U16)mfe_reg.reg0a, "", 0, ""); in MHal_MFE_SetCLKCTL()
293 WriteRegMFE(0x73, u16Reg1, "", 0, ""); in MHal_MFE_GetCRC()
304 WriteRegMFE(0x73, u16Reg1, "", 0, ""); in MHal_MFE_GetCRC()
392 WriteRegMFE(0x58, mfe_reg.reg58, "", 1, "bsp ubound"); in MHal_MFE_Enable_MIU_Protection()
393 WriteRegMFE(0x59, mfe_reg.reg59, "[%d]", 1, "en & bsp ubound"); in MHal_MFE_Enable_MIU_Protection()
394 WriteRegMFE(0x5a, mfe_reg.reg5a, "", 1, "bsp lbound"); in MHal_MFE_Enable_MIU_Protection()
395 WriteRegMFE(0x5b, mfe_reg.reg5b, "", 1, "bsp lbound"); in MHal_MFE_Enable_MIU_Protection()
397 WriteRegMFE(0x5c, mfe_reg.reg5c, "", 1, "rec ubound"); in MHal_MFE_Enable_MIU_Protection()
[all …]
/utopia/UTPA2-700.0.x/modules/mfe/hal/M7621/mfe/Aeon/
H A Dmhal_mfe.c225 WriteRegMFE(0x0, mfe_reg.reg00, "", 0, ""); in MHal_MFE_SWReset()
256 WriteRegMFE(0x1d, irq_bits, "", 0, ""); in MHal_MFE_ClearIRQ()
278 WriteRegMFE(0x0a, (MFE_U16)mfe_reg.reg0a, "", 0, ""); in MHal_MFE_SetCLKCTL()
293 WriteRegMFE(0x73, u16Reg1, "", 0, ""); in MHal_MFE_GetCRC()
304 WriteRegMFE(0x73, u16Reg1, "", 0, ""); in MHal_MFE_GetCRC()
392 WriteRegMFE(0x58, mfe_reg.reg58, "", 1, "bsp ubound"); in MHal_MFE_Enable_MIU_Protection()
393 WriteRegMFE(0x59, mfe_reg.reg59, "[%d]", 1, "en & bsp ubound"); in MHal_MFE_Enable_MIU_Protection()
394 WriteRegMFE(0x5a, mfe_reg.reg5a, "", 1, "bsp lbound"); in MHal_MFE_Enable_MIU_Protection()
395 WriteRegMFE(0x5b, mfe_reg.reg5b, "", 1, "bsp lbound"); in MHal_MFE_Enable_MIU_Protection()
397 WriteRegMFE(0x5c, mfe_reg.reg5c, "", 1, "rec ubound"); in MHal_MFE_Enable_MIU_Protection()
[all …]
/utopia/UTPA2-700.0.x/modules/mfe/hal/manhattan/mfe/Aeon/
H A Dmhal_mfe.c225 WriteRegMFE(0x0, mfe_reg.reg00, "", 0, ""); in MHal_MFE_SWReset()
256 WriteRegMFE(0x1d, irq_bits, "", 0, ""); in MHal_MFE_ClearIRQ()
278 WriteRegMFE(0x0a, (MFE_U16)mfe_reg.reg0a, "", 0, ""); in MHal_MFE_SetCLKCTL()
293 WriteRegMFE(0x73, u16Reg1, "", 0, ""); in MHal_MFE_GetCRC()
304 WriteRegMFE(0x73, u16Reg1, "", 0, ""); in MHal_MFE_GetCRC()
392 WriteRegMFE(0x58, mfe_reg.reg58, "", 1, "bsp ubound"); in MHal_MFE_Enable_MIU_Protection()
393 WriteRegMFE(0x59, mfe_reg.reg59, "[%d]", 1, "en & bsp ubound"); in MHal_MFE_Enable_MIU_Protection()
394 WriteRegMFE(0x5a, mfe_reg.reg5a, "", 1, "bsp lbound"); in MHal_MFE_Enable_MIU_Protection()
395 WriteRegMFE(0x5b, mfe_reg.reg5b, "", 1, "bsp lbound"); in MHal_MFE_Enable_MIU_Protection()
397 WriteRegMFE(0x5c, mfe_reg.reg5c, "", 1, "rec ubound"); in MHal_MFE_Enable_MIU_Protection()
[all …]
/utopia/UTPA2-700.0.x/modules/mfe/hal/maldives/mfe_ex/
H A Dmhal_mfe.c247 WriteRegMFE(0x0, mfe_reg->reg00, "", 0, ""); in MHal_MFE_SWReset()
270 WriteRegMFE(0x1d, irq_bits, "", 0, ""); in MHal_MFE_ClearIRQ()
285 WriteRegMFE(0x73, tmp_reg, "", 0, ""); in MHal_MFE_CycleReport()
311 WriteRegMFE(0x0a, (MFE_U16)mfe_reg->reg0a, "", 0, ""); in MHal_MFE_SetCLKCTL()
326 WriteRegMFE(0x73, u16Reg1, "", 0, ""); in MHal_MFE_GetCRC()
337 WriteRegMFE(0x73, u16Reg1, "", 0, ""); in MHal_MFE_GetCRC()
/utopia/UTPA2-700.0.x/modules/mfe/hal/mustang/mfe_ex/
H A Dmhal_mfe.c247 WriteRegMFE(0x0, mfe_reg->reg00, "", 0, ""); in MHal_MFE_SWReset()
270 WriteRegMFE(0x1d, irq_bits, "", 0, ""); in MHal_MFE_ClearIRQ()
285 WriteRegMFE(0x73, tmp_reg, "", 0, ""); in MHal_MFE_CycleReport()
311 WriteRegMFE(0x0a, (MFE_U16)mfe_reg->reg0a, "", 0, ""); in MHal_MFE_SetCLKCTL()
326 WriteRegMFE(0x73, u16Reg1, "", 0, ""); in MHal_MFE_GetCRC()
337 WriteRegMFE(0x73, u16Reg1, "", 0, ""); in MHal_MFE_GetCRC()
/utopia/UTPA2-700.0.x/modules/mfe/hal/messi/mfe_ex/
H A Dmhal_mfe.c247 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SWReset()
270 WriteRegMFE(0x1d, irq_bits, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_ClearIRQ()
285 WriteRegMFE(0x73, tmp_reg, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_CycleReport()
311 WriteRegMFE(0x0a, (MS_U16)mfe_reg->reg0a, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SetCLKCTL()
326 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()
337 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()
/utopia/UTPA2-700.0.x/modules/mfe/hal/manhattan/mfe_ex/
H A Dmhal_mfe.c247 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SWReset()
270 WriteRegMFE(0x1d, irq_bits, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_ClearIRQ()
285 WriteRegMFE(0x73, tmp_reg, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_CycleReport()
311 WriteRegMFE(0x0a, (MS_U16)mfe_reg->reg0a, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SetCLKCTL()
326 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()
337 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()
/utopia/UTPA2-700.0.x/modules/mfe/hal/mainz/mfe_ex/
H A Dmhal_mfe.c247 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SWReset()
270 WriteRegMFE(0x1d, irq_bits, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_ClearIRQ()
285 WriteRegMFE(0x73, tmp_reg, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_CycleReport()
311 WriteRegMFE(0x0a, (MS_U16)mfe_reg->reg0a, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SetCLKCTL()
326 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()
337 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()
/utopia/UTPA2-700.0.x/modules/mfe/hal/macan/mfe_ex/
H A Dmhal_mfe.c247 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SWReset()
270 WriteRegMFE(0x1d, irq_bits, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_ClearIRQ()
285 WriteRegMFE(0x73, tmp_reg, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_CycleReport()
311 WriteRegMFE(0x0a, (MS_U16)mfe_reg->reg0a, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SetCLKCTL()
326 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()
337 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()
/utopia/UTPA2-700.0.x/modules/mfe/hal/curry/mfe_ex/
H A Dmhal_mfe.c289 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SWReset()
312 WriteRegMFE(0x1d, irq_bits, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_ClearIRQ()
328 WriteRegMFE(0x73, tmp_reg, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_CycleReport()
354 WriteRegMFE(0x0a, (MS_U16)mfe_reg->reg0a, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SetCLKCTL()
369 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()
380 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()
/utopia/UTPA2-700.0.x/modules/mfe/hal/M7621/mfe_ex/
H A Dmhal_mfe.c293 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SWReset()
316 WriteRegMFE(0x1d, irq_bits, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_ClearIRQ()
332 WriteRegMFE(0x73, tmp_reg, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_CycleReport()
358 WriteRegMFE(0x0a, (MS_U16)mfe_reg->reg0a, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SetCLKCTL()
373 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()
384 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()
/utopia/UTPA2-700.0.x/modules/mfe/hal/maxim/mfe_ex/
H A Dmhal_mfe.c293 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SWReset()
316 WriteRegMFE(0x1d, irq_bits, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_ClearIRQ()
332 WriteRegMFE(0x73, tmp_reg, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_CycleReport()
358 WriteRegMFE(0x0a, (MS_U16)mfe_reg->reg0a, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SetCLKCTL()
373 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()
384 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()
/utopia/UTPA2-700.0.x/modules/mfe/hal/kano/mfe_ex/
H A Dmhal_mfe.c289 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SWReset()
312 WriteRegMFE(0x1d, irq_bits, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_ClearIRQ()
328 WriteRegMFE(0x73, tmp_reg, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_CycleReport()
354 WriteRegMFE(0x0a, (MS_U16)mfe_reg->reg0a, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SetCLKCTL()
369 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()
380 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()
/utopia/UTPA2-700.0.x/modules/mfe/hal/M7821/mfe_ex/
H A Dmhal_mfe.c293 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SWReset()
316 WriteRegMFE(0x1d, irq_bits, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_ClearIRQ()
332 WriteRegMFE(0x73, tmp_reg, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_CycleReport()
358 WriteRegMFE(0x0a, (MS_U16)mfe_reg->reg0a, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_SetCLKCTL()
373 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()
384 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)("")); in MHal_MFE_GetCRC()

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