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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MFE_chip.h"
96 #include "mfe_type.h"
97 #include "mfe_common.h"
98 #include "ms_dprintf.h"
99
100 #if defined(__MOBILE_CASE__)
101 #include "drv_clkgen_cmu.h"
102 #endif
103 #if defined(_MIPS_PLATFORM_)&&defined(_MFE_T8_)&&defined(_KERNEL_MODE_)
104 #elif defined(__UBOOT__)
105 #include <linux/string.h>
106 #else
107 #include <string.h>
108 #endif
109
110 #include "mhal_mfe.h"
111 #include "mfe_reg.h"
112
MHal_MFE_GetHWCap(MS_U16 * width,MS_U16 * height)113 MS_BOOL MHal_MFE_GetHWCap(MS_U16 *width, MS_U16 *height)
114 {
115 #ifdef MFE_SUPPORT_1080P
116 *width = 1920;
117 *height = 1088;
118 #else
119 *width = 1280;
120 *height = 720;
121 #endif
122 return TRUE;
123 }
124
125 #if (defined(_MFE_T8_)||defined(_MFE_M1_))&& !defined(_KERNEL_MODE_)
126 MS_U32 u32MFERegOSBase;
127
MHAL_MFE_InitRegBase(MS_U32 U32RegBase)128 void MHAL_MFE_InitRegBase(MS_U32 U32RegBase)
129 {
130 ms_dprintk(HAL_L1,"HAL_MFE_InitRegBase 0x%X\n", (MS_U32)U32RegBase);
131 u32MFERegOSBase = U32RegBase;
132 }
133
MHAL_MFE_CreateRegMap(MFE_REG * mfe_reg,MFE_REG1 * mfe_reg1)134 void MHAL_MFE_CreateRegMap(MFE_REG* mfe_reg, MFE_REG1* mfe_reg1)
135 {
136 //mfe_reg = malloc(sizeof(MFE_REG));
137 memset(mfe_reg, 0, sizeof(MFE_REG));
138 //mfe_reg1 = malloc(sizeof(MFE_REG1));
139 memset(mfe_reg1, 0, sizeof(MFE_REG1));
140
141 }
142
MHAL_MFE_DelRegMap(MFE_REG * mfe_reg,MFE_REG1 * mfe_reg1)143 void MHAL_MFE_DelRegMap(MFE_REG* mfe_reg, MFE_REG1* mfe_reg1)
144 {
145 //free(mfe_reg);
146 //free(mfe_reg1);
147 }
148
149 #endif
150
151
MHal_MFE_PowerOff(MS_U32 is_off,MFE_CLK_LEVEL clock_level)152 void MHal_MFE_PowerOff(MS_U32 is_off,MFE_CLK_LEVEL clock_level)
153 {
154 #ifndef WIN32
155
156 #if defined(__MOBILE_CASE__)
157 //#define CMU_MMP_ASIC_CLK_MFE 170UL //clk_occmux_sel CMU_CLK_OFF, CMU_CLK_32K, CMU_CLK_12M, CMU_CLK_24M, CMU_CLK_64M, CMU_CLK_85P3M, CMU_CLK_109P6M, CMU_CLK_128M, CMU_CLK_153P6M, CMU_CLK_170P6M
158 #ifndef CMU_CLK_24M
159 #define CMU_CLK_24M CMU_MMP_ASIC_CLK_24M
160 #define CMU_CLK_64M CMU_MMP_ASIC_CLK_64M
161 #define CMU_CLK_128M CMU_MMP_ASIC_CLK_128M
162 #define CMU_CLK_170P6M CMU_MMP_ASIC_CLK_170P6M
163 #define CMU_CLK_170P6M CMU_MMP_ASIC_CLK_170P6M
164 #endif
165
166 MS_S32 ret;
167 if (is_off) {
168 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_OFF);
169 if(ret < 0)
170 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_OFF fail\n");
171 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MIU_MFE, CMU_CLK_OFF);
172 if(ret < 0)
173 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_OFF fail\n");
174 } else {
175 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MIU_MFE, CMU_CLK_ON);
176 if(ret < 0)
177 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MIU_MFE CMU_CLK_ON fail\n");
178 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_ON);
179 if(ret < 0)
180 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE CMU_CLK_ON fail\n");
181
182 ms_dprintk(HAL_L1,"clk level = %d\n",clock_level);
183 switch (clock_level)
184 {
185 case MFE_CLK_VERY_SLOW:
186 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_24M); break;
187 case MFE_CLK_SLOW:
188 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_64M); break;
189 case MFE_CLK_MEDIUM:
190 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_128M); break;
191 case MFE_CLK_FAST:
192 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_170P6M); break;
193 default:
194 ret = DrvClkgenSetClk(CMU_MMP_ASIC_CLK_MFE, CMU_CLK_170P6M); break;
195 }
196 if(ret < 0)
197 ms_dprintk(HAL_L1,"CMU_MMP_ASIC_CLK_MFE Switch fail\n");
198 }
199
200 #elif defined(_MFE_T8_) &&defined(_MIPS_PLATFORM_)&&defined(_KERNEL_MODE_)
201 if (is_off) {
202 *(MS_U16*)(0xbf206600+(0x18)*4) = 1;//disable MFE clock
203 } else {
204 //*(MS_U16*)(0xbf206600+(0x18)*4) = 0; // 4'b0000 123
205 //*(MS_U16*)(0xbf206600+(0x18)*4) = 4; // 4'b0100 144
206 //*(MS_U16*)(0xbf206600+(0x18)*4) = 8; // 4'b1000 172
207 //*(MS_U16*)(0xbf206600+(0x18)*4) = 12; // 4'b1100 192
208
209 if((clock_level >>2) == 0 )
210 *(MS_U16*)(0xbf206600+(0x18)*4) = clock_level*4;
211 else
212 *(MS_U16*)(0xbf206600+(0x18)*4) = 8;
213 }
214 //MFE clock;
215 //*(MS_U16*)(0xbf200000+(0x1980+0x18)*4) = 2<<2; //2<<2
216 #elif defined(_MFE_T8_) &&defined(_MIPS_PLATFORM_)&&defined(_MFE_UTOPIA_)
217 if (is_off) {
218 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 1;//disable MFE clock
219 } else {
220 //*(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 0; // 4'b0000 123
221 //*(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 4; // 4'b0100 144
222 //*(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 8; // 4'b1000 172
223 //*(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; // 4'b1100 192
224 switch (clock_level)
225 {
226 case MFE_CLK_VERY_SLOW:
227 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 0; break;
228 case MFE_CLK_SLOW:
229 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 4; break;
230 case MFE_CLK_MEDIUM:
231 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 8; break;
232 case MFE_CLK_FAST:
233 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break;
234 default:
235 *(MS_U16*)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; break;
236 }
237 }
238 #endif
239
240 #endif // _FPGA_
241 }
242
MHal_MFE_SWReset(MFE_REG * mfe_reg)243 void MHal_MFE_SWReset(MFE_REG* mfe_reg)
244 {
245 MS_U16 temp;
246 mfe_reg->reg_mfe_g_soft_rstz = 1;
247 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)(""), 0, (MS_S8*)(""));
248 ReadRegMFE(0x0, &temp);
249 ms_dprintk(HAL_L1, "[HAL] SWReset reg00: %04x\n", (MS_U32)temp);
250 }
251
MHal_MFE_GetBitstreamEncodedLen(void)252 MS_U32 MHal_MFE_GetBitstreamEncodedLen(void)
253 {
254 MS_U16 reg_mfe_s_bsp_bit_cnt_high=0;
255 MS_U16 reg_mfe_s_bsp_bit_cnt_low=0;
256 MS_U32 nHwBytes;
257
258 // Read bit count
259 ReadRegMFE(0x42, ®_mfe_s_bsp_bit_cnt_low);
260 ReadRegMFE(0x43, ®_mfe_s_bsp_bit_cnt_high);
261 // Convert into byte count
262 nHwBytes = (((MS_U32)reg_mfe_s_bsp_bit_cnt_high<<16) + reg_mfe_s_bsp_bit_cnt_low ) >> 3;
263 return nHwBytes;
264 }
265
266
MHal_MFE_ClearIRQ(MS_U16 irq_bits)267 void MHal_MFE_ClearIRQ(MS_U16 irq_bits)
268 {
269 irq_bits = irq_bits&0x7f;
270 WriteRegMFE(0x1d, irq_bits, (MS_S8*)(""), 0, (MS_S8*)(""));
271 }
272
MHal_MFE_GetIRQ(MS_U16 * irq_bits)273 void MHal_MFE_GetIRQ(MS_U16 *irq_bits)
274 {
275 ReadRegMFE(0x1e, irq_bits);
276 ms_dprintk(HAL_L1, "[HAL] GetIRQ reg1e: 0x%x\n", (MS_S32)(*irq_bits));
277 }
278
MHal_MFE_CycleReport(void)279 MS_U32 MHal_MFE_CycleReport(void)
280 {
281 MS_U16 tmp_reg,tmp_reg1;
282 MS_U32 tCycles = 0;
283 ReadRegMFE(0x73, &tmp_reg);
284 tmp_reg = tmp_reg | 0x200; //enable total time;
285 WriteRegMFE(0x73, tmp_reg, (MS_S8*)(""), 0, (MS_S8*)(""));
286
287 ReadRegMFE(0x76, &tmp_reg);
288 ReadRegMFE(0x77, &tmp_reg1);
289
290 tCycles = ((tmp_reg1 & 0xff)<<16) | tmp_reg;
291 return tCycles;
292 }
293
MHal_MFE_set_outbitsbuf(MFE_REG * mfe_reg,OutBitSBUF * bitsbuf,MS_S32 outbufsize)294 void MHal_MFE_set_outbitsbuf(MFE_REG* mfe_reg, OutBitSBUF *bitsbuf, MS_S32 outbufsize)
295 {
296 #if defined(_MFE_M1_)||defined(_MFE_AGATE_)
297 SetObufAddr(mfe_reg, bitsbuf->start_addr, outbufsize, 0, 1);
298 #else
299 MS_U16 sadr_low, sadr_high, eadr_low, eadr_high;
300
301 sadr_low = LOWORD(bitsbuf->start_addr>>MIU_SHIFT);
302 sadr_high = HIWORD(bitsbuf->start_addr>>MIU_SHIFT);
303 eadr_low = LOWORD(((bitsbuf->end_addr)>>MIU_SHIFT)-1);
304 eadr_high = HIWORD(((bitsbuf->end_addr)>>MIU_SHIFT)-1);
305 SetObufAddr(mfe_reg, sadr_low, sadr_high, eadr_low, eadr_high);
306 #endif
307 }
308
MHal_MFE_SetCLKCTL(MFE_REG * mfe_reg)309 void MHal_MFE_SetCLKCTL(MFE_REG* mfe_reg)
310 {
311 WriteRegMFE(0x0a, (MS_U16)mfe_reg->reg0a, (MS_S8*)(""), 0, (MS_S8*)(""));
312 }
313
MHal_MFE_ResetReg(MFE_REG * mfe_reg)314 void MHal_MFE_ResetReg(MFE_REG* mfe_reg)
315 {
316 memset(mfe_reg, 0, sizeof(MFE_REG));
317 }
318
MHal_MFE_GetCRC(MS_U8 checksum_HW[8])319 void MHal_MFE_GetCRC(MS_U8 checksum_HW[8])
320 {
321 MS_S32 i;
322 MS_U16 u16Reg1;
323
324 ReadRegMFE(0x73, &u16Reg1);
325 u16Reg1 = u16Reg1 & 0xFDFF;
326 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)(""));
327
328 //call HW CRC64
329 for(i=0;i<4;i++){
330 ReadRegMFE(0x76+i, &u16Reg1);
331 checksum_HW[2*i] = (MS_U8)(u16Reg1&0xFF);
332 checksum_HW[2*i+1] = u16Reg1>>8;
333 }
334
335 ReadRegMFE(0x73, &u16Reg1);
336 u16Reg1 = u16Reg1 | 0x0100;
337 WriteRegMFE(0x73, u16Reg1, (MS_S8*)(""), 0, (MS_S8*)(""));
338 }
339
340
341