105 void WriteRegMFE(MFE_U32 u32Address, MFE_U16 val, char *str1, int num, char *str3)  in WriteRegMFE()  function
158     WriteRegMFE(0x3c, mfe_reg.reg3c, "", 0, "");  in SetObufAddr()
159     WriteRegMFE(0x3d, mfe_reg.reg3d, "", 0, "");  in SetObufAddr()
160     WriteRegMFE(0x3e, mfe_reg.reg3e, "", 0, "");  in SetObufAddr()
161     WriteRegMFE(0x3f, mfe_reg.reg3f, "", 0, "");  in SetObufAddr()
166     WriteRegMFE(0x3b, mfe_reg.reg3b, "", 0, "");  in SetObufAddr()
173     WriteRegMFE(0x1d, mfe_reg.reg1d, "", 0, "");  in ClearBsfFullIRQ()
190     WriteRegMFE(0x1d, mfe_reg.reg1d, "", 0, "");  in ClearIRQ()
208     WriteRegMFE(0x00, mfe_reg.reg00, "", 0, "");  in Enable_HW()
218     WriteRegMFE(0x0, mfe_reg.reg00, "[%d] reg00", nRegWriteCount++, "SW reset 1");  in ResetAllRegs()
220     WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "tbc_mode=0");  in ResetAllRegs()
221     WriteRegMFE(0x4, mfe_reg.reg04, "[%d] reg04", nRegWriteCount++, "er_bs mode threshold");  in ResetAllRegs()
223     WriteRegMFE(0x5, mfe_reg.reg05, "[%d] reg05", nRegWriteCount++, "inter prediction preference");  in ResetAllRegs()
225     WriteRegMFE(0x16, mfe_reg.reg16, "[%d] reg16", nRegWriteCount++, "clock gating=0");  in ResetAllRegs()
230     WriteRegMFE(0x18, mfe_reg.reg18, "[%d] reg18", nRegWriteCount++, "JPE encode mode");  in ResetAllRegs()
233     WriteRegMFE(0x19, mfe_reg.reg19, "[%d] reg19", nRegWriteCount++, "value");  in ResetAllRegs()
234     WriteRegMFE(0x1a, mfe_reg.reg1a, "[%d] reg1a", nRegWriteCount++, "value");  in ResetAllRegs()
235     WriteRegMFE(0x1b, mfe_reg.reg1b, "[%d] reg1b", nRegWriteCount++, "value");  in ResetAllRegs()
239     WriteRegMFE(0x20, mfe_reg.reg20, "[%d] reg20", nRegWriteCount++, "ME partition setting");  in ResetAllRegs()
242     WriteRegMFE(0x21, mfe_reg.reg21, "[%d] reg21", nRegWriteCount++, "value");  in ResetAllRegs()
244     WriteRegMFE(0x22, mfe_reg.reg22, "[%d] reg22", nRegWriteCount++, "me search range max depth");  in ResetAllRegs()
246     WriteRegMFE(0x23, mfe_reg.reg23, "[%d] reg23", nRegWriteCount++, "me mvx");  in ResetAllRegs()
248     WriteRegMFE(0x24, mfe_reg.reg24, "[%d] reg24", nRegWriteCount++, "me mvy");  in ResetAllRegs()
252     WriteRegMFE(0x25, mfe_reg.reg25, "[%d] reg25", nRegWriteCount++, "FME");  in ResetAllRegs()
255     WriteRegMFE(0x26, mfe_reg.reg26, "[%d] reg26", nRegWriteCount++, "MBR: mbbits");  in ResetAllRegs()
256     WriteRegMFE(0x27, mfe_reg.reg27, "[%d] reg27", nRegWriteCount++, "MBR: frame qstep");  in ResetAllRegs()
257     WriteRegMFE(0x29, mfe_reg.reg29, "[%d] reg29", nRegWriteCount++, "264 qp-offset");  in ResetAllRegs()
260     WriteRegMFE(0x2a, mfe_reg.reg2a, "[%d] reg2a", nRegWriteCount++, "QP min/max");  in ResetAllRegs()
262     WriteRegMFE(0x6e, mfe_reg.reg6e, "[%d] reg6e", nRegWriteCount++, "QStep min");  in ResetAllRegs()
264     WriteRegMFE(0x6f, mfe_reg.reg6f, "[%d] reg6f", nRegWriteCount++, "QStep max");  in ResetAllRegs()
270     WriteRegMFE(0x2b, mfe_reg.reg2b, "[%d] reg2b", nRegWriteCount++, "ieap");  in ResetAllRegs()
273     WriteRegMFE(0x2c, mfe_reg.reg2c, "[%d] reg2c", nRegWriteCount++, "Last zigzag");  in ResetAllRegs()
276     WriteRegMFE(0x2d, mfe_reg.reg2d, "[%d] reg2d", nRegWriteCount, "");  in ResetAllRegs()
277     WriteRegMFE(0x2e, mfe_reg.reg2e, "[%d] reg2e", nRegWriteCount, "");  in ResetAllRegs()
278     WriteRegMFE(0x2f, mfe_reg.reg2f, "[%d] reg2f", nRegWriteCount, "");  in ResetAllRegs()
279     WriteRegMFE(0x30, mfe_reg.reg30, "[%d] reg30", nRegWriteCount, "");  in ResetAllRegs()
280     WriteRegMFE(0x31, mfe_reg.reg31, "[%d] reg31", nRegWriteCount, "");  in ResetAllRegs()
282     WriteRegMFE(0x32, mfe_reg.reg32, "[%d] reg32", nRegWriteCount, "");  in ResetAllRegs()
283     WriteRegMFE(0x33, mfe_reg.reg33, "[%d] reg33", nRegWriteCount, "");  in ResetAllRegs()
284     WriteRegMFE(0x34, mfe_reg.reg34, "[%d] reg34", nRegWriteCount, "");  in ResetAllRegs()
287     WriteRegMFE(0x37, mfe_reg.reg37, "[%d] reg37", nRegWriteCount++, "MPEG4 MDC");  in ResetAllRegs()
288     WriteRegMFE(0x38, mfe_reg.reg38, "[%d] reg38", nRegWriteCount++, "MPEG4: vop_time_increment");  in ResetAllRegs()
289     WriteRegMFE(0x39, mfe_reg.reg39, "[%d] reg39", nRegWriteCount++, "value");  in ResetAllRegs()
291     WriteRegMFE(0x3a, mfe_reg.reg3a, "[%d] reg3a", nRegWriteCount++, "value");  in ResetAllRegs()
294     WriteRegMFE(0x46, mfe_reg.reg46, "[FDC %d] reg46", nRegWriteCount++, "fdc bs");  in ResetAllRegs()
295     WriteRegMFE(0x47, mfe_reg.reg47, "[FDC %d] reg47", nRegWriteCount++, "fdc len");  in ResetAllRegs()
296     WriteRegMFE(0x48, mfe_reg.reg48, "[FDC %d] reg48", nRegWriteCount++, "fdc vld");  in ResetAllRegs()
298     WriteRegMFE(0x49, mfe_reg.reg49, "[Table %d] reg49", nRegWriteCount++, "table address");  in ResetAllRegs()
299     WriteRegMFE(0x4a, mfe_reg.reg4a, "[Table %d] reg4a", nRegWriteCount++, "table write data");  in ResetAllRegs()
302     WriteRegMFE(0x70, mfe_reg.reg70, "[%d] reg70", nRegWriteCount++, "");  in ResetAllRegs()
303     WriteRegMFE(0x71, mfe_reg.reg71, "[%d] reg71", nRegWriteCount++, "");  in ResetAllRegs()
304     WriteRegMFE(0x72, mfe_reg.reg72, "[%d] reg72", nRegWriteCount++, "");  in ResetAllRegs()
305     WriteRegMFE(0x73, mfe_reg.reg73, "[%d] reg73", nRegWriteCount++, "");  in ResetAllRegs()
311     WriteRegMFE(0x71, mfe_reg.reg71, "[%d] reg71", 0, "reg_mfe_g_debug_trig_mbx");  in TestStopAtMb()
313     WriteRegMFE(0x72, mfe_reg.reg72, "[%d] reg72", 0, "reg_mfe_g_debug_trig_mby");  in TestStopAtMb()
315     WriteRegMFE(0x2d, mfe_reg.reg2d, "[%d] reg2d", 0, "reg_mfe_s_txip_sng_mb=1");  in TestStopAtMb()
318     WriteRegMFE(0x73, mfe_reg.reg73, "[%d] reg73", 0, "reg_mfe_g_debug_trig_mode=1");  in TestStopAtMb()
320     WriteRegMFE(0x70, mfe_reg.reg70, "[%d] reg70", 0, "reg_mfe_g_debug_trig_cycle=0");  in TestStopAtMb()
326     WriteRegMFE(0x2d, mfe_reg.reg2d, "[%d] reg2d", 0, "reg_mfe_s_txip_sng_set=1");  in TestStop()
352         WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg3", nRegWriteCount++, "tbc_mode=0");  in WriteQTable()
359             WriteRegMFE(0x4a, mfe_reg.reg4a, "[%d] reg4a", nRegWriteCount++, "table write data");  in WriteQTable()
363             WriteRegMFE(0x49, mfe_reg.reg49, "[%d] reg49", nRegWriteCount++, "table address");  in WriteQTable()
364             WriteRegMFE(0x48, mfe_reg.reg48, "[%d] reg48", nRegWriteCount++, "table write enable");  in WriteQTable()
379             WriteRegMFE(0x49, RegWQT.reg49,"",0,"");  in WriteQTable()
394 …      WriteRegMFE(0x4a, mfe_reg.reg4a, "[%d] reg4a", nRegWriteCount++, "table write data (inter)");  in WriteQTable()
398             WriteRegMFE(0x49, mfe_reg.reg49, "[%d] reg49", nRegWriteCount++, "table address");  in WriteQTable()
399             WriteRegMFE(0x48, mfe_reg.reg48, "[%d] reg48", nRegWriteCount++, "table write enable");  in WriteQTable()
415             WriteRegMFE(0x49, RegWQT.reg49,"",0,"");  in WriteQTable()
427         WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "tbc_mode=1");  in WriteQTable()
436         WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "tbc_mode=0");  in WriteQTable()
439         WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "tbc_mode=1");  in WriteQTable()
451         WriteRegMFE(0x03, RegQT_RB_REG03.reg03,"",0,"");  in WriteQTable()
458         WriteRegMFE(0x49, RegWQT_RB.reg49,"",0,"");  in WriteQTable()
472             WriteRegMFE(0x49, RegWQT_RB.reg49, "", 0, "");  in WriteQTable()
475             WriteRegMFE(0x48, mfe_reg.reg48, "[%d] reg48", nRegWriteCount++, "table write enable");  in WriteQTable()
502             WriteRegMFE(0x49, RegWQT_RB.reg49,"",0,"");  in WriteQTable()
505             WriteRegMFE(0x48, mfe_reg.reg48, "[%d] reg48", nRegWriteCount++, "table write enable");  in WriteQTable()
531         WriteRegMFE(0x03, RegQT_RB_REG03.reg03,"",0,"");  in WriteQTable()
578     WriteRegMFE(0x47, mfe_reg.reg47, "[FDC %d] reg47", nRegWriteNum++, "fdc round count");  in PutFDC()
589         WriteRegMFE(0x46, mfe_reg.reg46, "[FDC %d] reg46", nRegWriteNum++, "fdc bs");  in PutFDC()
590         WriteRegMFE(0x47, mfe_reg.reg47, "[FDC %d] reg47", nRegWriteNum++, "fdc len");  in PutFDC()
591         WriteRegMFE(0x48, mfe_reg.reg48, "[FDC %d] reg48", nRegWriteNum++, "fdc vld");  in PutFDC()
609         WriteRegMFE(0x48, RegFdc.reg48,"reg48",nRegWriteNum,"");  in PutFDC()
631     WriteRegMFE(0x46, mfe_reg.reg46, "[FDC %d] reg46", nRegWriteNum++, "fdc bs");  in PutFDC()
632     WriteRegMFE(0x47, mfe_reg.reg47, "[FDC %d] reg47", nRegWriteNum++, "fdc len");  in PutFDC()
633     WriteRegMFE(0x48, mfe_reg.reg48, "[FDC %d] reg48", nRegWriteNum++, "fdc vld");  in PutFDC()
651     WriteRegMFE(0x48, RegFdc.reg48,"reg48",nRegWriteNum,"");  in PutFDC()