1 //<MStar Software>
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77 //<MStar Software>
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MFE_chip.h"
96 #include "mfe_common.h"
97 #include "mfe_type.h"
98 #include "ms_dprintf.h"
99
100 #if defined(_MIPS_PLATFORM_)&&defined(_MFE_T8_)&&defined(_KERNEL_MODE_)
101 //#include <linux/kernel.h>
102 //#include <linux/string.h>
103 //#include "chip_int.h"
104 //#include <linux/interrupt.h>
105 #else
106 #include <string.h>
107 #endif
108
109
110 #include "mhal_mfe.h"
111 #include "mfe_reg.h"
112 #ifdef _AEON_PLATFORM_
113 #ifdef _MFE_T8_
114 #include "mdrv_irq.h"
115 #include "drvISR.h"
116 #endif
117 #elif defined(_WIN32)
118 #include <windows.h>
119 #include "pthread.h"
120 #endif //_AEON_PLATFORM_
121
122 #ifdef _MIPS_PLATFORM_
123 #ifdef _MFE_BIG2_
124 #include "utility.h"
125 #include "shellcfg.h"
126
127 #if !defined(_MFE_T8_)
128 #ifdef _ENABLE_ISR_
129 #include "cyg/hal/hal_intr.h"
130 #endif //_ENABLE_ISR_
131 #endif
132
133 #endif //MFE_BIG2
134 #endif //_MIPS_PLATFORM_
135
136 #ifdef _FPGA_
137 #include "fpga_def.h"
138 #endif
139
140
141
142 MFE_REG mfe_reg;
143
144 #if defined(_MFE_T8_) && defined(_MIPS_PLATFORM_)&& !defined(_KERNEL_MODE_)
145 unsigned int u32MFERegOSBase;
146 #endif
147
148 // RIU base
149 #if defined(_AEON_PLATFORM_) && defined(_MFE_T8_)
150 MFE_U32 RIU_BASE = 0xA0000000;
151 #elif defined(_AEON_PLATFORM_)
152 MFE_U32 RIU_BASE = 0xA0000000;
153 //extern U8 FSwrite_ready;
154 #elif defined(_MFE_BIG2_) && defined(_MIPS_PLATFORM_)
155 MFE_U32 RIU_BASE = 0xBF834000;
156 #elif defined(_MFE_T8_) && defined(_MIPS_PLATFORM_)&&defined(_KERNEL_MODE_)
157 MFE_U32 RIU_BASE = 0xBF200000; //CH4
158 #elif defined(_MFE_T8_) && defined(_MIPS_PLATFORM_)
159 // #define RIU_BASE U32MFERegOSBase //CH4
160 #elif defined(_HIF_) && defined(_MFE_BIG2_)
161 MFE_U32 RIU_BASE = 0xA0000000;
162 #elif defined(_FPGA_)
163 MFE_U32 RIU_BASE = 0xA0000000;
164 #else //if defined(_WIN32)//defined(_BCB_PLATFORM_)
165 unsigned short REG_BANK_MFE[0x100];
166 #endif
167
168 #if defined(_MFE_T8_) && defined(_MIPS_PLATFORM_)&& !defined(_KERNEL_MODE_)
169
MHAL_MFE_InitRegBase(MFE_U32 U32RegBase)170 void MHAL_MFE_InitRegBase(MFE_U32 U32RegBase)
171 {
172 ms_dprintk(HAL_L1,"HAL_MFE_InitRegBase 0x%X\n", (unsigned int)U32RegBase);
173 u32MFERegOSBase = U32RegBase;
174 }
175 #endif
176
177
MHal_MFE_PowerOff(MFE_U32 is_off,MFE_U32 clock_level)178 void MHal_MFE_PowerOff(MFE_U32 is_off,MFE_U32 clock_level)
179 {
180 #ifndef _FPGA_
181 #if defined(_MFE_BIG2_)&&defined(_MIPS_PLATFORM_) && !defined(Enable_CLKMGR)
182 if (is_off) {
183 *(short *)(0xBF8000C0) |= (0<<2); // speed down to 15M Hz
184 } else
185 *(short *)(0xBF8000C0) |= (6<<2); //ken: speed up to 156M Hz
186 #elif defined(_MFE_T8_) &&defined(_MIPS_PLATFORM_)&&defined(_KERNEL_MODE_)
187 if (is_off) {
188 *(unsigned short *)(0xbf206600+(0x18)*4) = 1;//disable MFE clock
189 } else {
190 //*(unsigned short *)(0xbf206600+(0x18)*4) = 0; // 4'b0000 123
191 //*(unsigned short *)(0xbf206600+(0x18)*4) = 4; // 4'b0100 144
192 //*(unsigned short *)(0xbf206600+(0x18)*4) = 8; // 4'b1000 172
193 //*(unsigned short *)(0xbf206600+(0x18)*4) = 12; // 4'b1100 192
194
195 if((clock_level >>2) == 0 )
196 *(unsigned short *)(0xbf206600+(0x18)*4) = clock_level*4;
197 else
198 *(unsigned short *)(0xbf206600+(0x18)*4) = 8;
199 }
200 //MFE clock;
201 //*(unsigned short *)(0xbf200000+(0x1980+0x18)*4) = 2<<2; //2<<2
202 #elif defined(_MFE_T8_) &&defined(_MIPS_PLATFORM_)
203 if (is_off) {
204 *(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 1;//disable MFE clock
205 } else {
206 //*(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 0; // 4'b0000 123
207 //*(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 4; // 4'b0100 144
208 //*(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 8; // 4'b1000 172
209 //*(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 12; // 4'b1100 192
210
211 if((clock_level >>2) == 0 )
212 *(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = clock_level*4;
213 else
214 *(unsigned short *)(T8_RIU_BASE+(0x1980+0x18)*4) = 8;
215 }
216 #endif
217
218 #endif // _FPGA_
219 }
220
MHal_MFE_SWReset(void)221 void MHal_MFE_SWReset(void)
222 {
223 MFE_U16 temp;
224 mfe_reg.reg_mfe_g_soft_rstz = 1;
225 WriteRegMFE(0x0, mfe_reg.reg00, "", 0, "");
226 ReadRegMFE(0x0, &temp);
227 ms_dprintk(HAL_L1, "[HAL] SWReset reg00: %04x\n", (unsigned int)temp);
228 }
229
MHal_MFE_GetBitstreamEncodedLen(void)230 MFE_U32 MHal_MFE_GetBitstreamEncodedLen(void)
231 {
232 MFE_REG reg;
233 int nHwBytes;
234
235 // Read bit count
236 reg.reg42 = 0;
237 reg.reg43 = 0;
238 ReadRegMFE(0x42, ®.reg42);
239 ReadRegMFE(0x43, ®.reg43);
240 // Convert into byte count
241 nHwBytes = (((int)reg.reg_mfe_s_bsp_bit_cnt_high<<16) + reg.reg_mfe_s_bsp_bit_cnt_low ) >> 3;
242 return nHwBytes;
243 }
244
245 /*
246 void MHal_MFE_SetIrqMask(MFE_REG* pMfeReg, U16 mask)
247 {
248 pMfeReg->reg_mfe_g_irq_mask = mask&0xff;
249 WriteRegMFE(0x1c, mfe_reg.reg1c, "", 0, "");
250 }
251 */
252
MHal_MFE_ClearIRQ(MFE_U16 irq_bits)253 void MHal_MFE_ClearIRQ(MFE_U16 irq_bits)
254 {
255 irq_bits = irq_bits&0x7f;
256 WriteRegMFE(0x1d, irq_bits, "", 0, "");
257 }
258
MHal_MFE_GetIRQ(MFE_U16 * irq_bits)259 void MHal_MFE_GetIRQ(MFE_U16 *irq_bits)
260 {
261 ReadRegMFE(0x1e, irq_bits);
262 ms_dprintk(HAL_L1, "[HAL] GetIRQ reg1e: 0x%x\n", (int)(*irq_bits));
263 }
264
MHal_MFE_set_outbitsbuf(OutBitSBUF * bitsbuf)265 void MHal_MFE_set_outbitsbuf(OutBitSBUF *bitsbuf)
266 {
267 MFE_WORD sadr_low, sadr_high, eadr_low, eadr_high;
268
269 sadr_low = LOWORD(bitsbuf->start_addr>>MIU_SHIFT);
270 sadr_high = HIWORD(bitsbuf->start_addr>>MIU_SHIFT);
271 eadr_low = LOWORD(((bitsbuf->end_addr)>>MIU_SHIFT)-1);
272 eadr_high = HIWORD(((bitsbuf->end_addr)>>MIU_SHIFT)-1);
273 SetObufAddr(sadr_low, sadr_high, eadr_low, eadr_high);
274 }
275
MHal_MFE_SetCLKCTL(void)276 void MHal_MFE_SetCLKCTL(void)
277 {
278 WriteRegMFE(0x0a, (MFE_U16)mfe_reg.reg0a, "", 0, "");
279 }
280
MHal_MFE_ResetReg()281 void MHal_MFE_ResetReg()
282 {
283 memset(&mfe_reg, 0, sizeof(MFE_REG));
284 }
285
MHal_MFE_GetCRC(MFE_U8 checksum_HW[8])286 void MHal_MFE_GetCRC(MFE_U8 checksum_HW[8])
287 {
288 int i;
289 MFE_U16 u16Reg1;
290
291 ReadRegMFE(0x73, &u16Reg1);
292 u16Reg1 = u16Reg1 & 0xFDFF;
293 WriteRegMFE(0x73, u16Reg1, "", 0, "");
294
295 //call HW CRC64
296 for(i=0;i<4;i++){
297 ReadRegMFE(0x76+i, &u16Reg1);
298 checksum_HW[2*i] = (MFE_U8)(u16Reg1&0xFF);
299 checksum_HW[2*i+1] = u16Reg1>>8;
300 }
301
302 ReadRegMFE(0x73, &u16Reg1);
303 u16Reg1 = u16Reg1 | 0x0100;
304 WriteRegMFE(0x73, u16Reg1, "", 0, "");
305 }
306
MHal_MFE_Enable_MIU_Protection(int MIU_TEST_MODE,MFE_CONFIG * pConfig)307 void MHal_MFE_Enable_MIU_Protection(int MIU_TEST_MODE,MFE_CONFIG* pConfig)
308 {
309
310 MFE_REG mfe_reg;
311 int width, height;
312 BufInfo* pBufInfo;
313
314
315 pBufInfo = &pConfig->ctxBufInfo;
316 width = pConfig->nBufWidth;
317 height = pConfig->nBufHeight;
318
319 #ifdef _MFE_A3_
320 mfe_reg.reg_mfe_s_marb_miu_bound_en_0 = 0x1;
321 mfe_reg.reg_mfe_s_marb_miu_bound_en_1 = 0x1;
322 mfe_reg.reg_mfe_s_marb_miu_bound_en_2 = (pBufInfo->m_bEnableMvStore==1) ? 1 : 0;
323 mfe_reg.reg_mfe_s_marb_miu_bound_en_3 = 0x1;
324
325 ms_dprintk(HAL_L1, "MIU PROTECTION reg_mfe_s_marb_miu_bound_en[0 to 3] = %x %x %x %x\n", \
326 mfe_reg.reg_mfe_s_marb_miu_bound_en_0,mfe_reg.reg_mfe_s_marb_miu_bound_en_1, \
327 mfe_reg.reg_mfe_s_marb_miu_bound_en_2,mfe_reg.reg_mfe_s_marb_miu_bound_en_3);
328 #else
329 if (pBufInfo->m_bEnableMvStore==1)
330 mfe_reg.reg_mfe_s_marb_miu_bound_en = 0xF; // (1111) 4 mode
331 else
332 mfe_reg.reg_mfe_s_marb_miu_bound_en = 0xB; // (1011) 3 mode without MV
333
334 ms_dprintk(HAL_L1, "MIU PROTECTION reg_mfe_s_marb_miu_bound_en = %x\n",mfe_reg.reg_mfe_s_marb_miu_bound_en);
335 #endif
336
337
338
339
340 // MIU_TEST_MODE = 0;
341
342 //BSP
343 // mfe_reg.reg_mfe_s_marb_miu_bound_en = 1;
344
345 mfe_reg.reg_mfe_s_marb_ubound_0_low = (MFE_U16)(((pBufInfo->m_nOutBufAddr[pBufInfo->m_nOutBuffer-1].miuAddress+pBufInfo->m_OutBufferSize)>>3)&0xFFFF);
346 mfe_reg.reg_mfe_s_marb_ubound_0_high = (MFE_U16)((pBufInfo->m_nOutBufAddr[pBufInfo->m_nOutBuffer-1].miuAddress+pBufInfo->m_OutBufferSize)>>(3+16));
347 mfe_reg.reg_mfe_s_marb_lbound_0_low = (MFE_U16)(((pBufInfo->m_nOutBufAddr[0].miuAddress+MIU_TEST_MODE*8)>>3)&0xFFFF);
348 mfe_reg.reg_mfe_s_marb_lbound_0_high = (MFE_U16)((pBufInfo->m_nOutBufAddr[0].miuAddress+MIU_TEST_MODE*8)>>(3+16));
349
350
351 //BSP end
352
353 // MIU_TEST_MODE = 1;
354 //MC
355 // mfe_reg.reg_mfe_s_marb_miu_bound_en = 2;
356
357 //upper bound: Chrome rec addr + ((W/2)*(H/2) ) * 2
358 //lower bound: Luma rec addr
359 mfe_reg.reg_mfe_s_marb_ubound_1_low = (MFE_U16)(((pBufInfo->m_nRecCAddr.miuAddress+height*width/2 -MIU_TEST_MODE*8)>>3)&0xFFFF);
360 mfe_reg.reg_mfe_s_marb_ubound_1_high = (MFE_U16)((pBufInfo->m_nRecCAddr.miuAddress+height*width/2 -MIU_TEST_MODE*8)>>(3+16));
361 mfe_reg.reg_mfe_s_marb_lbound_1_low = (MFE_U16)(((pBufInfo->m_nRecYAddr.miuAddress)>>3)&0xFFFF);
362 mfe_reg.reg_mfe_s_marb_lbound_1_high = (MFE_U16)((pBufInfo->m_nRecYAddr.miuAddress)>>(3+16));
363
364
365 //MC end
366 // MIU_TEST_MODE = 0;
367 //MV
368 //upper bound: start addr + (number of MB)*8
369 //lower bound:start addr
370 mfe_reg.reg_mfe_s_marb_ubound_2_low = (MFE_U16)(((pBufInfo->m_nMvStoreAddr.miuAddress+ (height/MIU_MB_SIZE)*(width/MIU_MB_SIZE)*8 -MIU_TEST_MODE*8)>>3)&0xFFFF);
371 mfe_reg.reg_mfe_s_marb_ubound_2_high = (MFE_U16)((pBufInfo->m_nMvStoreAddr.miuAddress+ (height/MIU_MB_SIZE)*(width/MIU_MB_SIZE)*8 -MIU_TEST_MODE*8)>>(3+16));
372 mfe_reg.reg_mfe_s_marb_lbound_2_low = (MFE_U16)(((pBufInfo->m_nMvStoreAddr.miuAddress)>>3)&0xFFFF);
373 mfe_reg.reg_mfe_s_marb_lbound_2_high = (MFE_U16)((pBufInfo->m_nMvStoreAddr.miuAddress)>>(3+16));
374
375
376 //MV end
377
378 //GN
379 // mfe_reg.reg_mfe_s_marb_miu_bound_en = 8;
380
381 //upper bound: start addr + ( #.MB per width)*64
382 //lower bound:start addr
383 mfe_reg.reg_mfe_s_marb_ubound_3_low = (MFE_U16)(((pBufInfo->m_nGNAddr.miuAddress + (width/MIU_MB_SIZE)*64 -MIU_TEST_MODE*64)>>3)&0xFFFF);
384 mfe_reg.reg_mfe_s_marb_ubound_3_high = (MFE_U16)((pBufInfo->m_nGNAddr.miuAddress + (width/MIU_MB_SIZE)*64 -MIU_TEST_MODE*64)>>(3+16));
385 mfe_reg.reg_mfe_s_marb_lbound_3_low = (MFE_U16)(((pBufInfo->m_nGNAddr.miuAddress)>>3)&0xFFFF);
386 mfe_reg.reg_mfe_s_marb_lbound_3_high = (MFE_U16)((pBufInfo->m_nGNAddr.miuAddress)>>(3+16));
387
388 //GN end
389
390
391
392 WriteRegMFE(0x58, mfe_reg.reg58, "", 1, "bsp ubound");
393 WriteRegMFE(0x59, mfe_reg.reg59, "[%d]", 1, "en & bsp ubound");
394 WriteRegMFE(0x5a, mfe_reg.reg5a, "", 1, "bsp lbound");
395 WriteRegMFE(0x5b, mfe_reg.reg5b, "", 1, "bsp lbound");
396
397 WriteRegMFE(0x5c, mfe_reg.reg5c, "", 1, "rec ubound");
398 WriteRegMFE(0x5d, mfe_reg.reg5d, "[%d]", 1, "rec ubound");
399 WriteRegMFE(0x5e, mfe_reg.reg5e, "", 1, "rec lbound");
400 WriteRegMFE(0x5f, mfe_reg.reg5f, "", 1, "rec lbound");
401
402 WriteRegMFE(0x60, mfe_reg.reg60, "", 1, "mv obuf ubound");
403 WriteRegMFE(0x61, mfe_reg.reg61, "[%d]", 1, "mv obuf ubound");
404 WriteRegMFE(0x62, mfe_reg.reg62, "", 1, "mv obuf lbound");
405 WriteRegMFE(0x63, mfe_reg.reg63, "", 1, "mv obuf lbound");
406
407 WriteRegMFE(0x64, mfe_reg.reg64, "", 1, "mv obuf ubound");
408 WriteRegMFE(0x65, mfe_reg.reg65, "[%d]", 1, "mv obuf ubound");
409 WriteRegMFE(0x66, mfe_reg.reg66, "", 1, "mv obuf lbound");
410 WriteRegMFE(0x67, mfe_reg.reg67, "", 1, "mv obuf lbound");
411
412
413 }
414
MHal_MFE_Enable_MIU_Protection_Check(int MIU_TEST_MODE,int TYPE)415 void MHal_MFE_Enable_MIU_Protection_Check(int MIU_TEST_MODE,int TYPE)
416 {
417
418 ms_dprintk(HAL_L1, "TEST_MIU_PROTECTION\n");
419
420 //MV
421 if(TYPE == 3){
422 MIU_PRO_REG miu_reg59;
423 MIU_PRO_REG2 miu_reg19;
424
425
426 ReadRegMFE(0x19, &miu_reg19.reg19);
427 if(miu_reg19.reg_mfe_g_mp4_direct_mvstore==1){
428 ReadRegMFE(0x59, &miu_reg59.reg59);
429 if(MIU_TEST_MODE != miu_reg59.reg_mfe_s_marb_miu_bound_err ){
430 ms_dprintk(HAL_L2, "\n[error] TEST_MIU_PROTECTION reg_mfe_s_marb_miu_bound_err = %d\n",miu_reg59.reg_mfe_s_marb_miu_bound_err);
431 }
432 else
433 ms_dprintk(HAL_L2, "\nTEST_MIU_PROTECTION reg_mfe_s_marb_miu_bound_err = %d\n",miu_reg59.reg_mfe_s_marb_miu_bound_err);
434
435
436 }
437 else
438 ms_dprintk(HAL_L2, "\n no test MV miu_PROTECTION in this frame.\n");
439 }
440
441 else
442 {
443 MIU_PRO_REG miu_reg59;
444 ReadRegMFE(0x59, &miu_reg59.reg59);
445 //read HW error flag
446 if(MIU_TEST_MODE != miu_reg59.reg_mfe_s_marb_miu_bound_err ){
447 ms_dprintk(HAL_L2, "\n[error] TEST_MIU_PROTECTION reg_mfe_s_marb_miu_bound_err = %d\n",miu_reg59.reg_mfe_s_marb_miu_bound_err);
448 }
449 else
450 ms_dprintk(HAL_L2, "\nTEST_MIU_PROTECTION reg_mfe_s_marb_miu_bound_err = %d\n",miu_reg59.reg_mfe_s_marb_miu_bound_err);
451
452 }
453
454
455 }
456
457
458