Searched refs:VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK (Results 1 – 6 of 6) sorted by relevance
| /utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/vpu_v3/ |
| H A D | regVPU_EX.h | 490 #define VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK BMASK(11:8) macro
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| H A D | halVPU_EX.c | 1184 …_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK); in _VPU_EX_InitAddressLimiter()
1193 …SS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK); in _VPU_EX_InitAddressLimiter()
1202 …RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_REPLACE_ADDR, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK); in _VPU_EX_InitAddressLimiter()
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| /utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/vpu_v3/ |
| H A D | regVPU_EX.h | 490 #define VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK BMASK(11:8) macro
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| H A D | halVPU_EX.c | 1180 …_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK); in _VPU_EX_InitAddressLimiter()
1189 …SS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK); in _VPU_EX_InitAddressLimiter()
1198 …RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_REPLACE_ADDR, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK); in _VPU_EX_InitAddressLimiter()
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| /utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/vpu_v3/ |
| H A D | regVPU_EX.h | 490 #define VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK BMASK(11:8) macro
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| H A D | halVPU_EX.c | 1183 …_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_START, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK); in _VPU_EX_InitAddressLimiter()
1192 …SS_RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR0_END, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK); in _VPU_EX_InitAddressLimiter()
1201 …RANGE0_CFG, VDR2_D_ACCESS_RANGE0_CFG_WRITE_REPLACE_ADDR, VDR2_D_ACCESS_RANGE0_CFG_WRITE_ADDR_MASK); in _VPU_EX_InitAddressLimiter()
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