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Searched refs:REG_UPDATE_DC1_CW (Results 1 – 25 of 34) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/mvop/hal/mustang/mvop/
H A DhalMVOP.c3849 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
3850 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
3876 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_SYNC_CW); in HAL_MVOP_SubSetSynClk()
3877 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_SYNC_CW); in HAL_MVOP_SubSetSynClk()
H A DregMVOP.h406 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE0) macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/macan/mvop/
H A DregMVOP.h426 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE1) macro
H A DhalMVOP.c4633 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4634 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4668 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_SYNC_CW); in HAL_MVOP_SubSetSynClk()
4669 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_SYNC_CW); in HAL_MVOP_SubSetSynClk()
/utopia/UTPA2-700.0.x/modules/mvop/hal/messi/mvop/
H A DregMVOP.h424 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE1) macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/manhattan/mvop/
H A DregMVOP.h417 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE1) macro
H A DhalMVOP.c4364 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4365 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4399 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_SYNC_CW); in HAL_MVOP_SubSetSynClk()
4400 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_SYNC_CW); in HAL_MVOP_SubSetSynClk()
/utopia/UTPA2-700.0.x/modules/mvop/hal/M7821/mvop/
H A DregMVOP.h431 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE1) macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/mainz/mvop/
H A DregMVOP.h424 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE1) macro
H A DhalMVOP.c4770 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4771 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4808 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_SYNC_CW); in HAL_MVOP_SubSetSynClk()
4809 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_SYNC_CW); in HAL_MVOP_SubSetSynClk()
/utopia/UTPA2-700.0.x/modules/mvop/hal/mooney/mvop/
H A DregMVOP.h447 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE1) macro
H A DhalMVOP.c4485 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4486 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4520 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_SYNC_CW); in HAL_MVOP_SubSetSynClk()
4521 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_SYNC_CW); in HAL_MVOP_SubSetSynClk()
/utopia/UTPA2-700.0.x/modules/mvop/hal/maserati/mvop/
H A DregMVOP.h432 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE1) macro
H A DhalMVOP.c4842 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4843 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4877 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_SYNC_CW); in HAL_MVOP_SubSetSynClk()
4878 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_SYNC_CW); in HAL_MVOP_SubSetSynClk()
/utopia/UTPA2-700.0.x/modules/mvop/hal/M7621/mvop/
H A DregMVOP.h444 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE1) macro
H A DhalMVOP.c4821 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4822 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4856 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_SYNC_CW); in HAL_MVOP_SubSetSynClk()
4857 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_SYNC_CW); in HAL_MVOP_SubSetSynClk()
/utopia/UTPA2-700.0.x/modules/mvop/hal/M5621/mvop/
H A DregMVOP.h436 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE0) macro
H A DhalMVOP.c4355 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4356 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW); in HAL_MVOP_SubSetSynClk()
4382 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_SYNC_CW); in HAL_MVOP_SubSetSynClk()
4383 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_SYNC_CW); in HAL_MVOP_SubSetSynClk()
/utopia/UTPA2-700.0.x/modules/mvop/hal/kastor/mvop/
H A DregMVOP.h459 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE1) macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/curry/mvop/
H A DregMVOP.h456 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE1) macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/kano/mvop/
H A DregMVOP.h457 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE1) macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/k6lite/mvop/
H A DregMVOP.h464 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE1) macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/maxim/mvop/
H A DregMVOP.h444 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE1) macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/k7u/mvop/
H A DregMVOP.h492 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE1) macro
/utopia/UTPA2-700.0.x/modules/mvop/hal/k6/mvop/
H A DregMVOP.h525 #define REG_UPDATE_DC1_CW (CHIP_REG_BASE + 0xE1) macro

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