1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #include "MsCommon.h"
101 #ifndef MSOS_TYPE_LINUX_KERNEL
102 #include <string.h>
103 #endif
104 #include "MsTypes.h"
105 #include "MsIRQ.h"
106 #include "MsOS.h"
107 #include "drvMVOP.h"
108 #include "drvMIU.h"
109
110 // Internal Definition
111 #include "regMVOP.h"
112 #include "halMVOP.h"
113
114 #ifndef ANDROID
115 #define MVOP_PRINTF printf
116 #else
117 #include <sys/mman.h>
118 #include <cutils/ashmem.h>
119 #include <cutils/log.h>
120
121 #define MVOP_PRINTF ALOGD
122 #endif
123
124 // Common
125 #ifdef MSOS_TYPE_LINUX_KERNEL
126 #include <asm/div64.h>
127 #else
128 #define do_div(x,y) ((x)/=(y))
129 #define do_mod(x,y) ((x)%=(y))
130 #endif
131 //-------------------------------------------------------------------------------------------------
132 // Driver Compiler Options
133 //-------------------------------------------------------------------------------------------------
134
135
136 //-------------------------------------------------------------------------------------------------
137 // Local Defines
138 //-------------------------------------------------------------------------------------------------
139 #define MPLL_CLOCK_216 (216000000ULL)
140 #define MPLL_CLOCK_432 (432000000ULL)
141
142 #define BIT0 BIT(0)
143 #define BIT1 BIT(1)
144 #define BIT2 BIT(2)
145 #define BIT3 BIT(3)
146 #define BIT4 BIT(4)
147 #define BIT5 BIT(5)
148 #define BIT6 BIT(6)
149 #define BIT7 BIT(7)
150 #define BIT15 BIT(15)
151
152 #define ALIGN_UPTO_16(x) ((((x) + 15) >> 4) << 4)
153 #define ALIGN_UPTO_4(x) ((((x) + 3) >> 2) << 2)
154 #define ALIGN_UPTO_2(x) ((((x) + 1) >> 1) << 1)
155
156 #define MVOP_VBlank 45
157 #define MVOP_HBlank_SD 200
158 #define MVOP_HBlank_HD 300
159 #if 0
160 static MS_U32 u32RiuBaseAdd=0;
161 static MS_BOOL bMirrorModeVer = 0;
162 static MS_BOOL bMirrorModeHor = 0;
163 static MS_BOOL bMirrorMode=0;
164 static MS_BOOL bSubMirrorModeVer = 0;
165 static MS_BOOL bSubMirrorModeHor = 0;
166 static MS_BOOL bSubMirrorMode=0;
167 static MS_BOOL bEnableFreerunMode = FALSE;
168 static MS_BOOL bSubEnableFreerunMode = FALSE;
169 static MS_BOOL b3DLRMode=0; /// 3D L/R dual buffer mode
170 static MS_BOOL bSub3DLRMode=0;
171 static MS_BOOL b3DLRAltOutput = FALSE; /// 3D L/R line alternative output
172 static MS_BOOL bNewVSyncMode = FALSE;
173 static MVOP_RptFldMode eRepeatField = E_MVOP_RPTFLD_NONE; /// mvop output repeating fields for single field input.
174 static MVOP_RptFldMode eSubRepeatField = E_MVOP_RPTFLD_NONE; /// mvop output repeating fields for single field input.
175 static MVOP_RgbFormat eMainRgbFmt = E_MVOP_RGB_NONE;
176 static MVOP_RgbFormat eSubRgbFmt = E_MVOP_RGB_NONE;
177 #endif
178
179 typedef struct
180 {
181 MS_BOOL bMirrorModeVer;
182 MS_BOOL bMirrorModeHor;
183 MS_BOOL bMirrorMode;
184 MS_BOOL bEnableFreerunMode;
185
186 MS_BOOL b3DLRMode; /// 3D L/R dual buffer mode
187
188 MS_BOOL b3DLRAltOutput; /// 3D L/R line alternative output
189 MS_BOOL b3DLRAltSBSOutput; /// 3D L/R side by side output
190 MS_BOOL bNewVSyncMode;
191 MVOP_RptFldMode eRepeatField; /// mvop output repeating fields for single field input.
192 MVOP_RgbFormat eMainRgbFmt;
193 MS_BOOL bIsInit;
194 MS_BOOL bRptPreVsync;
195 MS_BOOL bIs422;
196 MS_BOOL bIsH265;
197 MS_BOOL bIsHS;
198 MS_U16 u16CropXStart;
199 MS_U16 u16CropYStart;
200 MS_U16 u16CropXSize;
201 MS_U16 u16CropYSize;
202 MS_BOOL bIs2p;
203 MS_BOOL bIsEnable;
204 MS_U16 u16VsyncLines;
205 MVOP_OutputImodeType eInterlaceType;
206 MS_BOOL bIsXcTrig;
207 MS_BOOL bIs265DV;
208 #if MVOP_SUPPORT_SUB
209 MS_BOOL bSubMirrorModeVer;
210 MS_BOOL bSubMirrorModeHor;
211 MS_BOOL bSubMirrorMode;
212 MS_BOOL bSubEnableFreerunMode;
213 MS_BOOL bSub3DLRMode;
214 MS_BOOL bSubNewVSyncMode;
215 MVOP_RptFldMode eSubRepeatField; /// mvop output repeating fields for single field input.
216 MVOP_RgbFormat eSubRgbFmt;
217 MS_BOOL bSubIsInit;
218 MS_BOOL bSubRptPreVsync;
219 MS_BOOL bSubIs422;
220 MS_BOOL bSubIsH265;
221 MS_BOOL bSub3DLRAltOutput; /// 3D L/R line alternative output
222 MS_BOOL bSub3DLRAltSBSOutput;
223 MS_BOOL bSubIsHS;
224 MS_U16 u16SubCropXStart;
225 MS_U16 u16SubCropYStart;
226 MS_U16 u16SubCropXSize;
227 MS_U16 u16SubCropYSize;
228 MS_BOOL bSubIs2p;
229 MS_BOOL bSubIsEnable;
230 MS_U16 u16SubVsyncLines;
231 MVOP_OutputImodeType eSubInterlaceType;
232 MS_BOOL bSubIsXcTrig;
233 #endif
234 }MVOP_CTX_HAL;
235
236 static MVOP_CTX_HAL *g_pHalMVOPCtx = NULL;
237 static MS_VIRT u32RiuBaseAdd=0;
238
239 #ifndef MSOS_TYPE_LINUX
240 MVOP_CTX_HAL g_stmvopHalCtx;
241 #endif
242 #if defined(SUPPORT_X_MODEL_FEATURE)
243 MVOP_CTX_HAL g_stmvopHalCtx;
244 #endif
245 #define RIU_MAP u32RiuBaseAdd //obtained in init
246
247 #define RIU8 ((unsigned char volatile *) RIU_MAP)
248 #define RIU16 ((MS_U16 volatile *) RIU_MAP)
249 #define MST_MACRO_START do {
250 #define MST_MACRO_END } while (0)
251
252 #define HAL_WriteByte( u32Reg, u8Val ) \
253 MST_MACRO_START \
254 if ( __builtin_constant_p( u32Reg ) ) \
255 { \
256 RIU8[((u32Reg) * 2) - ((u32Reg) & 1)] = u8Val; \
257 } \
258 else \
259 { \
260 RIU8[(u32Reg << 1) - (u32Reg & 1)] = u8Val; \
261 } \
262 MST_MACRO_END
263
264 #define HAL_ReadByte( u32Reg ) \
265 (__builtin_constant_p( u32Reg ) ? \
266 (((u32Reg) & 0x01) ? RIU8[(u32Reg) * 2 - 1] : RIU8[(u32Reg) * 2]) : \
267 (RIU8[(u32Reg << 1) - (u32Reg & 1)]))
268
269 #define HAL_Read2Byte( u32Reg ) \
270 (RIU16[u32Reg])
271
272 #define HAL_ReadRegBit( u32Reg, u8Mask ) \
273 (RIU8[(u32Reg) * 2 - ((u32Reg) & 1)] & (u8Mask))
274
275 #define HAL_WriteRegBit( u32Reg, bEnable, u8Mask ) \
276 MST_MACRO_START \
277 MS_U32 u32Reg8 = ((u32Reg) * 2) - ((u32Reg) & 1); \
278 RIU8[u32Reg8] = (bEnable) ? (RIU8[u32Reg8] | (u8Mask)) : \
279 (RIU8[u32Reg8] & ~(u8Mask)); \
280 MST_MACRO_END
281
282 #define HAL_WriteByteMask( u32Reg, u8Val, u8Msk ) \
283 MST_MACRO_START \
284 MS_U32 u32Reg8 = ((u32Reg) * 2) - ((u32Reg) & 1); \
285 RIU8[u32Reg8] = (RIU8[u32Reg8] & ~(u8Msk)) | ((u8Val) & (u8Msk)); \
286 MST_MACRO_END
287
288 #define HAL_Write2Byte(u32Reg, u16Val) \
289 RIU16[u32Reg] = u16Val;
290
291 #define SUB_REG(x) (x-MVOP_REG_BASE+MVOP_SUB_REG_BASE)
292
293 #define _FUNC_NOT_USED() do {} while ( 0 )
294 #ifndef UNUSED
295 #define UNUSED(x) (void)(x)
296 #endif
297
298 #define LOWBYTE(u16) ((MS_U8)(u16))
299 #define HIGHBYTE(u16) ((MS_U8)((u16) >> 8))
300
301
302 #define VOP_ON_MIU1 ((HAL_ReadByte(0x12F9) & BIT2) == BIT2)
303 #define _MaskMiuReq_MVOP_R( m ) HAL_WriteRegBit(0x12C7, m, BIT2)
304 #define _MaskMiu1Req_MVOP_R( m ) HAL_WriteRegBit(0x06C7, m, BIT2)
305
306 #define HAL_MIU_SetReqMask( miu_clients, mask ) \
307 do { \
308 if (VOP_ON_MIU1 == 0) \
309 _MaskMiuReq_##miu_clients( mask ); \
310 else \
311 _MaskMiu1Req_##miu_clients( mask ); \
312 }while(0)
313
314 #define SUBVOP_ON_MIU1 ((HAL_ReadByte(0x12F9) & BIT2) == BIT2)
315 #define _MaskMiuReq_SUBMVOP_R( m ) HAL_WriteRegBit(0x12C7, m, BIT2)
316 #define _MaskMiu1Req_SUBMVOP_R( m ) HAL_WriteRegBit(0x06C7, m, BIT2)
317
318 #define HAL_MIU_SubSetReqMask( miu_clients, mask ) \
319 do { \
320 if (SUBVOP_ON_MIU1 == 0) \
321 _MaskMiuReq_##miu_clients( mask ); \
322 else \
323 _MaskMiu1Req_##miu_clients( mask ); \
324 }while(0)
325
326 #define MVOP_DBG_ENABLE 0
327 #if MVOP_DBG_ENABLE
328 #define MVOP_DBG(fmt, args...) MVOP_PRINTF(fmt, ##args)
329 #else
330 #define MVOP_DBG(fmt, args...) {}
331 #endif
332
333 typedef enum
334 {
335 E_MVOP_INIT_OK = 0,
336 E_MVOP_INIT_FAIL = 1,
337 E_MVOP_INIT_ALREADY_EXIST = 2
338 } MVOP_HalInitCtxResults;
339 //-------------------------------------------------------------------------------------------------
340 // Local Structures
341 //-------------------------------------------------------------------------------------------------
342
343
344 //-------------------------------------------------------------------------------------------------
345 // Global Variables
346 //-------------------------------------------------------------------------------------------------
347
348 #define Y_INFO 0
349 #define UV_INFO 1
350
351 //-------------------------------------------------------------------------------------------------
352 // Local Variables
353 //-------------------------------------------------------------------------------------------------
354
355
356 //-------------------------------------------------------------------------------------------------
357 // Debug Functions
358 //-------------------------------------------------------------------------------------------------
359
360
361 //-------------------------------------------------------------------------------------------------
362 // Local Functions
363 //-------------------------------------------------------------------------------------------------
364
365
366 //-------------------------------------------------------------------------------------------------
367 // Global Functions
368 //-------------------------------------------------------------------------------------------------
369
_HAL_MVOP_InitVarCtx(void)370 void _HAL_MVOP_InitVarCtx(void)
371 {
372 g_pHalMVOPCtx->bMirrorModeVer = 0;
373 g_pHalMVOPCtx->bMirrorModeHor = 0;
374 g_pHalMVOPCtx->bMirrorMode=0;
375 g_pHalMVOPCtx->bEnableFreerunMode = FALSE;
376 g_pHalMVOPCtx->b3DLRMode=0; /// 3D L/R dual buffer mode
377 g_pHalMVOPCtx->b3DLRAltOutput = FALSE; /// 3D L/R line alternative output
378 g_pHalMVOPCtx->b3DLRAltSBSOutput = FALSE;
379 g_pHalMVOPCtx->bNewVSyncMode = FALSE;
380 g_pHalMVOPCtx->eRepeatField = E_MVOP_RPTFLD_NONE; /// mvop output repeating fields for single field input.
381 g_pHalMVOPCtx->eMainRgbFmt = E_MVOP_RGB_NONE;
382 g_pHalMVOPCtx->bIsInit = 0;
383 g_pHalMVOPCtx->bRptPreVsync = 0;
384 g_pHalMVOPCtx->bIs422 = 0;
385 g_pHalMVOPCtx->bIsH265 = 0;
386 g_pHalMVOPCtx->bIsHS = FALSE;
387 g_pHalMVOPCtx->u16CropXStart = 0;
388 g_pHalMVOPCtx->u16CropYStart = 0;
389 g_pHalMVOPCtx->u16CropXSize = 0;
390 g_pHalMVOPCtx->u16CropYSize = 0;
391 g_pHalMVOPCtx->bIs2p = FALSE;
392 g_pHalMVOPCtx->bIsEnable = 0;
393 g_pHalMVOPCtx->u16VsyncLines = 0;
394 g_pHalMVOPCtx->eInterlaceType = E_MVOP_PRO;
395 g_pHalMVOPCtx->bIsXcTrig = FALSE;
396 g_pHalMVOPCtx->bIs265DV = 0;
397 }
398
_HAL_MVOP_SubInitVarCtx(void)399 void _HAL_MVOP_SubInitVarCtx(void)
400 {
401 #if MVOP_SUPPORT_SUB
402 g_pHalMVOPCtx->bSubMirrorModeVer = 0;
403 g_pHalMVOPCtx->bSubMirrorModeHor = 0;
404 g_pHalMVOPCtx->bSubMirrorMode=0;
405 g_pHalMVOPCtx->bSubEnableFreerunMode = FALSE;
406 g_pHalMVOPCtx->bSub3DLRMode=0;
407 g_pHalMVOPCtx->bSubNewVSyncMode = FALSE;
408 g_pHalMVOPCtx->eSubRepeatField = E_MVOP_RPTFLD_NONE; /// mvop output repeating fields for single field input.
409 g_pHalMVOPCtx->eSubRgbFmt = E_MVOP_RGB_NONE;
410 g_pHalMVOPCtx->bSubIsInit = 0;
411 g_pHalMVOPCtx->bSubRptPreVsync = 0;
412 g_pHalMVOPCtx->bSubIs422 = 0;
413 g_pHalMVOPCtx->bSubIsH265 = 0;
414 g_pHalMVOPCtx->bSub3DLRAltOutput = FALSE; /// 3D L/R line alternative output
415 g_pHalMVOPCtx->bSub3DLRAltSBSOutput = FALSE;
416 g_pHalMVOPCtx->bSubIsHS = FALSE;
417 g_pHalMVOPCtx->u16SubCropXStart = 0;
418 g_pHalMVOPCtx->u16SubCropYStart = 0;
419 g_pHalMVOPCtx->u16SubCropXSize = 0;
420 g_pHalMVOPCtx->u16SubCropYSize = 0;
421 g_pHalMVOPCtx->bSubIs2p = FALSE;
422 g_pHalMVOPCtx->bSubIsEnable = 0;
423 g_pHalMVOPCtx->u16SubVsyncLines = 0;
424 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_PRO;
425 g_pHalMVOPCtx->bSubIsXcTrig = FALSE;
426 #endif
427 }
428
_HAL_MVOP_InitContext(MS_BOOL * pbFirstDrvInstant)429 MVOP_HalInitCtxResults _HAL_MVOP_InitContext(MS_BOOL *pbFirstDrvInstant)
430 {
431 MS_BOOL bNeedInitShared = FALSE;
432
433 //check first init by MsOS_SHM_GetId / MSOS_SHM_QUERY
434 #if 0
435 if (g_pHalMVOPCtx)
436 {
437 // The context instance has been created already
438 // before somewhere sometime in the same process.
439 *pbFirstDrvInstant = bNeedInitShared;
440 //return E_MVOP_INIT_FAIL;
441 return E_MVOP_INIT_OK;
442 }
443 #endif
444
445 #if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_LINUX_KERNEL)
446 #if !defined(SUPPORT_X_MODEL_FEATURE)
447 MS_U32 u32ShmId;
448 MS_VIRT u32Addr;
449 MS_U32 u32BufSize;
450
451 //MsOS_SHM_Init(); init in msos_init
452 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux MVOP HAL driver", sizeof(MVOP_CTX_HAL), &u32ShmId, &u32Addr, &u32BufSize, MSOS_SHM_QUERY))
453 {
454 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux MVOP HAL driver", sizeof(MVOP_CTX_HAL), &u32ShmId, &u32Addr, &u32BufSize, MSOS_SHM_CREATE))
455 {
456 MVOP_DBG(MVOP_PRINTF("MVOP: SHM allocation failed!\n");)
457 return E_MVOP_INIT_FAIL;
458 }
459 MVOP_DBG(MVOP_PRINTF("MVOP: [%s][%d] This is first initial 0x%08lx\n", __FUNCTION__, __LINE__, u32Addr);)
460 memset( (MS_U8*)u32Addr, 0, sizeof(MVOP_CTX_HAL));
461 bNeedInitShared = TRUE;
462 g_pHalMVOPCtx = (MVOP_CTX_HAL*)u32Addr;
463 _HAL_MVOP_InitVarCtx();
464 #if MVOP_SUPPORT_SUB
465 _HAL_MVOP_SubInitVarCtx();
466 #endif
467 }
468 else
469 {
470 g_pHalMVOPCtx = (MVOP_CTX_HAL*)u32Addr;
471 bNeedInitShared = FALSE;
472 *pbFirstDrvInstant = bNeedInitShared;
473
474 return E_MVOP_INIT_ALREADY_EXIST;
475 }
476 #else
477 g_pHalMVOPCtx = &g_stmvopHalCtx;
478 bNeedInitShared = TRUE;
479 #endif
480 #else
481 g_pHalMVOPCtx = &g_stmvopHalCtx;
482 bNeedInitShared = TRUE;
483 #endif
484 *pbFirstDrvInstant = bNeedInitShared;
485
486 if (bNeedInitShared)
487 {
488 memset(g_pHalMVOPCtx, 0, sizeof(*g_pHalMVOPCtx));
489 }
490
491 return E_MVOP_INIT_OK;
492 }
493
_HAL_MVOP_IsSupport4k2k2P(void)494 MS_BOOL _HAL_MVOP_IsSupport4k2k2P(void)
495 {
496 return TRUE;
497 }
498
HAL_MVOP_RegSetBase(MS_VIRT u32Base)499 void HAL_MVOP_RegSetBase(MS_VIRT u32Base)
500 {
501 u32RiuBaseAdd = u32Base;
502 }
503
HAL_MVOP_InitMirrorMode(MS_BOOL bMir)504 void HAL_MVOP_InitMirrorMode(MS_BOOL bMir)
505 {
506 //set bit[3:7] to support mirror mode
507 HAL_WriteRegBit(VOP_MIRROR_CFG, bMir, VOP_MIRROR_CFG_ENABLE);
508 }
509
HAL_MVOP_SetVerticalMirrorMode(MS_BOOL bEnable)510 void HAL_MVOP_SetVerticalMirrorMode(MS_BOOL bEnable)
511 {
512 if (g_pHalMVOPCtx == NULL)
513 {
514 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
515 return;
516 }
517
518 if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(VOP_MIRROR_CFG, VOP_MIRROR_CFG_ENABLE))
519 {
520 //MVOP_PRINTF("Setup mirror mode\n");
521 HAL_MVOP_InitMirrorMode(TRUE);
522 }
523
524 HAL_WriteRegBit(VOP_MIRROR_CFG, bEnable, VOP_MIRROR_CFG_VEN);
525 g_pHalMVOPCtx->bMirrorModeVer = bEnable;
526 }
527
HAL_MVOP_SetHorizontallMirrorMode(MS_BOOL bEnable)528 void HAL_MVOP_SetHorizontallMirrorMode(MS_BOOL bEnable)
529 {
530 if (g_pHalMVOPCtx == NULL)
531 {
532 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
533 return;
534 }
535
536 if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(VOP_MIRROR_CFG, VOP_MIRROR_CFG_ENABLE))
537 {
538 //MVOP_PRINTF("Setup mirror mode\n");
539 HAL_MVOP_InitMirrorMode(TRUE);
540 }
541
542 HAL_WriteRegBit(VOP_MIRROR_CFG, bEnable, VOP_MIRROR_CFG_HEN);
543 g_pHalMVOPCtx->bMirrorModeHor = bEnable;
544 }
545
HAL_MVOP_Init(void)546 void HAL_MVOP_Init(void)
547 {
548 MVOP_HalInitCtxResults eRet;
549 MS_BOOL pbFirstDrvInstant;
550
551 eRet = _HAL_MVOP_InitContext(&pbFirstDrvInstant);
552 if(eRet == E_MVOP_INIT_FAIL)
553 {
554 MVOP_DBG(MVOP_PRINTF("[%s] MVOP Context Init failed!\n",__FUNCTION__);)
555 return;
556 }
557 else if(eRet == E_MVOP_INIT_ALREADY_EXIST)
558 {
559 if(g_pHalMVOPCtx->bIsInit)
560 {
561 MVOP_DBG(MVOP_PRINTF("[%s] Main MVOP Context has Initialized!\n",__FUNCTION__);)
562 return;
563 }
564 }
565
566 HAL_MVOP_InitMirrorMode(TRUE);
567 //Enable dynamic clock gating
568 //Note: cannot enable VOP_GCLK_VCLK_ON, or hsync cannot be sent out.
569 HAL_WriteByteMask(VOP_GCLK, VOP_GCLK_MIU_ON, VOP_GCLK_MIU_ON|VOP_GCLK_VCLK_ON);
570 g_pHalMVOPCtx->bIsInit = 1;
571 }
572
HAL_MVOP_SetFieldInverse(MS_BOOL b2MVD,MS_BOOL b2IP)573 void HAL_MVOP_SetFieldInverse(MS_BOOL b2MVD, MS_BOOL b2IP)
574 {
575 // Set fld inv & ofld_inv
576 HAL_WriteRegBit(VOP_CTRL0+1, b2MVD, BIT3); //inverse the field to MVD
577 HAL_WriteRegBit(VOP_CTRL0+1, b2IP, BIT4); //inverse the field to IP
578 }
579
HAL_MVOP_SetChromaWeighting(MS_BOOL bEnable)580 void HAL_MVOP_SetChromaWeighting(MS_BOOL bEnable)
581 {
582 HAL_WriteRegBit(VOP_REG_WEIGHT_CTRL, bEnable, BIT1);
583 }
584
585 //load new value into active registers 0x20-0x26
HAL_MVOP_LoadReg(void)586 void HAL_MVOP_LoadReg(void)
587 {
588 HAL_WriteRegBit(VOP_REG_WR, 1, BIT0);
589 HAL_WriteRegBit(VOP_REG_WR, 0, BIT0);
590
591 HAL_WriteRegBit(VOP_REG_WR, 1, BIT4);
592 HAL_WriteRegBit(VOP_REG_WR, 0, BIT4);
593 }
594
595
HAL_MVOP_SetMIUReqMask(MS_BOOL bEnable)596 void HAL_MVOP_SetMIUReqMask(MS_BOOL bEnable)
597 {
598 #if 0 //[FIXME]
599 if (bEnable)
600 { // mask MVOP2MI to protect MIU
601 HAL_MIU_SetReqMask(MVOP_R, 1);
602 MsOS_DelayTask(1);
603 }
604 else
605 { // unmask MVOP2MI
606 MsOS_DelayTask(1);
607 HAL_MIU_SetReqMask(MVOP_R, 0);
608 }
609 #endif
610 MS_U8 u8Miu;
611
612 if(HAL_MVOP_GetIsOnlyMiuIPControl() == TRUE)
613 {
614 // mask msb mvop
615 u8Miu = (HAL_ReadByte(VOP_MIU_SEL) & VOP_MSB_BUF0_MIU_SEL) >> 4;
616 }
617 else
618 {
619 u8Miu = VOP_ON_MIU1;
620 }
621 eMIUClientID eClientID = MIU_CLIENT_MVOP_128BIT_R;
622 //MVOP_PRINTF("Enter %s bEnable=%x ReqMask=0x%x, 0x%x\n", __FUNCTION__, bEnable,
623 // HAL_ReadByte(0x1266), HAL_ReadByte(0x0666));
624 if (bEnable)
625 { // mask MVOP2MI to protect MIU
626 MDrv_MIU_MaskReq(u8Miu,eClientID);
627 MsOS_DelayTask(1);
628 }
629 else
630 { // unmask MVOP2MI
631 MsOS_DelayTask(1);
632 MDrv_MIU_UnMaskReq(u8Miu,eClientID);
633 }
634
635 //MVOP_PRINTF(">Exit %s bEnable=%x ReqMask=0x%x, 0x%x\n", __FUNCTION__, bEnable,
636 // HAL_ReadByte(0x1266), HAL_ReadByte(0x0666));
637 }
638
HAL_MVOP_Rst(void)639 void HAL_MVOP_Rst(void)
640 {
641 #if 0
642 MS_BOOL bMCU = FALSE;
643
644 bMCU = HAL_ReadRegBit(VOP_MPG_JPG_SWITCH, BIT1);
645 #endif
646 HAL_WriteRegBit(VOP_CTRL0, 0, BIT0);
647 HAL_WriteRegBit(VOP_CTRL0, 1, BIT0);
648
649 g_pHalMVOPCtx->bIsEnable = 1;
650 #if 0
651 // sw patch: for mvop hsk mode, switching mvop enable/disable may cause video was stuck.
652 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] HAL_MVOP_Enable patch \n");)
653 HAL_MVOP_SetBlackBG();
654 HAL_MVOP_SetPattern(MVOP_PATTERN_FRAMECOLOR);
655 HAL_WriteRegBit(VOP_REG_WR, 1, BIT4);
656 HAL_WriteRegBit(VOP_MPG_JPG_SWITCH, 1, BIT1);
657 MsOS_DelayTask(40);
658 if(bMCU == FALSE)
659 {
660 HAL_WriteRegBit(VOP_MPG_JPG_SWITCH, 0, BIT1);
661 }
662 HAL_MVOP_SetPattern(MVOP_PATTERN_NORMAL);
663 HAL_WriteRegBit(VOP_REG_WR, 0, BIT4);
664 #endif
665 }
666
HAL_MVOP_Enable(MS_BOOL bEnable,MS_U8 u8Framerate)667 void HAL_MVOP_Enable(MS_BOOL bEnable, MS_U8 u8Framerate)
668 {
669 MS_U8 regval;
670 #if 0 //remove patch
671 MS_U8 u8FrmDur = 40;
672 MS_BOOL bMCU = FALSE;
673
674 bMCU = HAL_ReadRegBit(VOP_MPG_JPG_SWITCH, BIT1);
675
676 if(u8Framerate != 0)
677 {
678 u8FrmDur = 1000/u8Framerate; //time of one frame(ms).
679 }
680 #endif
681
682 regval = HAL_ReadByte(VOP_CTRL0);
683
684 if ( bEnable )
685 {
686 regval |= 0x1;
687 }
688 else
689 {
690 regval &= ~0x1;
691 HAL_Write2Byte(VOP_BF_VS_MVD, 0x200);
692 HAL_Write2Byte(VOP_TF_VS_MVD, 0x200);
693 }
694 #if 0
695 // sw patch: for mvop hsk mode, switching mvop enable/disable may cause video was stuck.
696 if( bEnable && (g_pHalMVOPCtx->bIsEnable == FALSE)) // need patch only from off to on
697 {
698 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] HAL_MVOP_Enable patch \n");)
699 HAL_MVOP_SetBlackBG();
700 HAL_MVOP_SetPattern(MVOP_PATTERN_FRAMECOLOR);
701 HAL_WriteRegBit(VOP_REG_WR, 1, BIT4);
702 HAL_WriteRegBit(VOP_MPG_JPG_SWITCH, 1, BIT1);
703 MsOS_DelayTask(u8FrmDur);
704 if(bMCU == FALSE)
705 {
706 HAL_WriteRegBit(VOP_MPG_JPG_SWITCH, 0, BIT1);
707 }
708 HAL_MVOP_SetPattern(MVOP_PATTERN_NORMAL);
709 HAL_WriteRegBit(VOP_REG_WR, 0, BIT4);
710 }
711 #endif
712 g_pHalMVOPCtx->bIsEnable = bEnable;
713
714 HAL_WriteByte(VOP_CTRL0, regval);
715 }
716
HAL_MVOP_GetEnableState(void)717 MS_BOOL HAL_MVOP_GetEnableState(void)
718 {
719 return (HAL_ReadRegBit(VOP_CTRL0, BIT0));
720 }
721
HAL_MVOP_GetMaxFreerunClk(void)722 HALMVOPFREQUENCY HAL_MVOP_GetMaxFreerunClk(void)
723 {
724 return HALMVOP_160MHZ;
725 }
726
HAL_MVOP_Get4k2kClk(void)727 HALMVOPFREQUENCY HAL_MVOP_Get4k2kClk(void)
728 {
729 return HALMVOP_320MHZ;
730 }
731
HAL_MVOP_SetFrequency(HALMVOPFREQUENCY enFrequency)732 void HAL_MVOP_SetFrequency(HALMVOPFREQUENCY enFrequency)
733 {
734 // clear
735 HAL_WriteByteMask(REG_CKG_DC0, 0, CKG_DC0_MASK);
736 switch(enFrequency)
737 {
738 case HALMVOP_SYNCMODE:
739 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK);
740 break;
741 case HALMVOP_FREERUNMODE:
742 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_FREERUN, CKG_DC0_MASK);
743 break;
744 case HALMVOP_160MHZ:
745 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK);
746 break;
747 case HALMVOP_144MHZ:
748 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_144MHZ, CKG_DC0_MASK);
749 break;
750 case HALMVOP_320MHZ:
751 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_320MHZ, CKG_DC0_MASK);
752 break;
753 default:
754 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK);
755 MVOP_PRINTF("Attention! In HAL_MVOP_SetFrequency default path!\n");
756 break;
757 }
758 }
759
HAL_MVOP_GetMaximumClk(void)760 HALMVOPFREQUENCY HAL_MVOP_GetMaximumClk(void)
761 {
762 return HALMVOP_320MHZ;
763 }
764
HAL_MVOP_GetCurrentClk(void)765 HALMVOPFREQUENCY HAL_MVOP_GetCurrentClk(void)
766 {
767 (MVOP_DBG("%s err: HAL_MVOP_GetCurrentClk=NULL\n", __FUNCTION__));
768 return 0;
769 }
770
HAL_MVOP_SetOutputInterlace(MS_BOOL bEnable)771 void HAL_MVOP_SetOutputInterlace(MS_BOOL bEnable)
772 {
773 MS_U8 regval;
774
775 regval = HAL_ReadByte(VOP_CTRL0);
776
777 if ( bEnable )
778 {
779 regval |= 0x80;
780 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
781 }
782 else
783 {
784 regval &= ~0x80;
785 }
786
787 HAL_WriteByte(VOP_CTRL0, regval);
788 }
789
HAL_MVOP_SetPattern(MVOP_Pattern enMVOPPattern)790 void HAL_MVOP_SetPattern(MVOP_Pattern enMVOPPattern)
791 {
792 HAL_WriteByteMask(VOP_TST_IMG, enMVOPPattern, BIT2 | BIT1 | BIT0);
793 }
794
HAL_MVOP_SetTileFormat(MVOP_TileFormat eTileFmt)795 MS_BOOL HAL_MVOP_SetTileFormat(MVOP_TileFormat eTileFmt)
796 {
797 if (eTileFmt == E_MVOP_TILE_8x32)
798 {
799 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
800 return TRUE;
801 }
802 else if (eTileFmt == E_MVOP_TILE_16x32)
803 {
804 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
805 return TRUE;
806 }
807 else
808 {
809 return FALSE;
810 }
811 }
812
HAL_MVOP_GetSupportRgbFormat(MVOP_RgbFormat eRgbFmt)813 MS_BOOL HAL_MVOP_GetSupportRgbFormat(MVOP_RgbFormat eRgbFmt)
814 {
815 if ((eRgbFmt == E_MVOP_RGB_565) || (eRgbFmt == E_MVOP_RGB_888))
816 {
817 return TRUE;
818 }
819 return FALSE;
820 }
821
HAL_MVOP_SetRgbFormat(MVOP_RgbFormat eRgbFmt)822 MS_BOOL HAL_MVOP_SetRgbFormat(MVOP_RgbFormat eRgbFmt)
823 {
824 MS_BOOL bRet = FALSE;
825
826 if (g_pHalMVOPCtx == NULL)
827 {
828 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
829 return FALSE;
830 }
831
832 if (eRgbFmt == E_MVOP_RGB_NONE)
833 {
834 HAL_WriteByteMask(VOP_RGB_FMT, 0, VOP_RGB_FMT_SEL);
835 bRet = TRUE;
836 }
837 else if (eRgbFmt == E_MVOP_RGB_565)
838 {
839 HAL_WriteByteMask(VOP_RGB_FMT, VOP_RGB_FMT_565, VOP_RGB_FMT_SEL);
840 bRet = TRUE;
841 }
842 else if (eRgbFmt == E_MVOP_RGB_888)
843 {
844 HAL_WriteByteMask(VOP_RGB_FMT, VOP_RGB_FMT_888, VOP_RGB_FMT_SEL);
845 bRet = TRUE;
846 }
847
848 if (bRet == TRUE)
849 {
850 g_pHalMVOPCtx->eMainRgbFmt = eRgbFmt;
851 }
852 return bRet;
853 }
854
HAL_MVOP_SetBlackBG(void)855 void HAL_MVOP_SetBlackBG(void)
856 {
857 MS_U8 regval;
858
859 //set MVOP test pattern to black
860 HAL_WriteByte((VOP_TST_IMG + 1), 0x10);
861 HAL_WriteByte(VOP_U_PAT , 0x80);
862 HAL_WriteByte((VOP_U_PAT + 1), 0x80);
863
864 regval = HAL_ReadByte(VOP_TST_IMG);
865 HAL_WriteByte(VOP_TST_IMG, 0x02);
866 HAL_WriteByte(VOP_TST_IMG, 0x00);
867 HAL_WriteByte(VOP_TST_IMG, regval);
868 }
869
HAL_MVOP_SetCropWindow(MVOP_InputCfg * pparam)870 void HAL_MVOP_SetCropWindow(MVOP_InputCfg *pparam)
871 {
872 #if 1
873 UNUSED(pparam);
874 #else // enable it when test code is ready
875 MS_U32 x, y;
876 MS_U32 u32offset;
877
878 if(!pparam)
879 {
880 return;
881 }
882 //set MVOP test pattern to black
883 HAL_MVOP_SetBlackBG();
884 #if 0
885 if((pparam->enVideoType == MVOP_H264) && (pparam->u16StripSize == 1920))
886 {
887 pparam->u16StripSize = 1952;
888 }
889 #endif
890 if((pparam->enVideoType == MVOP_MPG) || (pparam->enVideoType == MVOP_MPEG4))
891 {
892 pparam->u16CropX = (pparam->u16CropX >> 3) << 3; // 8 bytes align
893 pparam->u16CropY = (pparam->u16CropY >> 6) << 6; // 64 bytes align
894 }
895 else if((pparam->enVideoType == MVOP_H264) || (pparam->enVideoType == MVOP_RM))
896 {
897 pparam->u16CropX = (pparam->u16CropX >> 4) << 4; // 16 bytes align
898 pparam->u16CropY = (pparam->u16CropY >> 6) << 6; // 64 bytes align
899 }
900 else
901 {
902 MS_ASSERT(0);
903 }
904
905 x = (MS_U32)pparam->u16CropX;
906 y = (MS_U32)pparam->u16CropY;
907
908 // y offset
909 u32offset = ((y * pparam->u16StripSize + (x << 5)) >> 3);
910 HAL_WriteByte((VOP_JPG_YSTR0_L ), (MS_U8)(u32offset));
911 HAL_WriteByte((VOP_JPG_YSTR0_L + 1), (MS_U8)(u32offset >> 8));
912 HAL_WriteByte((VOP_JPG_YSTR0_H ), (MS_U8)(u32offset >> 16));
913 HAL_WriteByte((VOP_JPG_YSTR0_H + 1), (MS_U8)((u32offset >> 24) & VOP_YUV_STR_HIBITS));
914
915 // uv offset
916 u32offset = ((y >> 1) * pparam->u16StripSize + (x << 5)) >> 3;
917 HAL_WriteByte((VOP_JPG_UVSTR0_L ), (MS_U8)(u32offset));
918 HAL_WriteByte((VOP_JPG_UVSTR0_L + 1), (MS_U8)(u32offset >> 8));
919 HAL_WriteByte((VOP_JPG_UVSTR0_H ), (MS_U8)(u32offset >> 16));
920 HAL_WriteByte((VOP_JPG_UVSTR0_H + 1), (MS_U8)((u32offset >> 24) & VOP_YUV_STR_HIBITS));
921
922 pparam->u16CropWidth= (pparam->u16CropWidth >> 3) << 3;
923 // HSize, VSize
924 HAL_WriteByte((VOP_JPG_HSIZE ), LOWBYTE(pparam->u16CropWidth ));
925 HAL_WriteByte((VOP_JPG_HSIZE + 1), HIGHBYTE(pparam->u16CropWidth ));
926 HAL_WriteByte((VOP_JPG_VSIZE ), LOWBYTE(pparam->u16CropHeight));
927 HAL_WriteByte((VOP_JPG_VSIZE + 1), HIGHBYTE(pparam->u16CropHeight ));
928
929 HAL_WriteByteMask(VOP_MPG_JPG_SWITCH, BIT0, BIT1|BIT0);
930
931 // clear extend strip len bit by default
932 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
933 if((pparam->enVideoType == MVOP_MPG) || (pparam->enVideoType == MVOP_MPEG4))
934 {
935 // Disable H264 or RM Input
936 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 0, BIT2|BIT3);
937 //8*32 tile format
938 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
939 }
940 else if((pparam->enVideoType == MVOP_H264) || (pparam->enVideoType == MVOP_RM))
941 {
942 //16*32 tile format
943 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
944 // SVD mode enable
945 HAL_WriteByteMask(VOP_INPUT_SWITCH1, BIT3, BIT2|BIT3);
946 // set mvop to 64bit interface
947 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
948 }
949 HAL_MVOP_LoadReg();
950 #endif
951 }
952
HAL_MVOP_SetRepeatField(MVOP_RptFldMode eMode)953 void HAL_MVOP_SetRepeatField(MVOP_RptFldMode eMode)
954 {
955 if (g_pHalMVOPCtx == NULL)
956 {
957 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
958 return;
959 }
960 g_pHalMVOPCtx->eRepeatField = eMode;
961 }
962
HAL_MVOP_SetInputMode(VOPINPUTMODE mode,MVOP_InputCfg * pparam,MS_U16 u16ECOVersion)963 void HAL_MVOP_SetInputMode( VOPINPUTMODE mode, MVOP_InputCfg *pparam, MS_U16 u16ECOVersion )
964 {
965 MS_U8 regval;
966 MS_U16 u16strip, u16strip_lsb;
967
968 if (g_pHalMVOPCtx == NULL)
969 {
970 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
971 return;
972 }
973 #if 0
974 /*****************************************************/
975 // Reset MVOP setting
976 HAL_WriteByte(VOP_TST_IMG, 0x40); //reset test pattern or BG
977 HAL_MVOP_Set3DLRAltOutput_VHalfScaling(DISABLE); //reset to default: disable 3D L/R alternative output.
978 HAL_MVOP_Set3DLR2ndCfg(DISABLE); //reset to default: disable 3D L/R 2nd pitch.
979 HAL_MVOP_SetRgbFormat(E_MVOP_RGB_NONE); //reset rgb format
980 HAL_WriteRegBit(VOP_CTRL1, 0, VOP_MVD_VS_MD); //default use original vsync
981 // Only for Monaco: Enable deciding bot by top address + 2
982 HAL_WriteRegBit(VOP_MIRROR_CFG, 1, VOP_FIELD_FROM_ADDR);
983
984 //set MVOP test pattern to black
985 HAL_MVOP_SetBlackBG();
986
987 // clear extend strip len bit by default
988 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
989
990 // set mvop to 128bit_i128 interface
991 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
992
993 // Disable H264 or RM Input
994 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 0, BIT2|BIT3);
995 // Clear 422 Flag
996 g_pHalMVOPCtx->bIs422 = 0;
997 // Clear evd Flag for interlace mode setting
998 g_pHalMVOPCtx->bIsH265 = 0;
999 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_L, 1, BIT3);
1000 HAL_WriteRegBit(VOP_MIRROR_CFG, 1, BIT5);
1001 //8*32 tile format
1002 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
1003 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD);
1004 HAL_MVOP_SetFieldInverse(ENABLE, ENABLE);
1005 // EVD mode disable
1006 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, EVD_ENABLE);
1007 // EVD 10 bits disable
1008 HAL_WriteByteMask(VOP_REG_MASK, BIT1, VOP_LSB_REQ_MASK);
1009 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_Y_EN);
1010 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_UV_EN);
1011 HAL_WriteRegBit(VOP_UV_SHIFT, 1, VOP_GCLK_MIU_ON);
1012 // Disable 420 BW Saving mode
1013 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_420_BW_SAVE);
1014 // Disable New Vsync Mode
1015 g_pHalMVOPCtx->bNewVSyncMode = FALSE;
1016 // VP9 MODE disable
1017 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, VOP_R2_WISHBONE);
1018 HAL_WriteRegBit(VOP_MPG_JPG_SWITCH, 0, VOP_DRAM_RD_MODE);
1019 // Disable 2p mode
1020 HAL_MVOP_SetEnable4k2k2P(FALSE);
1021 /*****************************************************/
1022 #endif
1023 regval = 0;
1024 regval |= ( mode & 0x3 );
1025
1026 if ( mode == VOPINPUT_HARDWIRE )
1027 {
1028 HAL_WriteByte(VOP_MPG_JPG_SWITCH, regval);
1029 }
1030 else if ( mode == VOPINPUT_HARDWIRECLIP )
1031 {
1032 HAL_WriteByte(VOP_MPG_JPG_SWITCH, regval);
1033
1034 // HSize, VSize
1035 HAL_WriteByte(VOP_JPG_HSIZE , LOWBYTE( pparam->u16HSize ));
1036 HAL_WriteByte((VOP_JPG_HSIZE + 1), HIGHBYTE( pparam->u16HSize ));
1037 HAL_WriteByte(VOP_JPG_VSIZE , LOWBYTE( pparam->u16VSize ));
1038 HAL_WriteByte((VOP_JPG_VSIZE + 1), HIGHBYTE( pparam->u16VSize ));
1039 }
1040 else if (mode == VOPINPUT_MCUCTRL)
1041 {
1042 // disable from wb
1043 HAL_WriteRegBit(VOP_REG_MFDEC_2_L, 0, VOP_MF_FROM_WB);
1044 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, VOP_R2_WISHBONE);
1045 g_pHalMVOPCtx->bMirrorMode = (g_pHalMVOPCtx->bMirrorModeVer||g_pHalMVOPCtx->bMirrorModeHor);
1046 if ( pparam->bProgressive )
1047 regval |= 0x4;
1048 else
1049 {
1050 regval &= ~0x4;
1051 regval |= 0x1; //reg_dc_md=b'11 for interlace input
1052 if (E_MVOP_RPTFLD_NONE == g_pHalMVOPCtx->eRepeatField)
1053 {
1054 MVOP_DBG("%s normal NOT repeat field %x\n", __FUNCTION__, g_pHalMVOPCtx->eRepeatField);
1055 //To support mcu mode interlace, need to set h'3B[9]=1,
1056 //h'11[12]=0, and Y1/UV1 address equal to Y0/UV0 address.
1057 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD);
1058 HAL_MVOP_SetFieldInverse(ENABLE, DISABLE);
1059 }
1060 }
1061
1062 if ( pparam->bYUV422 )
1063 regval |= 0x10;
1064 else
1065 regval &= ~0x10;
1066
1067 if ( pparam->b422pack )
1068 regval |= 0x80;
1069
1070 if ( pparam->bDramRdContd == 1 )
1071 regval |= 0x20;
1072 else
1073 regval &= ~0x20;
1074
1075 // for backward compatable to saturn
1076 // [3] UV-7bit mode don't care
1077 // [5] dram_rd_md =0
1078 // [6] Fld don't care
1079 // [7] 422pack don'care
1080 HAL_WriteByte(VOP_MPG_JPG_SWITCH, regval);
1081 g_pHalMVOPCtx->bIs422 = pparam->bYUV422;
1082 HAL_WriteRegBit(VOP_REG_DUMMY, !(pparam->bYUV422), VOP_420_BW_SAVE);
1083 HAL_WriteRegBit(VOP_REG_BW_SAVE, !(pparam->bYUV422), VOP_420_BW_SAVE_EX);
1084
1085 if (pparam->u16StripSize == 0)
1086 {
1087 if (pparam->bSD)
1088 {
1089 u16strip = 720;
1090 u16strip_lsb = 720;
1091 }
1092 else
1093 {
1094 u16strip = 1920;
1095 u16strip_lsb = 1920;
1096 }
1097 }
1098 else
1099 {
1100 u16strip = pparam->u16StripSize;
1101 u16strip_lsb = pparam->u16StripSize;
1102 }
1103
1104 // set dc_strip[7:0]
1105 if ( pparam->bDramRdContd == 0 )
1106 {
1107 u16strip = (u16strip + 31) / 32 * 32; //need align for monaco
1108 u16strip = u16strip/8;
1109 u16strip_lsb = (u16strip_lsb+127)/128;
1110 u16strip_lsb *= 4;
1111 }
1112 else
1113 {
1114 if ( pparam->b422pack )
1115 {
1116 if (E_MVOP_RGB_888 == g_pHalMVOPCtx->eMainRgbFmt)
1117 {
1118 u16strip *= 2; //4bytes/pixel (yuv422:2bytes/pixel)
1119 }
1120 //VOP_REG_STRIP_ALIGN and Mirror mode are mutually exclusive, after M10(support mirror), VOP_DC_STRIP_H
1121 //replace VOP_REG_STRIP_ALIGN, which supported maximun Hsize is 8188
1122 #if 0
1123 // [071016 Andy] support YUV422 pack mode
1124 if ((u16strip < 1024) || g_pHalMVOPCtx->bMirrorMode)
1125 {
1126 u16strip = u16strip/4;
1127 // dont extend strip len
1128 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1129 }
1130 else
1131 {
1132 u16strip = u16strip/8;
1133 // extend strip len to 2048
1134 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 1, BIT0);
1135 }
1136 #endif
1137 u16strip = u16strip/4;
1138 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1139 }
1140 else
1141 {
1142 u16strip = u16strip/8;
1143 }
1144 }
1145
1146 if (u16strip >= 256 )
1147 {
1148 HAL_WriteByte(VOP_DC_STRIP_H, (u16strip>>8));
1149 //reg_dc_strip_h[2:0] = reg_dc_strip[10:8]
1150 }
1151 else
1152 {
1153 HAL_WriteByteMask(VOP_DC_STRIP_H, 0, BIT0 | BIT1 | BIT2);
1154 }
1155
1156 regval = u16strip;
1157 HAL_WriteByte(VOP_DC_STRIP, regval);
1158 //LSB strip
1159 HAL_WriteByte(VOP_DC_STRIP_LSB, u16strip_lsb & 0x3ff);
1160
1161
1162 HAL_MVOP_SetYUVBaseAdd(pparam->u32YOffset, pparam->u32UVOffset,
1163 pparam->bProgressive, pparam->b422pack);
1164
1165 if (E_MVOP_RPTFLD_NONE != g_pHalMVOPCtx->eRepeatField)
1166 {
1167 MVOP_DBG("%s reset eRepeatField=%x ==>", __FUNCTION__, g_pHalMVOPCtx->eRepeatField);
1168 //To output the same field for single field input,
1169 //do NOT set h'3B[9]=1 and h'11[12]=0
1170 g_pHalMVOPCtx->eRepeatField = E_MVOP_RPTFLD_NONE; //reset the flag to repeat field
1171 MVOP_DBG(" %x\n", g_pHalMVOPCtx->eRepeatField);
1172 }
1173
1174 // HSize
1175 MS_U16 u16HSize = ALIGN_UPTO_16(pparam->u16HSize);
1176 if (u16HSize != pparam->u16HSize)
1177 {
1178 MVOP_DBG(MVOP_PRINTF("\n\n Change HSize %d to %d\n", pparam->u16HSize, u16HSize);)
1179 }
1180 HAL_WriteByte(VOP_JPG_HSIZE , LOWBYTE( u16HSize ));
1181 HAL_WriteByte((VOP_JPG_HSIZE + 1), HIGHBYTE( u16HSize ));
1182
1183 // VSize
1184 MS_U16 u16VSize = pparam->u16VSize;
1185 if (g_pHalMVOPCtx->bMirrorModeVer)
1186 {
1187 u16VSize = ALIGN_UPTO_4(pparam->u16VSize);
1188 MVOP_DBG(MVOP_PRINTF("\n\n Change VSize %d to %d\n", pparam->u16VSize, u16VSize);)
1189 }
1190 HAL_WriteByte(VOP_JPG_VSIZE , LOWBYTE( u16VSize ));
1191 HAL_WriteByte((VOP_JPG_VSIZE + 1), HIGHBYTE( u16VSize ));
1192 }
1193
1194 HAL_MVOP_LoadReg();
1195 }
1196
1197
HAL_MVOP_EnableUVShift(MS_BOOL bEnable)1198 void HAL_MVOP_EnableUVShift(MS_BOOL bEnable)
1199 {
1200 MS_U8 regval;
1201
1202 regval = HAL_ReadByte(VOP_MPG_JPG_SWITCH);
1203
1204 if (((regval & BIT4) == BIT4) && ((regval & 0x3)== 0x2))
1205 { // 422 with MCU control mode
1206 if (bEnable)
1207 {
1208 MS_ASSERT(0);
1209 }
1210 }
1211
1212 // output 420 and interlace
1213 //[IP - Sheet] : Main Page --- 420CUP
1214 //[Project] : Titania2
1215 //[Description]: Chroma artifacts when 420to422 is applied duplicate method.
1216 //[Root cause]: Apply 420to422 average algorithm to all DTV input cases.
1217 //The average algorithm must cooperate with MVOP.
1218 HAL_WriteByteMask(VOP_UV_SHIFT, (bEnable)?1:0, 0x3);
1219 }
1220
1221 static MS_BOOL _bEnable60P = false;
HAL_MVOP_SetEnable60P(MS_BOOL bEnable)1222 void HAL_MVOP_SetEnable60P(MS_BOOL bEnable)
1223 {
1224 _bEnable60P = bEnable;
1225 }
1226
1227 static MS_BOOL _bEnable4k2kClk = false;
HAL_MVOP_SetEnable4k2kClk(MS_BOOL bEnable)1228 void HAL_MVOP_SetEnable4k2kClk(MS_BOOL bEnable)
1229 {
1230 _bEnable4k2kClk = bEnable;
1231 }
1232
HAL_MVOP_SetEnable4k2k2P(MS_BOOL bEnable)1233 void HAL_MVOP_SetEnable4k2k2P(MS_BOOL bEnable)
1234 {
1235 g_pHalMVOPCtx->bIs2p = bEnable;
1236 HAL_WriteRegBit(VOP_REG_4K2K_2P, bEnable, VOP_4K2K_2P);
1237
1238 }
1239
HAL_MVOP_EnableFreerunMode(MS_BOOL bEnable)1240 void HAL_MVOP_EnableFreerunMode(MS_BOOL bEnable)
1241 {
1242 if (g_pHalMVOPCtx == NULL)
1243 {
1244 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1245 return;
1246 }
1247 g_pHalMVOPCtx->bEnableFreerunMode = bEnable;
1248 }
1249
HAL_MVOP_SetVSyncMode(MS_U8 u8Mode)1250 void HAL_MVOP_SetVSyncMode(MS_U8 u8Mode)
1251 {
1252 if (g_pHalMVOPCtx == NULL)
1253 {
1254 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1255 return;
1256 }
1257 if (1==u8Mode)
1258 {
1259 g_pHalMVOPCtx->bNewVSyncMode = TRUE;
1260 }
1261 else
1262 {
1263 g_pHalMVOPCtx->bNewVSyncMode = FALSE;
1264 }
1265 }
1266
HAL_MVOP_SetOutputTiming(MVOP_Timing * ptiming)1267 void HAL_MVOP_SetOutputTiming( MVOP_Timing *ptiming )
1268 {
1269 MS_U8 regval;
1270
1271 if (g_pHalMVOPCtx == NULL)
1272 {
1273 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1274 return;
1275 }
1276
1277 HAL_WriteByte(VOP_FRAME_VCOUNT , LOWBYTE( ptiming->u16V_TotalCount ));
1278 HAL_WriteByte((VOP_FRAME_VCOUNT + 1), HIGHBYTE( ptiming->u16V_TotalCount ));
1279 HAL_WriteByte(VOP_FRAME_HCOUNT , LOWBYTE( ptiming->u16H_TotalCount ));
1280 HAL_WriteByte((VOP_FRAME_HCOUNT + 1), HIGHBYTE( ptiming->u16H_TotalCount ));
1281
1282 HAL_WriteByte((VOP_VB0_STR ), LOWBYTE( ptiming->u16VBlank0_Start ));
1283 HAL_WriteByte((VOP_VB0_STR + 1), HIGHBYTE( ptiming->u16VBlank0_Start ));
1284 HAL_WriteByte((VOP_VB0_END ), LOWBYTE( ptiming->u16VBlank0_End ));
1285 HAL_WriteByte((VOP_VB0_END + 1), HIGHBYTE( ptiming->u16VBlank0_End ));
1286 HAL_WriteByte((VOP_VB1_STR ), LOWBYTE( ptiming->u16VBlank1_Start ));
1287 HAL_WriteByte((VOP_VB1_STR + 1), HIGHBYTE( ptiming->u16VBlank1_Start ));
1288 HAL_WriteByte((VOP_VB1_END ), LOWBYTE( ptiming->u16VBlank1_End ));
1289 HAL_WriteByte((VOP_VB1_END + 1), HIGHBYTE( ptiming->u16VBlank1_End ));
1290 HAL_WriteByte((VOP_TF_STR ), LOWBYTE( ptiming->u16TopField_Start ));
1291 HAL_WriteByte((VOP_TF_STR + 1), HIGHBYTE( ptiming->u16TopField_Start ));
1292 HAL_WriteByte((VOP_BF_STR ), LOWBYTE( ptiming->u16BottomField_Start ));
1293 HAL_WriteByte((VOP_BF_STR + 1), HIGHBYTE( ptiming->u16BottomField_Start ));
1294 HAL_WriteByte((VOP_HACT_STR ), LOWBYTE( ptiming->u16HActive_Start ));
1295 HAL_WriteByte((VOP_HACT_STR + 1), HIGHBYTE( ptiming->u16HActive_Start ));
1296
1297 HAL_WriteByte((VOP_TF_VS ), LOWBYTE( ptiming->u16TopField_VS ));
1298 HAL_WriteByte((VOP_TF_VS + 1), HIGHBYTE( ptiming->u16TopField_VS ));
1299 HAL_WriteByte((VOP_BF_VS ), LOWBYTE( ptiming->u16BottomField_VS ));
1300 HAL_WriteByte((VOP_BF_VS + 1), HIGHBYTE( ptiming->u16BottomField_VS ));
1301
1302 if((ptiming->u16Height >= 2160 || ptiming->u16Width >= 3840) && (ptiming->bInterlace == FALSE))
1303 {
1304 //Monet/Mooney 4k2k pmode default 30 lines forwarding.
1305 g_pHalMVOPCtx->bNewVSyncMode = TRUE;
1306 g_pHalMVOPCtx->u16VsyncLines = 0;
1307 }
1308
1309 if(g_pHalMVOPCtx->bNewVSyncMode)
1310 {
1311 #define NEW_VSYNC_MODE_ADVANCE_LINECNT 30
1312 MS_U16 u16BottomField_VS2MVD;
1313 MS_U16 u16TopField_VS2MVD;
1314 MVOP_DBG(MVOP_PRINTF("MVOP use new vync mode, forwarding %d lines\n",NEW_VSYNC_MODE_ADVANCE_LINECNT);)
1315
1316 if(g_pHalMVOPCtx->u16VsyncLines == 0)
1317 u16BottomField_VS2MVD = ptiming->u16BottomField_VS - NEW_VSYNC_MODE_ADVANCE_LINECNT;
1318 else
1319 u16BottomField_VS2MVD = ptiming->u16BottomField_VS - g_pHalMVOPCtx->u16VsyncLines;
1320
1321 MVOP_DBG(MVOP_PRINTF("BottomField VS ori=0x%x, new=0x%x\n", ptiming->u16BottomField_VS, u16BottomField_VS2MVD);)
1322 HAL_WriteByte((VOP_BF_VS_MVD ), LOWBYTE( u16BottomField_VS2MVD ));
1323 HAL_WriteByte((VOP_BF_VS_MVD + 1), HIGHBYTE( u16BottomField_VS2MVD ));
1324
1325 if(g_pHalMVOPCtx->u16VsyncLines == 0)
1326 u16TopField_VS2MVD = ptiming->u16V_TotalCount - NEW_VSYNC_MODE_ADVANCE_LINECNT;
1327 else
1328 u16TopField_VS2MVD = ptiming->u16V_TotalCount - g_pHalMVOPCtx->u16VsyncLines;
1329
1330 MVOP_DBG(MVOP_PRINTF("TopField VS Vtt=0x%x, new=0x%x\n", ptiming->u16V_TotalCount, u16TopField_VS2MVD);)
1331 HAL_WriteByte((VOP_TF_VS_MVD ), LOWBYTE( u16TopField_VS2MVD ));
1332 HAL_WriteByte((VOP_TF_VS_MVD + 1), HIGHBYTE( u16TopField_VS2MVD ));
1333
1334 #if SUPPORT_FILED_DB // t/b signal 30 lines forwarding
1335 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_DC2MVD_FLD_SEL);
1336 HAL_WriteRegBit(VOP_REG_BW_THD_H, 1, REG_MVD_FLD_SEL);
1337
1338 HAL_WriteByte((VOP_TF_STR_MVD ), LOWBYTE( u16TopField_VS2MVD ));
1339 HAL_WriteByte((VOP_TF_STR_MVD + 1), HIGHBYTE( u16TopField_VS2MVD ));
1340 HAL_WriteByte((VOP_BF_STR_MVD ), LOWBYTE( u16BottomField_VS2MVD ));
1341 HAL_WriteByte((VOP_BF_STR_MVD + 1), HIGHBYTE( u16BottomField_VS2MVD ));
1342 #endif
1343
1344 HAL_WriteRegBit(VOP_GCLK, 0, VOP_GCLK_MIU_ON);
1345
1346 HAL_WriteRegBit(VOP_CTRL1, 1, VOP_MVD_VS_MD); //Use new vsync
1347
1348 g_pHalMVOPCtx->bNewVSyncMode = FALSE; //restore to original mode
1349 }
1350 else
1351 {
1352 MS_U16 u16BottomField_VS2MVD = 0x200;
1353 HAL_WriteByte((VOP_BF_VS_MVD ), LOWBYTE( u16BottomField_VS2MVD ));
1354 HAL_WriteByte((VOP_BF_VS_MVD + 1), HIGHBYTE( u16BottomField_VS2MVD ));
1355
1356 MS_U16 u16TopField_VS2MVD = 0x200;
1357 HAL_WriteByte((VOP_TF_VS_MVD ), LOWBYTE( u16TopField_VS2MVD ));
1358 HAL_WriteByte((VOP_TF_VS_MVD + 1), HIGHBYTE( u16TopField_VS2MVD ));
1359 HAL_WriteRegBit(VOP_CTRL1, 0, VOP_MVD_VS_MD);
1360 }
1361
1362 // + S3, set default IMG_HSTR, IMG_VSTR0, IMG_VSTR1
1363 #ifdef _SUPPORT_IMG_OFFSET_
1364 HAL_WriteByte((VOP_IMG_HSTR ), LOWBYTE( ptiming->u16HImg_Start));
1365 HAL_WriteByte((VOP_IMG_HSTR + 1), HIGHBYTE( ptiming->u16HImg_Start ));
1366 HAL_WriteByte((VOP_IMG_VSTR0 ), LOWBYTE( ptiming->u16VImg_Start0));
1367 HAL_WriteByte((VOP_IMG_VSTR0+ 1), HIGHBYTE( ptiming->u16VImg_Start0 ));
1368 HAL_WriteByte((VOP_IMG_VSTR1 ), LOWBYTE( ptiming->u16VImg_Start1 ));
1369 HAL_WriteByte((VOP_IMG_VSTR1+ 1), HIGHBYTE( ptiming->u16VImg_Start1 ));
1370 #else
1371 HAL_WriteByte((VOP_IMG_HSTR ), LOWBYTE( ptiming->u16HActive_Start ));
1372 HAL_WriteByte((VOP_IMG_HSTR + 1), HIGHBYTE( ptiming->u16HActive_Start ));
1373 HAL_WriteByte((VOP_IMG_VSTR0 ), LOWBYTE( ptiming->u16VBlank0_End ));
1374 HAL_WriteByte((VOP_IMG_VSTR0+ 1), HIGHBYTE( ptiming->u16VBlank0_End ));
1375 HAL_WriteByte((VOP_IMG_VSTR1 ), LOWBYTE( ptiming->u16VBlank1_End ));
1376 HAL_WriteByte((VOP_IMG_VSTR1+ 1), HIGHBYTE( ptiming->u16VBlank1_End ));
1377 #endif
1378 // select mvop output from frame color(black)
1379 HAL_WriteByte((VOP_TST_IMG + 1), 0x10);
1380 HAL_WriteByte((VOP_U_PAT ), 0x80);
1381 HAL_WriteByte((VOP_U_PAT + 1), 0x80);
1382 // set mvop src to test pattern
1383 regval = HAL_ReadByte(VOP_TST_IMG);
1384 HAL_WriteByte(VOP_TST_IMG, 0x02);
1385 // make changed registers take effect
1386 HAL_MVOP_LoadReg();
1387
1388 HAL_MVOP_SetMIUReqMask(TRUE);
1389 // reset mvop to avoid timing change cause mvop hang-up
1390 HAL_MVOP_Rst();
1391 HAL_MVOP_SetMIUReqMask(FALSE);
1392
1393 // select mvop output from mvd
1394 HAL_WriteByte(VOP_TST_IMG, 0x00);
1395 HAL_WriteByte(VOP_TST_IMG, regval);
1396 HAL_WriteRegBit(VOP_CTRL0, ptiming->bHDuplicate, BIT2);// H pixel duplicate
1397
1398 #if 0
1399 MVOP_DBG(MVOP_PRINTF("\nMVOP SetOutputTiming\n");)
1400 MVOP_DBG(MVOP_PRINTF(" VTot=%u,\t",ptiming->u16V_TotalCount);)
1401 MVOP_DBG(MVOP_PRINTF(" HTot=%u,\t",ptiming->u16H_TotalCount);)
1402 MVOP_DBG(MVOP_PRINTF(" I/P=%u\n",ptiming->bInterlace);)
1403 MVOP_DBG(MVOP_PRINTF(" W=%u,\t",ptiming->u16Width);)
1404 MVOP_DBG(MVOP_PRINTF(" H=%u,\t",ptiming->u16Height);)
1405 MVOP_DBG(MVOP_PRINTF(" FRate=%u,\t",ptiming->u8Framerate);)
1406 MVOP_DBG(MVOP_PRINTF(" HFreq=%u\n",ptiming->u16H_Freq);)
1407 MVOP_DBG(MVOP_PRINTF(" Num=0x%x,\t",ptiming->u16Num);)
1408 MVOP_DBG(MVOP_PRINTF(" Den=0x%x,\t",ptiming->u16Den);)
1409 MVOP_DBG(MVOP_PRINTF(" u16ExpFRate=%u #\n\n", ptiming->u16ExpFrameRate);)
1410 #endif
1411 }
1412
HAL_MVOP_SetDCClk(MS_U8 clkNum,MS_BOOL bEnable)1413 void HAL_MVOP_SetDCClk(MS_U8 clkNum, MS_BOOL bEnable)
1414 {
1415 MS_ASSERT( (clkNum==0) || (clkNum==1) );
1416 if (clkNum==0)
1417 {
1418 HAL_WriteRegBit(REG_CKG_DC0, !bEnable, CKG_DC0_GATED);
1419 }
1420 }
1421
HAL_MVOP_SetDCSRAMClk(MS_U8 clkNum,MS_BOOL bEnable)1422 void HAL_MVOP_SetDCSRAMClk(MS_U8 clkNum, MS_BOOL bEnable)
1423 {
1424 MS_ASSERT( (clkNum==0) || (clkNum==1) );
1425 if (clkNum==0)
1426 {
1427 HAL_WriteRegBit(REG_CKG_DC_SRAM, !bEnable, CKG_DC0_SRAM);
1428 }
1429 }
1430
HAL_MVOP_SetSynClk(MVOP_Timing * ptiming)1431 void HAL_MVOP_SetSynClk(MVOP_Timing *ptiming)
1432 {
1433 if (g_pHalMVOPCtx == NULL)
1434 {
1435 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1436 return;
1437 }
1438 if(g_pHalMVOPCtx->bEnableFreerunMode)
1439 {
1440 MS_U64 u64mpll_clock = MPLL_CLOCK_216 << 27 ; //mvop hw bug, tsp default use 216MHz mpll clock @ maserati
1441 if(HAL_ReadRegBit(REG_CLK_SYN_STC, BIT0) == BIT0) //check stc1 clock use 432 or 216
1442 {
1443 u64mpll_clock = MPLL_CLOCK_432 << 27 ;
1444 }
1445 MS_U64 u64exp_clock = (((MS_U64)ptiming->u16H_TotalCount * (MS_U64)ptiming->u16V_TotalCount * (MS_U64)ptiming->u16ExpFrameRate)/1000);
1446 do_div(u64mpll_clock, u64exp_clock);
1447 MS_U32 u32FreerunClk = (MS_U32)u64mpll_clock;
1448 HAL_MVOP_SetFrequency(HALMVOP_FREERUNMODE);
1449 HAL_WriteByte((REG_DC0_FREERUN_CW_L ), LOWBYTE((MS_U16)u32FreerunClk));
1450 HAL_WriteByte((REG_DC0_FREERUN_CW_L+1), HIGHBYTE((MS_U16)u32FreerunClk));
1451 HAL_WriteByte((REG_DC0_FREERUN_CW_H ), LOWBYTE((MS_U16)(u32FreerunClk >> 16)));
1452 HAL_WriteByte((REG_DC0_FREERUN_CW_H+1), HIGHBYTE((MS_U16)(u32FreerunClk >> 16)));
1453 HAL_WriteRegBit(REG_UPDATE_DC0_CW, 1, UPDATE_DC0_FREERUN_CW);
1454 HAL_WriteRegBit(REG_UPDATE_DC0_CW, 0, UPDATE_DC0_FREERUN_CW);
1455 }
1456 else if (_bEnable60P)
1457 {
1458 //Set DC1 Timing
1459 MS_U32 u32FrameRate = (MS_U32)ptiming->u16ExpFrameRate;
1460 MS_U32 u32VSize = 1024;
1461 MS_U32 u32HSize = ((86400000 / u32FrameRate) * 1000) / u32VSize;
1462
1463 if(u32HSize > 4096)
1464 MVOP_PRINTF("[Warning] xc support u32HSize > 4096 after CL 712830\n");
1465
1466 HAL_MVOP_SetFrequency(HAL_MVOP_GetMaxFreerunClk());
1467
1468 HAL_WriteRegBit(VOP_REG_YC422_EN_H, 0, VOP_FRAME_RST); // reg_frame_rst = 0
1469
1470 HAL_WriteRegBit(VOP_CTRL0, DISABLE, VOP_FSYNC_EN); // frame sync disable
1471 }
1472 else if (_bEnable4k2kClk)
1473 {
1474 HAL_MVOP_SetFrequency(HAL_MVOP_Get4k2kClk());
1475
1476 HAL_WriteRegBit(VOP_REG_YC422_EN_H, 0, VOP_FRAME_RST); // reg_frame_rst = 0
1477
1478 HAL_WriteRegBit(VOP_CTRL0, DISABLE, VOP_FSYNC_EN); // frame sync disable
1479 }
1480 else
1481 {
1482 HAL_MVOP_SetFrequency(HALMVOP_SYNCMODE);
1483 HAL_WriteByte((REG_DC0_NUM ), LOWBYTE( ptiming->u16Num));
1484 HAL_WriteByte((REG_DC0_NUM+1), HIGHBYTE(ptiming->u16Num));
1485 HAL_WriteByte((REG_DC0_DEN ), LOWBYTE( ptiming->u16Den));
1486 HAL_WriteByte((REG_DC0_DEN+1), HIGHBYTE(ptiming->u16Den));
1487 HAL_WriteRegBit(REG_UPDATE_DC0_CW, 1, UPDATE_DC0_SYNC_CW);
1488 HAL_WriteRegBit(REG_UPDATE_DC0_CW, 0, UPDATE_DC0_SYNC_CW);
1489 }
1490 }
1491
1492
HAL_MVOP_SetMonoMode(MS_BOOL bEnable)1493 void HAL_MVOP_SetMonoMode(MS_BOOL bEnable)
1494 {
1495 if(bEnable)
1496 {
1497 HAL_WriteByte(VOP_U_PAT , 0x80);
1498 HAL_WriteByte((VOP_U_PAT+1), 0x80);
1499
1500 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 1, BIT1); // Mono mode enable
1501 }
1502 else
1503 {
1504 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 0, BIT1); //Mono mode disable
1505 }
1506 }
1507
1508 /******************************************************************************/
1509 /// Set MVOP for H264 Hardwire Mode
1510 /******************************************************************************/
HAL_MVOP_SetH264HardwireMode(void)1511 void HAL_MVOP_SetH264HardwireMode(void)
1512 {
1513 // Hardwire mode
1514 HAL_WriteByte(VOP_MPG_JPG_SWITCH, 0x00);
1515
1516 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1517
1518 //16*32 tile format
1519 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
1520
1521 // SVD mode enable
1522 HAL_WriteByteMask(VOP_INPUT_SWITCH1, BIT3, BIT2|BIT3);
1523
1524 // set mvop to 128bit_i128 interface
1525 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
1526
1527 // Only for Monaco: Disable deciding bot by top address + 2
1528 HAL_WriteRegBit(VOP_MIRROR_CFG, 0, VOP_FIELD_FROM_ADDR);
1529
1530 // Enable mfdec setting from wb from Manhattan
1531 HAL_WriteRegBit(VOP_REG_MFDEC_2_L, 1, VOP_MF_FROM_WB);
1532 HAL_WriteRegBit(VOP_REG_DUMMY, 1, VOP_32x32_WB); //32x32 from wb
1533
1534 // H264 use WISHBONE(R2) interface
1535 //HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, VOP_R2_WISHBONE);
1536
1537 // Write trigger
1538 HAL_MVOP_LoadReg();
1539 }
1540
1541 /******************************************************************************/
1542 /// Set MVOP for RM Hardwire Mode
1543 /******************************************************************************/
HAL_MVOP_SetRMHardwireMode(void)1544 void HAL_MVOP_SetRMHardwireMode(void)
1545 {
1546 HAL_MVOP_SetH264HardwireMode();
1547 }
1548
1549 /******************************************************************************/
1550 /// Set MVOP for JPEG Hardwire Mode
1551 /******************************************************************************/
HAL_MVOP_SetJpegHardwireMode(void)1552 void HAL_MVOP_SetJpegHardwireMode(void)
1553 {
1554 MS_U8 regval = 0x00;
1555
1556 regval |= 0x80; // packmode
1557 regval |= 0x20; // Dram Rd Contd
1558 HAL_WriteByte(VOP_MPG_JPG_SWITCH, regval);
1559 g_pHalMVOPCtx->bIs422 = 1;
1560 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_420_BW_SAVE);
1561 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
1562
1563 // Write trigger
1564 HAL_MVOP_LoadReg();
1565 }
1566
1567 /******************************************************************************/
1568 /// Set MVOP for EVD Hardwire Mode
1569 /******************************************************************************/
HAL_MVOP_SetEVDHardwireMode(MS_U16 u16ECOVersion)1570 void HAL_MVOP_SetEVDHardwireMode(MS_U16 u16ECOVersion)
1571 {
1572 UNUSED(u16ECOVersion);
1573
1574 // Hardwire mode
1575 HAL_WriteByte(VOP_MPG_JPG_SWITCH, 0x00);
1576
1577 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1578
1579 //16*32 tile format
1580 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
1581
1582 // EVD use HVD interface
1583 //HAL_WriteByteMask(VOP_INPUT_SWITCH1, BIT3, BIT2|BIT3);
1584
1585 // EVD mode enable
1586 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, EVD_ENABLE);
1587
1588 // set mvop to 128bit_i128 interface
1589 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
1590
1591 // set evd flag for interlace mode setting
1592 g_pHalMVOPCtx->bIsH265 = 1;
1593
1594 // Enable mfdec setting from wb
1595 HAL_WriteRegBit(VOP_REG_MFDEC_2_L, 1, VOP_MF_FROM_WB);
1596
1597 // 10 bits from wb
1598 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_H, 1, VOP_INFO_FROM_CODEC_10BIT);
1599
1600 HAL_WriteByteMask(VOP_REG_MASK, 0, VOP_LSB_REQ_MASK);//10 bits bw control by vdec fw
1601
1602 // Write trigger
1603 HAL_MVOP_LoadReg();
1604 }
1605
1606 /******************************************************************************/
1607 /// Set MVOP for VP9 Hardwire Mode
1608 /// vp9 hw change in Manhathan: tile mode 16x32
1609 /******************************************************************************/
HAL_MVOP_SetVP9HardwireMode(void)1610 void HAL_MVOP_SetVP9HardwireMode(void)
1611 {
1612 // Hardwire mode
1613 HAL_WriteByte(VOP_MPG_JPG_SWITCH, 0x00);
1614
1615 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1616
1617 //16*32 tile format
1618 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
1619
1620 // VP9 use WISHBONE(R2) interface
1621 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, VOP_R2_WISHBONE);
1622
1623 // Enable VP9 dram continue mode
1624 //HAL_WriteRegBit(VOP_MPG_JPG_SWITCH, 1, VOP_DRAM_RD_MODE);
1625
1626 // set mvop to 128bit_i128 interface
1627 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
1628
1629 // Enable mfdec setting from wb
1630 HAL_WriteRegBit(VOP_REG_MFDEC_2_L, 1, VOP_MF_FROM_WB);
1631
1632 // EVD mode enable
1633 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, EVD_ENABLE);
1634 // 10 bits from wb
1635 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_H, 1, VOP_INFO_FROM_CODEC_10BIT);
1636
1637 HAL_WriteByteMask(VOP_REG_MASK, 0, VOP_LSB_REQ_MASK);//10 bits bw control by vdec fw
1638
1639 // Write trigger
1640 HAL_MVOP_LoadReg();
1641 }
1642
1643 /******************************************************************************/
1644 /// Set MVOP for EVD MCU Mode
1645 /******************************************************************************/
HAL_MVOP_SetEVDFeature(MVOP_DevID eID,MVOP_EVDFeature * stEVDInput)1646 void HAL_MVOP_SetEVDFeature(MVOP_DevID eID, MVOP_EVDFeature* stEVDInput)
1647 {
1648 switch(eID)
1649 {
1650 case E_MVOP_DEV_0:
1651
1652 HAL_WriteRegBit(VOP_INPUT_SWITCH0, stEVDInput->bEnableEVD, EVD_ENABLE);// 32x32 enable
1653
1654 switch(stEVDInput->eEVDBit[Y_INFO])
1655 {
1656 case E_MVOP_EVD_8BIT:
1657 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_Y_EN);
1658 break;
1659 case E_MVOP_EVD_10BIT:
1660 HAL_WriteRegBit(VOP_EVD_10B_EN, 1, VOP_EVD_10B_Y_EN);
1661 break;
1662 default:
1663 break;
1664 }
1665
1666 switch(stEVDInput->eEVDBit[UV_INFO])
1667 {
1668 case E_MVOP_EVD_8BIT:
1669 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_UV_EN);
1670 break;
1671 case E_MVOP_EVD_10BIT:
1672 HAL_WriteRegBit(VOP_EVD_10B_EN, 1, VOP_EVD_10B_UV_EN);
1673 break;
1674 default:
1675 break;
1676 }
1677
1678 //LSB BW Discard MASK
1679 if(stEVDInput->eEVDBit[Y_INFO] || stEVDInput->eEVDBit[UV_INFO])
1680 {
1681 HAL_WriteByteMask(VOP_REG_MASK, 0, VOP_LSB_REQ_MASK);
1682 HAL_WriteRegBit(VOP_UV_SHIFT, 0, VOP_GCLK_MIU_ON);
1683 MVOP_DBG(MVOP_PRINTF("[Debug] 10 bits display\n"););
1684 }
1685 else
1686 {
1687 //HAL_WriteByteMask(VOP_REG_MASK, BIT1, VOP_LSB_REQ_MASK);
1688 MVOP_DBG(MVOP_PRINTF("[Debug] 10 bits bw riu control default enable\n"););
1689 }
1690
1691 // Write trigger
1692 HAL_MVOP_LoadReg();
1693 break;
1694 case E_MVOP_DEV_1:
1695 #if MVOP_SUPPORT_SUB
1696
1697 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), stEVDInput->bEnableEVD, EVD_ENABLE);// 32x32 enable
1698
1699 switch(stEVDInput->eEVDBit[Y_INFO])
1700 {
1701 case E_MVOP_EVD_8BIT:
1702 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_Y_EN);
1703 break;
1704 case E_MVOP_EVD_10BIT:
1705 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 1, VOP_EVD_10B_Y_EN);
1706 break;
1707 default:
1708 break;
1709 }
1710
1711 switch(stEVDInput->eEVDBit[UV_INFO])
1712 {
1713 case E_MVOP_EVD_8BIT:
1714 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_UV_EN);
1715 break;
1716 case E_MVOP_EVD_10BIT:
1717 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 1, VOP_EVD_10B_UV_EN);
1718 break;
1719 default:
1720 break;
1721 }
1722
1723 //LSB BW Discard MASK
1724 if(stEVDInput->eEVDBit[Y_INFO] || stEVDInput->eEVDBit[UV_INFO])
1725 {
1726 HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), 0, VOP_LSB_REQ_MASK);
1727 HAL_WriteRegBit(SUB_REG(VOP_UV_SHIFT), 0, VOP_GCLK_MIU_ON);
1728 MVOP_DBG(MVOP_PRINTF("[Debug] 10 bits display\n"););
1729 }
1730 else
1731 {
1732 //HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), BIT1, VOP_LSB_REQ_MASK);
1733 MVOP_DBG(MVOP_PRINTF("[Debug] 10 bits bw riu control default enable\n"););
1734 }
1735 // Write trigger
1736 HAL_MVOP_SubLoadReg();
1737 #endif
1738 break;
1739 default:
1740 break;
1741 }
1742
1743 }
1744
1745
1746 ///Enable 3D L/R dual buffer mode
HAL_MVOP_Enable3DLR(MS_BOOL bEnable)1747 MS_BOOL HAL_MVOP_Enable3DLR(MS_BOOL bEnable)
1748 {
1749 if (g_pHalMVOPCtx == NULL)
1750 {
1751 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1752 return FALSE;
1753 }
1754 HAL_WriteRegBit(VOP_MULTI_WIN_CFG0, bEnable, VOP_LR_BUF_MODE);
1755 g_pHalMVOPCtx->b3DLRMode = bEnable;
1756 if(bEnable)
1757 {
1758 //only for monaco: do not wait for data ready.
1759 HAL_WriteByteMask(VOP_NOT_WAIT_READ_DATA, 2, VOP_NOT_WAIT_RDLAT);
1760 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
1761 }
1762 else
1763 {
1764 HAL_WriteByteMask(VOP_NOT_WAIT_READ_DATA, 0, VOP_NOT_WAIT_RDLAT);
1765 }
1766 return TRUE;
1767 }
1768
1769 ///Get if 3D L/R mode is enabled
HAL_MVOP_Get3DLRMode(void)1770 MS_BOOL HAL_MVOP_Get3DLRMode(void)
1771 {
1772 if (g_pHalMVOPCtx == NULL)
1773 {
1774 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1775 return FALSE;
1776 }
1777 return g_pHalMVOPCtx->b3DLRMode;
1778 }
1779
HAL_MVOP_GetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters * pMvopTimingInfo)1780 MS_BOOL HAL_MVOP_GetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters *pMvopTimingInfo)
1781 {
1782 if(NULL == pMvopTimingInfo)
1783 {
1784 MVOP_PRINTF("HAL_MVOP_GetTimingInfoFromRegisters():pMvopTimingInfo is NULL\n");
1785 return FALSE;
1786 }
1787 if(HAL_MVOP_GetEnableState() == FALSE)
1788 {
1789 MVOP_PRINTF("MVOP is not enabled!\n");
1790 pMvopTimingInfo->bEnabled = FALSE;
1791 return FALSE;
1792 }
1793 pMvopTimingInfo->bEnabled = TRUE;
1794 pMvopTimingInfo->u16H_TotalCount = (HAL_ReadByte((VOP_FRAME_HCOUNT + 1))<< 8) | (HAL_ReadByte((VOP_FRAME_HCOUNT)));
1795 pMvopTimingInfo->u16V_TotalCount = (HAL_ReadByte((VOP_FRAME_VCOUNT + 1))<< 8) | (HAL_ReadByte((VOP_FRAME_VCOUNT)));
1796 pMvopTimingInfo->u16VBlank0_Start = (HAL_ReadByte((VOP_VB0_STR + 1))<< 8) | (HAL_ReadByte((VOP_VB0_STR)));
1797 pMvopTimingInfo->u16VBlank0_End = (HAL_ReadByte((VOP_VB0_END + 1))<< 8) | (HAL_ReadByte((VOP_VB0_END)));
1798 pMvopTimingInfo->u16VBlank1_Start = (HAL_ReadByte((VOP_VB1_STR + 1))<< 8) | (HAL_ReadByte((VOP_VB1_STR)));
1799 pMvopTimingInfo->u16VBlank1_End = (HAL_ReadByte((VOP_VB1_END + 1))<< 8) | (HAL_ReadByte((VOP_VB1_END)));
1800 pMvopTimingInfo->u16TopField_Start = (HAL_ReadByte((VOP_TF_STR + 1))<< 8) | (HAL_ReadByte((VOP_TF_STR)));
1801 pMvopTimingInfo->u16BottomField_Start = (HAL_ReadByte((VOP_BF_STR + 1))<< 8) | (HAL_ReadByte((VOP_BF_STR)));
1802 pMvopTimingInfo->u16HActive_Start = (HAL_ReadByte((VOP_HACT_STR + 1))<< 8) | (HAL_ReadByte((VOP_HACT_STR)));
1803 pMvopTimingInfo->u16TopField_VS = (HAL_ReadByte((VOP_TF_VS + 1))<< 8) | (HAL_ReadByte((VOP_TF_VS)));
1804 pMvopTimingInfo->u16BottomField_VS = (HAL_ReadByte((VOP_BF_VS + 1))<< 8) | (HAL_ReadByte((VOP_BF_VS)));
1805 pMvopTimingInfo->bInterlace = (HAL_ReadRegBit(VOP_CTRL0, BIT7) == BIT7);
1806 return TRUE;
1807 }
1808
HAL_MVOP_SetYUVBaseAdd(MS_PHY u32YOffset,MS_PHY u32UVOffset,MS_BOOL bProgressive,MS_BOOL b422pack)1809 void HAL_MVOP_SetYUVBaseAdd(MS_PHY u32YOffset, MS_PHY u32UVOffset, MS_BOOL bProgressive, MS_BOOL b422pack)
1810 {
1811 MS_PHY u64tmp = 0;
1812
1813 if (g_pHalMVOPCtx == NULL)
1814 {
1815 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1816 return;
1817 }
1818 // Y offset
1819 u64tmp = u32YOffset >> 3;
1820 if ( !bProgressive )
1821 { //Refine Y offset for interlace repeat bottom field
1822 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
1823 {
1824 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
1825 u64tmp += 2;
1826 }
1827 else
1828 {
1829 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
1830 }
1831 }
1832 HAL_WriteByte(VOP_JPG_YSTR0_L, u64tmp & 0xff);
1833 HAL_WriteByte((VOP_JPG_YSTR0_L+1), (u64tmp >> 8) & 0xff);
1834 HAL_WriteByte((VOP_JPG_YSTR0_L+2), (u64tmp >> 16) & 0xff);
1835 HAL_WriteByte((VOP_JPG_YSTR0_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
1836
1837 if (!bProgressive )
1838 { //Y offset of bottom field if interlace
1839 HAL_WriteByte(VOP_JPG_YSTR1_L, u64tmp & 0xff);
1840 HAL_WriteByte((VOP_JPG_YSTR1_L+1), (u64tmp >> 8) & 0xff);
1841 HAL_WriteByte((VOP_JPG_YSTR1_L+2), (u64tmp >> 16) & 0xff);
1842 HAL_WriteByte((VOP_JPG_YSTR1_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
1843 }
1844
1845 if (b422pack)
1846 {
1847 u32UVOffset = u32YOffset + 16; //add 16 for 128bit; add 8 for 64bit
1848 }
1849 // UV offset
1850 u64tmp = u32UVOffset >> 3;
1851 if( !bProgressive )
1852 { //Refine UV offset for interlace repeat bottom field
1853 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
1854 {
1855 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
1856 u64tmp += 2;
1857 }
1858 else
1859 {
1860 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
1861 }
1862 }
1863 HAL_WriteByte(VOP_JPG_UVSTR0_L, u64tmp & 0xff);
1864 HAL_WriteByte((VOP_JPG_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
1865 HAL_WriteByte((VOP_JPG_UVSTR0_L+2), (u64tmp >> 16) & 0xff);
1866 HAL_WriteByte((VOP_JPG_UVSTR0_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
1867
1868 if( !bProgressive )
1869 { //UV offset of bottom field if interlace
1870 HAL_WriteByte(VOP_JPG_UVSTR1_L, u64tmp & 0xff);
1871 HAL_WriteByte((VOP_JPG_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
1872 HAL_WriteByte((VOP_JPG_UVSTR1_L+2), (u64tmp >> 16) & 0xff);
1873 HAL_WriteByte((VOP_JPG_UVSTR1_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
1874 }
1875
1876 return;
1877 }
1878
HAL_MVOP_SetYUVBaseAddMultiView(MVOP_BaseAddInput * stBaseAddInfo)1879 MS_BOOL HAL_MVOP_SetYUVBaseAddMultiView(MVOP_BaseAddInput *stBaseAddInfo)
1880 {
1881 MS_PHY u64tmpY = 0;
1882 MS_PHY u64tmpUV = 0;
1883
1884 if (stBaseAddInfo == NULL)
1885 {
1886 MVOP_DBG(MVOP_PRINTF("%s stBaseAddInfo is NULL pointer\n", __FUNCTION__);)
1887 return FALSE;
1888 }
1889 // Y offset
1890 u64tmpY = (stBaseAddInfo->u32YOffset) >> 3;
1891 // UV offset
1892 u64tmpUV = (stBaseAddInfo->u32UVOffset) >> 3;
1893
1894 switch(stBaseAddInfo->eView)
1895 {
1896 case E_MVOP_MAIN_VIEW:
1897 // Y offset
1898 HAL_WriteByte(VOP_JPG_YSTR0_L, u64tmpY & 0xff);
1899 HAL_WriteByte((VOP_JPG_YSTR0_L+1), (u64tmpY >> 8) & 0xff);
1900 HAL_WriteByte((VOP_JPG_YSTR0_L+2), (u64tmpY >> 16) & 0xff);
1901 HAL_WriteByte((VOP_JPG_YSTR0_L+3), (u64tmpY >> 24) & VOP_YUV_STR_HIBITS);
1902
1903 // UV offset
1904 HAL_WriteByte(VOP_JPG_UVSTR0_L, u64tmpUV & 0xff);
1905 HAL_WriteByte((VOP_JPG_UVSTR0_L+1), (u64tmpUV >> 8) & 0xff);
1906 HAL_WriteByte((VOP_JPG_UVSTR0_L+2), (u64tmpUV >> 16) & 0xff);
1907 HAL_WriteByte((VOP_JPG_UVSTR0_L+3), (u64tmpUV >> 24) & VOP_YUV_STR_HIBITS);
1908 break;
1909 case E_MVOP_2ND_VIEW:
1910 // Y offset
1911 HAL_WriteByte(VOP_JPG_YSTR1_L, u64tmpY & 0xff);
1912 HAL_WriteByte((VOP_JPG_YSTR1_L+1), (u64tmpY >> 8) & 0xff);
1913 HAL_WriteByte((VOP_JPG_YSTR1_L+2), (u64tmpY >> 16) & 0xff);
1914 HAL_WriteByte((VOP_JPG_YSTR1_L+3), (u64tmpY >> 24) & VOP_YUV_STR_HIBITS);
1915
1916 //UV offset
1917 HAL_WriteByte(VOP_JPG_UVSTR1_L, u64tmpUV & 0xff);
1918 HAL_WriteByte((VOP_JPG_UVSTR1_L+1), (u64tmpUV >> 8) & 0xff);
1919 HAL_WriteByte((VOP_JPG_UVSTR1_L+2), (u64tmpUV >> 16) & 0xff);
1920 HAL_WriteByte((VOP_JPG_UVSTR1_L+3), (u64tmpUV >> 24) & VOP_YUV_STR_HIBITS);
1921 break;
1922 default:
1923 break;
1924 }
1925 return TRUE;
1926 }
1927
HAL_MVOP_GetYBaseAdd(void)1928 MS_PHY HAL_MVOP_GetYBaseAdd(void)
1929 {
1930 MS_PHY u64YOffset = 0;
1931 u64YOffset = HAL_ReadByte(VOP_JPG_YSTR0_L)&0xff;
1932 u64YOffset |=((HAL_ReadByte((VOP_JPG_YSTR0_L+1))<<8)&0xff00);
1933 u64YOffset |=((HAL_ReadByte((VOP_JPG_YSTR0_L+2))<<16)&0xff0000);
1934 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
1935 return u64YOffset;
1936 }
1937
HAL_MVOP_GetUVBaseAdd(void)1938 MS_PHY HAL_MVOP_GetUVBaseAdd(void)
1939 {
1940 MS_PHY u64UVOffset = 0;
1941 u64UVOffset = HAL_ReadByte(VOP_JPG_UVSTR0_L)&0xff;
1942 u64UVOffset |=((HAL_ReadByte((VOP_JPG_UVSTR0_L+1))<<8)&0xff00);
1943 u64UVOffset |=((HAL_ReadByte((VOP_JPG_UVSTR0_L+2))<<16)&0xff0000);
1944 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
1945 return u64UVOffset;
1946 }
1947
HAL_MVOP_GetYBaseAddMultiView(MVOP_3DView eView)1948 MS_PHY HAL_MVOP_GetYBaseAddMultiView(MVOP_3DView eView)
1949 {
1950 MS_PHY u64YOffset = 0;
1951 switch(eView)
1952 {
1953 case E_MVOP_MAIN_VIEW:
1954 u64YOffset = HAL_ReadByte(VOP_JPG_YSTR0_L)&0xff;
1955 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR0_L+1))<<8)&0xff00);
1956 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR0_L+2))<<16)&0xff0000);
1957 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
1958 break;
1959 case E_MVOP_2ND_VIEW:
1960 u64YOffset = HAL_ReadByte(VOP_JPG_YSTR1_L)&0xff;
1961 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR1_L+1))<<8)&0xff00);
1962 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR1_L+2))<<16)&0xff0000);
1963 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR1_L+3))<<24)&0x7000000);
1964 break;
1965 default:
1966 u64YOffset = 0;
1967 break;
1968 }
1969 return u64YOffset;
1970 }
1971
HAL_MVOP_GetUVBaseAddMultiView(MVOP_3DView eView)1972 MS_PHY HAL_MVOP_GetUVBaseAddMultiView(MVOP_3DView eView)
1973 {
1974 MS_PHY u64UVOffset = 0;
1975 switch(eView)
1976 {
1977 case E_MVOP_MAIN_VIEW:
1978 u64UVOffset = HAL_ReadByte(VOP_JPG_UVSTR0_L)&0xff;
1979 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR0_L+1))<<8)&0xff00);
1980 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR0_L+2))<<16)&0xff0000);
1981 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
1982 break;
1983 case E_MVOP_2ND_VIEW:
1984 u64UVOffset = HAL_ReadByte(VOP_JPG_UVSTR1_L)&0xff;
1985 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR1_L+1))<<8)&0xff00);
1986 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR1_L+2))<<16)&0xff0000);
1987 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR1_L+3))<<24)&0x7000000);
1988 break;
1989 default:
1990 u64UVOffset = 0;
1991 break;
1992 }
1993 return u64UVOffset;
1994 }
1995
HAL_MVOP_Set3DLRAltOutput_VHalfScaling(MS_BOOL bEnable)1996 MS_BOOL HAL_MVOP_Set3DLRAltOutput_VHalfScaling(MS_BOOL bEnable)
1997 {
1998 MS_BOOL bEnDualBuff = bEnable ? ENABLE : DISABLE; //enable dual buffer
1999 MS_BOOL bEnSWDualBuff = bEnable ? DISABLE : ENABLE; //buffer controlled by HK instead of FW
2000 MS_BOOL bEnMirrMaskBase = bEnable ? DISABLE : ENABLE; //do not mask LSB
2001 MS_BOOL bEnHwFldBase = bEnable ? DISABLE : ENABLE; //hardware calculate field jump base address
2002
2003 if (g_pHalMVOPCtx == NULL)
2004 {
2005 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2006 return FALSE;
2007 }
2008 //Set 0x27[2] = 1 (enable SW dual buffer mode)
2009 HAL_WriteRegBit(VOP_REG_WR, bEnDualBuff, VOP_BUF_DUAL);
2010
2011 //Set 0x38[8] = 0 (use SW dual buffer mode)
2012 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_H, bEnSWDualBuff, VOP_INFO_FROM_CODEC_DUAL_BUFF);
2013
2014 //Set 0x3b[7] = 0 (use MVD/HVD firmware send base)
2015 HAL_WriteRegBit(VOP_MIRROR_CFG, bEnMirrMaskBase, VOP_MASK_BASE_LSB);
2016
2017 //Set 0x3b[5] = 0 (hardware calculate field jump base address)
2018 HAL_WriteRegBit(VOP_MIRROR_CFG, bEnHwFldBase, VOP_HW_FLD_BASE);
2019
2020 g_pHalMVOPCtx->b3DLRAltOutput = bEnable;
2021 return TRUE;
2022 }
2023
HAL_MVOP_Set3DLRAltOutput(MS_BOOL bEnable)2024 MS_BOOL HAL_MVOP_Set3DLRAltOutput(MS_BOOL bEnable)
2025 {
2026 //Set 0x3C[2] = 1 (enable 3D L/R dual buffer line alternative output)
2027 //it works when 0x3C[0] = 1
2028 HAL_WriteRegBit(VOP_MULTI_WIN_CFG0, bEnable, VOP_LR_LA_OUT);
2029 // bw saving not support: LA/SBS
2030 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_420_BW_SAVE);
2031 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
2032 HAL_MVOP_LoadReg();
2033
2034 g_pHalMVOPCtx->b3DLRAltOutput = bEnable;
2035 return TRUE;
2036 }
2037
HAL_MVOP_Set3DLRAltSBSOutput(MS_BOOL bEnable)2038 MS_BOOL HAL_MVOP_Set3DLRAltSBSOutput(MS_BOOL bEnable)
2039 {
2040 //it works when 0x3C[0] = 1 and 0x3C[2] = 1
2041 //Set 0x3C[3] = 1 (3D L/R line alternative read, side-by-side output)
2042 HAL_WriteRegBit(VOP_MULTI_WIN_CFG0, bEnable, VOP_LR_LA2SBS_OUT);
2043 g_pHalMVOPCtx->b3DLRAltSBSOutput = bEnable;
2044 return TRUE;
2045 }
2046
HAL_MVOP_Get3DLRAltOutput(void)2047 MS_BOOL HAL_MVOP_Get3DLRAltOutput(void)
2048 {
2049 if (g_pHalMVOPCtx == NULL)
2050 {
2051 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2052 return FALSE;
2053 }
2054 return g_pHalMVOPCtx->b3DLRAltOutput;
2055 }
2056
HAL_MVOP_Get3DLRAltSBSOutput(void)2057 MS_BOOL HAL_MVOP_Get3DLRAltSBSOutput(void)
2058 {
2059 return g_pHalMVOPCtx->b3DLRAltSBSOutput;
2060 }
2061
HAL_MVOP_GetOutput3DType(void)2062 EN_MVOP_Output_3D_TYPE HAL_MVOP_GetOutput3DType(void)
2063 {
2064 EN_MVOP_Output_3D_TYPE en3DType = E_MVOP_OUTPUT_3D_NONE;
2065 if(g_pHalMVOPCtx->b3DLRMode)
2066 {
2067 if(g_pHalMVOPCtx->b3DLRAltSBSOutput)
2068 {
2069 en3DType = E_MVOP_OUTPUT_3D_SBS;
2070 }
2071 else
2072 {
2073 en3DType = E_MVOP_OUTPUT_3D_TB;
2074 }
2075 }
2076 else if(g_pHalMVOPCtx->b3DLRAltOutput)
2077 {
2078 en3DType = E_MVOP_OUTPUT_3D_LA;
2079 }
2080 return en3DType;
2081 }
2082
HAL_MVOP_Set3DLR2ndCfg(MS_BOOL bEnable)2083 MS_BOOL HAL_MVOP_Set3DLR2ndCfg(MS_BOOL bEnable)
2084 {
2085 //Set 0x3c[7] as 1 to enable
2086 HAL_WriteRegBit(VOP_MULTI_WIN_CFG0, bEnable, VOP_LR_DIFF_SIZE);
2087 return TRUE;
2088 }
2089
HAL_MVOP_Get3DLR2ndCfg(void)2090 MS_BOOL HAL_MVOP_Get3DLR2ndCfg(void)
2091 {
2092 MS_BOOL bEnable = FALSE;
2093 if (VOP_LR_DIFF_SIZE == (VOP_LR_DIFF_SIZE & HAL_ReadRegBit(VOP_MULTI_WIN_CFG0, VOP_LR_DIFF_SIZE)))
2094 {
2095 bEnable = TRUE;
2096 }
2097 return bEnable;
2098 }
2099
HAL_MVOP_GetMirrorMode(MVOP_DevID eID)2100 MVOP_DrvMirror HAL_MVOP_GetMirrorMode(MVOP_DevID eID)
2101 {
2102 MVOP_DrvMirror enMirror = E_VOPMIRROR_NONE;
2103 if (g_pHalMVOPCtx == NULL)
2104 {
2105 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2106 return FALSE;
2107 }
2108 switch(eID)
2109 {
2110 case E_MVOP_DEV_0:
2111 if(g_pHalMVOPCtx->bMirrorModeVer && g_pHalMVOPCtx->bMirrorModeHor)
2112 {
2113 enMirror = E_VOPMIRROR_HVBOTH;
2114 }
2115 else if(g_pHalMVOPCtx->bMirrorModeHor)
2116 {
2117 enMirror = E_VOPMIRROR_HORIZONTALL;
2118 }
2119 else if(g_pHalMVOPCtx->bMirrorModeVer)
2120 {
2121 enMirror = E_VOPMIRROR_VERTICAL;
2122 }
2123 break;
2124 case E_MVOP_DEV_1:
2125 #if MVOP_SUPPORT_SUB
2126 if(g_pHalMVOPCtx->bSubMirrorModeVer &&g_pHalMVOPCtx-> bSubMirrorModeHor)
2127 {
2128 enMirror = E_VOPMIRROR_HVBOTH;
2129 }
2130 else if(g_pHalMVOPCtx->bSubMirrorModeHor)
2131 {
2132 enMirror = E_VOPMIRROR_HORIZONTALL;
2133 }
2134 else if(g_pHalMVOPCtx->bSubMirrorModeVer)
2135 {
2136 enMirror = E_VOPMIRROR_VERTICAL;
2137 }
2138 #endif
2139 break;
2140 default:
2141 break;
2142 }
2143 return enMirror;
2144 }
2145
HAL_MVOP_SetVerDup(MS_BOOL bEnable)2146 MS_BOOL HAL_MVOP_SetVerDup(MS_BOOL bEnable)
2147 {
2148 HAL_WriteRegBit(VOP_CTRL0, bEnable, BIT3);// V line duplicate
2149 return TRUE;
2150 }
2151
HAL_MVOP_GetVerDup(void)2152 MS_BOOL HAL_MVOP_GetVerDup(void)
2153 {
2154 return (HAL_ReadRegBit(VOP_CTRL0, BIT3) == BIT3);
2155 }
2156
HAL_MVOP_SetVerx4Dup(MS_BOOL bEnable)2157 MS_BOOL HAL_MVOP_SetVerx4Dup(MS_BOOL bEnable)
2158 {
2159 HAL_WriteRegBit(VOP_CTRL0, bEnable, BIT3);// x4 duplicate should raise V line duplicate first
2160 HAL_WriteRegBit(VOP_RGB_FMT, bEnable, BIT3);// V line x4 duplicate
2161 return TRUE;
2162 }
2163
HAL_MVOP_SetHorx4Dup(MS_BOOL bEnable)2164 MS_BOOL HAL_MVOP_SetHorx4Dup(MS_BOOL bEnable)
2165 {
2166 HAL_WriteRegBit(VOP_CTRL0, bEnable, BIT2);// x4 duplicate should raise H pixel duplicate first
2167 HAL_WriteRegBit(VOP_RGB_FMT, bEnable, BIT2);// H line x4 duplicate
2168 return TRUE;
2169 }
2170
HAL_MVOP_GetVerx4Dup(void)2171 MS_BOOL HAL_MVOP_GetVerx4Dup(void)
2172 {
2173 return ((HAL_ReadRegBit(VOP_RGB_FMT, BIT3) & HAL_ReadRegBit(VOP_CTRL0, BIT3)) == BIT3);
2174 }
2175
HAL_MVOP_GetHorx4Dup(void)2176 MS_BOOL HAL_MVOP_GetHorx4Dup(void)
2177 {
2178 return ((HAL_ReadRegBit(VOP_RGB_FMT, BIT2) & HAL_ReadRegBit(VOP_CTRL0, BIT2)) == BIT2);
2179 }
2180
HAL_MVOP_GetTopVStart(MVOP_DevID eID)2181 MS_U16 HAL_MVOP_GetTopVStart(MVOP_DevID eID)
2182 {
2183 MS_U16 u16TopVStart = 0;
2184 switch(eID)
2185 {
2186 case E_MVOP_DEV_0:
2187 u16TopVStart = HAL_Read2Byte(VOP_IMG_VSTR0)&0x1fff;
2188 break;
2189 case E_MVOP_DEV_1:
2190 #if MVOP_SUPPORT_SUB
2191 u16TopVStart = HAL_Read2Byte(SUB_REG(VOP_IMG_VSTR0))&0x1fff;
2192 #endif
2193 break;
2194 default:
2195 break;
2196 }
2197 return u16TopVStart;
2198 }
2199
HAL_MVOP_GetBottomVStart(MVOP_DevID eID)2200 MS_U16 HAL_MVOP_GetBottomVStart(MVOP_DevID eID)
2201 {
2202 MS_U16 u16BotVStart = 0;
2203 switch(eID)
2204 {
2205 case E_MVOP_DEV_0:
2206 u16BotVStart = HAL_Read2Byte(VOP_IMG_VSTR1)&0x1fff;
2207 break;
2208 case E_MVOP_DEV_1:
2209 #if MVOP_SUPPORT_SUB
2210 u16BotVStart = HAL_Read2Byte(SUB_REG(VOP_IMG_VSTR1))&0x1fff;
2211 #endif
2212 break;
2213 default:
2214 break;
2215 }
2216 return u16BotVStart;
2217 }
2218
HAL_MVOP_GetVCount(MVOP_DevID eID)2219 MS_U16 HAL_MVOP_GetVCount(MVOP_DevID eID)
2220 {
2221 MS_U16 u16VCount = 0;
2222 switch(eID)
2223 {
2224 case E_MVOP_DEV_0:
2225 u16VCount = HAL_Read2Byte(VOP_DEBUG_2A)&0x1fff;
2226 break;
2227 case E_MVOP_DEV_1:
2228 #if MVOP_SUPPORT_SUB
2229 u16VCount = HAL_Read2Byte(SUB_REG(VOP_DEBUG_2A))&0x1fff;
2230 #endif
2231 break;
2232 default:
2233 break;
2234 }
2235 return u16VCount;
2236 }
2237
HAL_MVOP_SetVC1RangeMap(MVOP_DevID eID,MVOP_VC1RangeMapInfo * stVC1RangeMapInfo)2238 MS_BOOL HAL_MVOP_SetVC1RangeMap(MVOP_DevID eID, MVOP_VC1RangeMapInfo *stVC1RangeMapInfo)
2239 {
2240 MS_U32 u8Luma = 0;
2241 MS_U32 u8Chroma = 0;
2242
2243 if (stVC1RangeMapInfo == NULL)
2244 {
2245 MVOP_DBG(MVOP_PRINTF("%s stBaseAddInfo is NULL pointer\n", __FUNCTION__);)
2246 return FALSE;
2247 }
2248
2249 // Luma value
2250 u8Luma = stVC1RangeMapInfo->u8LumaValue;
2251 // Chroma value
2252 u8Chroma = stVC1RangeMapInfo->u8ChromaValue;
2253
2254 switch(eID)
2255 {
2256 case E_MVOP_DEV_0:
2257 //set VC1 Luma value
2258 if(stVC1RangeMapInfo->bIsEnableLuma)
2259 {
2260 HAL_WriteRegBit(VOP_RAMAP_LUMA, 1, BIT7);
2261 HAL_WriteByteMask(VOP_RAMAP_LUMA, u8Luma, VOP_RAMAP_LUMA_VAL);
2262 }
2263 else //disable
2264 {
2265 HAL_WriteRegBit(VOP_RAMAP_LUMA, 0, BIT7);
2266 }
2267
2268 //set VC1 Chroma value
2269 if(stVC1RangeMapInfo->bIsEnableChroma)
2270 {
2271 HAL_WriteRegBit(VOP_RAMAP_CHROMA, 1, BIT7);
2272 HAL_WriteByteMask(VOP_RAMAP_CHROMA, u8Chroma, VOP_RAMAP_CHROMA_VAL);
2273 }
2274 else
2275 {
2276 HAL_WriteRegBit(VOP_RAMAP_CHROMA, 0, BIT7);
2277 }
2278 break;
2279 case E_MVOP_DEV_1:
2280 #if MVOP_SUPPORT_SUB
2281 //set VC1 Luma value
2282 if(stVC1RangeMapInfo->bIsEnableLuma)
2283 {
2284 HAL_WriteRegBit(SUB_REG(VOP_RAMAP_LUMA), 1, BIT7);
2285 HAL_WriteByteMask(SUB_REG(VOP_RAMAP_LUMA), u8Luma, VOP_RAMAP_LUMA_VAL);
2286 }
2287 else //disable
2288 {
2289 HAL_WriteRegBit(SUB_REG(VOP_RAMAP_LUMA), 0, BIT7);
2290 }
2291
2292 //set VC1 Chroma value
2293 if(stVC1RangeMapInfo->bIsEnableChroma)
2294 {
2295 HAL_WriteRegBit(SUB_REG(VOP_RAMAP_CHROMA), 1, BIT7);
2296 HAL_WriteByteMask(SUB_REG(VOP_RAMAP_CHROMA), u8Chroma, VOP_RAMAP_CHROMA_VAL);
2297 }
2298 else
2299 {
2300 HAL_WriteRegBit(SUB_REG(VOP_RAMAP_CHROMA), 0, BIT7);
2301 }
2302 #endif
2303 break;
2304 default:
2305 break;
2306 }
2307 return TRUE;
2308 }
2309
2310 MS_U16 g_u16SetStartX = 0;
2311 MS_U16 g_u16SetStartY = 0;
2312 MS_BOOL g_bIsY4Align = 0;
2313
HAL_MVOP_SetStartX(MVOP_DevID eID,MS_U16 u16XPos)2314 void HAL_MVOP_SetStartX(MVOP_DevID eID, MS_U16 u16XPos)
2315 {
2316 switch(eID)
2317 {
2318 case E_MVOP_DEV_0:
2319 u16XPos = ALIGN_UPTO_2(u16XPos);
2320 HAL_WriteByte(VOP_REG_CROP_HSTART, u16XPos & 0xff);
2321 HAL_WriteByte((VOP_REG_CROP_HSTART + 1),((u16XPos) >> (8)) & (0x1f));
2322 if(0 == u16XPos)
2323 {
2324 g_pHalMVOPCtx->u16CropXStart = 0;
2325 }
2326 else
2327 {
2328 g_pHalMVOPCtx->u16CropXStart += u16XPos;
2329 }
2330 // Write trigger
2331 HAL_MVOP_LoadReg();
2332 break;
2333 case E_MVOP_DEV_1:
2334 #if MVOP_SUPPORT_SUB
2335 u16XPos = ALIGN_UPTO_2(u16XPos);
2336 HAL_WriteByte(SUB_REG(VOP_REG_CROP_HSTART), u16XPos & 0xff);
2337 HAL_WriteByte(SUB_REG((VOP_REG_CROP_HSTART + 1)),((u16XPos) >> (8)) & (0x1f));
2338 if(0 == u16XPos)
2339 {
2340 g_pHalMVOPCtx->u16SubCropXStart = 0;
2341 }
2342 else
2343 {
2344 g_pHalMVOPCtx->u16SubCropXStart += u16XPos;
2345 }
2346 // Write trigger
2347 HAL_MVOP_SubLoadReg();
2348 #endif
2349 break;
2350 default:
2351 break;
2352 }
2353 }
2354
2355
HAL_MVOP_SetStartY(MVOP_DevID eID,MS_U16 u16YPos,MS_BOOL bIsInterlace)2356 void HAL_MVOP_SetStartY(MVOP_DevID eID, MS_U16 u16YPos, MS_BOOL bIsInterlace)
2357 {
2358 switch(eID)
2359 {
2360 case E_MVOP_DEV_0:
2361 HAL_WriteByteMask(VOP_REG_CROP_VSTART, u16YPos & 0xff, 0xff);
2362 HAL_WriteByteMask((VOP_REG_CROP_VSTART + 1), ((u16YPos) >> (8)) & (0x1f), 0x1f);
2363 if(0 == u16YPos)
2364 {
2365 g_pHalMVOPCtx->u16CropYStart = 0;
2366 }
2367 else
2368 {
2369 g_pHalMVOPCtx->u16CropYStart += u16YPos;
2370 }
2371 // Write trigger
2372 HAL_MVOP_LoadReg();
2373 break;
2374 case E_MVOP_DEV_1:
2375 #if MVOP_SUPPORT_SUB
2376 HAL_WriteByteMask(SUB_REG(VOP_REG_CROP_VSTART), u16YPos & 0xff, 0xff);
2377 HAL_WriteByteMask(SUB_REG((VOP_REG_CROP_VSTART + 1)), ((u16YPos) >> (8)) & (0x1f), 0x1f);
2378 if(0 == u16YPos)
2379 {
2380 g_pHalMVOPCtx->u16SubCropYStart = 0;
2381 }
2382 else
2383 {
2384 g_pHalMVOPCtx->u16SubCropYStart += u16YPos;
2385 }
2386 // Write trigger
2387 HAL_MVOP_SubLoadReg();
2388 #endif
2389 break;
2390 default:
2391 break;
2392 }
2393 }
2394
2395
HAL_MVOP_SetPicWidthMinus(MVOP_DevID eID,MS_U16 u16XSizes,MS_U16 u16Width)2396 void HAL_MVOP_SetPicWidthMinus(MVOP_DevID eID, MS_U16 u16XSizes, MS_U16 u16Width)
2397 {
2398 switch(eID)
2399 {
2400 case E_MVOP_DEV_0:
2401 u16XSizes = ALIGN_UPTO_2(u16XSizes);
2402 HAL_WriteByte(VOP_REG_CROP_HSIZE, u16XSizes & 0xff);
2403 HAL_WriteByte((VOP_REG_CROP_HSIZE + 1), ((u16XSizes) >> (8)) & (0x1f));
2404
2405 if(0 == u16XSizes)
2406 {
2407 g_pHalMVOPCtx->u16CropXSize = 0;
2408 }
2409 else
2410 {
2411 g_pHalMVOPCtx->u16CropXSize = u16XSizes;
2412 }
2413 // Write trigger
2414 HAL_MVOP_LoadReg();
2415 break;
2416 case E_MVOP_DEV_1:
2417 #if MVOP_SUPPORT_SUB
2418 u16XSizes = ALIGN_UPTO_2(u16XSizes);
2419 HAL_WriteByte(SUB_REG(VOP_REG_CROP_HSIZE), u16XSizes & 0xff);
2420 HAL_WriteByte(SUB_REG((VOP_REG_CROP_HSIZE + 1)), ((u16XSizes) >> (8)) & (0x1f));
2421 if(0 == u16XSizes)
2422 {
2423 g_pHalMVOPCtx->u16SubCropXSize = 0;
2424 }
2425 else
2426 {
2427 g_pHalMVOPCtx->u16SubCropXSize = u16XSizes;
2428 }
2429 // Write trigger
2430 HAL_MVOP_SubLoadReg();
2431 #endif
2432 break;
2433 default:
2434 break;
2435 }
2436 }
2437
2438
HAL_MVOP_SetPicHeightMinus(MVOP_DevID eID,MS_U16 u16YSizes,MS_U16 u16Height)2439 void HAL_MVOP_SetPicHeightMinus(MVOP_DevID eID, MS_U16 u16YSizes, MS_U16 u16Height)
2440 {
2441 switch(eID)
2442 {
2443 case E_MVOP_DEV_0:
2444 if(TRUE == g_pHalMVOPCtx->bMirrorModeVer)
2445 {
2446 MS_U16 u16YstMir = 0;
2447 if((g_pHalMVOPCtx->u16CropYStart + u16YSizes) < u16Height)
2448 {
2449 u16YstMir = u16Height - g_pHalMVOPCtx->u16CropYStart - u16YSizes;
2450 HAL_MVOP_SetStartX(E_MVOP_DEV_0, u16YstMir);
2451 }
2452 else
2453 {
2454 MVOP_PRINTF("[Warning] crop y size or start out of boundary.");
2455 return;
2456 }
2457 }
2458 HAL_WriteByte(VOP_REG_CROP_VSIZE, (u16YSizes) & 0xff);
2459 HAL_WriteByte((VOP_REG_CROP_VSIZE + 1), ((u16YSizes) >> (8)) & (0x1f));
2460 if(0 == u16YSizes)
2461 {
2462 g_pHalMVOPCtx->u16CropYSize = 0;
2463 }
2464 else
2465 {
2466 g_pHalMVOPCtx->u16CropYSize += u16YSizes;
2467 }
2468 // Write trigger
2469 HAL_MVOP_LoadReg();
2470 break;
2471 case E_MVOP_DEV_1:
2472 #if MVOP_SUPPORT_SUB
2473 if(TRUE == g_pHalMVOPCtx->bSubMirrorModeVer)
2474 {
2475 MS_U16 u16YstMir = 0;
2476 if((g_pHalMVOPCtx->u16SubCropYStart + u16YSizes) < u16Height)
2477 {
2478 u16YstMir = u16Height - g_pHalMVOPCtx->u16SubCropYStart - u16YSizes;
2479 HAL_MVOP_SetStartX(E_MVOP_DEV_1, u16YstMir);
2480 }
2481 else
2482 {
2483 MVOP_PRINTF("[Warning] crop y size or start out of boundary.");
2484 return;
2485 }
2486 }
2487 HAL_WriteByte(SUB_REG(VOP_REG_CROP_VSIZE), (u16YSizes) & 0xff);
2488 HAL_WriteByte(SUB_REG((VOP_REG_CROP_VSIZE + 1)), ((u16YSizes) >> (8)) & (0x1f));
2489 if(0 == u16YSizes)
2490 {
2491 g_pHalMVOPCtx->u16SubCropYSize = 0;
2492 }
2493 else
2494 {
2495 g_pHalMVOPCtx->u16SubCropYSize += u16YSizes;
2496 }
2497 // Write trigger
2498 HAL_MVOP_SubLoadReg();
2499
2500 #endif
2501 break;
2502 default:
2503 break;
2504 }
2505 }
2506
2507
2508
2509 /******************************************************************************/
2510 /// Set MVOP Saving BW Mode
2511 /// @ Napoli this command should be set after MDrv_MVOP_SetOutputCfg
2512 /******************************************************************************/
HAL_MVOP_Set420BWSaveMode(MS_BOOL bEnable)2513 MS_BOOL HAL_MVOP_Set420BWSaveMode(MS_BOOL bEnable)
2514 {
2515 MS_BOOL bValue = FALSE;
2516
2517 //hw limtation: 3DLA/3DSBS/422/p mode in, i mode out/i mode in, p mode out(only need to check in MCU mode)
2518 bValue = (g_pHalMVOPCtx->b3DLRAltSBSOutput || g_pHalMVOPCtx->b3DLRAltOutput /*|| g_pHalMVOPCtx->b3DLRMode */|| g_pHalMVOPCtx->bIs422 );
2519
2520 if(bValue)
2521 {
2522 MVOP_DBG(MVOP_PRINTF("%s Hit the limitation of saving bw, disable BW Saving mode\n", __FUNCTION__);)
2523 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_420_BW_SAVE);
2524 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
2525 HAL_MVOP_LoadReg();
2526 return FALSE;
2527 }
2528 else
2529 {
2530 HAL_WriteRegBit(VOP_REG_DUMMY, bEnable, VOP_420_BW_SAVE);
2531 if( g_pHalMVOPCtx->b3DLRMode == FALSE)
2532 HAL_WriteRegBit(VOP_REG_BW_SAVE, bEnable, VOP_420_BW_SAVE_EX);
2533 else
2534 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
2535 HAL_MVOP_LoadReg();
2536 return TRUE;
2537 }
2538 }
2539
HAL_MVOP_SetEVDYUVBaseAdd(MVOP_EVDBaseAddInput * stEVDBaseAddInfo)2540 MS_BOOL HAL_MVOP_SetEVDYUVBaseAdd(MVOP_EVDBaseAddInput *stEVDBaseAddInfo)
2541 {
2542 //----------------------------------------------------
2543 // Set MSB YUV Address
2544 //----------------------------------------------------
2545
2546 MS_PHY u64tmp = 0;
2547
2548 if (g_pHalMVOPCtx == NULL)
2549 {
2550 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2551 return FALSE;
2552 }
2553 // Y offset
2554 u64tmp = stEVDBaseAddInfo->u32MSBYOffset >> 3;
2555 if ( !stEVDBaseAddInfo->bProgressive)
2556 { //Refine Y offset for interlace repeat bottom field
2557 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
2558 {
2559 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2560 u64tmp += 2;
2561 }
2562 else
2563 {
2564 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2565 }
2566 }
2567 HAL_WriteByte(VOP_JPG_YSTR0_L, u64tmp & 0xff);
2568 HAL_WriteByte((VOP_JPG_YSTR0_L+1), (u64tmp >> 8) & 0xff);
2569 HAL_WriteByte((VOP_JPG_YSTR0_H), (u64tmp >> 16) & 0xff);
2570 HAL_WriteByte((VOP_JPG_YSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2571
2572 if (!stEVDBaseAddInfo->bProgressive )
2573 { //Y offset of bottom field if interlace
2574 HAL_WriteByte(VOP_JPG_YSTR1_L, u64tmp & 0xff);
2575 HAL_WriteByte((VOP_JPG_YSTR1_L+1), (u64tmp >> 8) & 0xff);
2576 HAL_WriteByte((VOP_JPG_YSTR1_H), (u64tmp >> 16) & 0xff);
2577 HAL_WriteByte((VOP_JPG_YSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2578 }
2579
2580 if (stEVDBaseAddInfo->b422Pack)
2581 {
2582 stEVDBaseAddInfo->u32MSBUVOffset = stEVDBaseAddInfo->u32MSBYOffset + 16; //add 16 for 128bit; add 8 for 64bit
2583 }
2584 // UV offset
2585 u64tmp = stEVDBaseAddInfo->u32MSBUVOffset >> 3;
2586 if( !stEVDBaseAddInfo->bProgressive )
2587 { //Refine UV offset for interlace repeat bottom field
2588 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
2589 {
2590 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2591 u64tmp += 2;
2592 }
2593 else
2594 {
2595 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2596 }
2597 }
2598 HAL_WriteByte(VOP_JPG_UVSTR0_L, u64tmp & 0xff);
2599 HAL_WriteByte((VOP_JPG_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
2600 HAL_WriteByte((VOP_JPG_UVSTR0_H), (u64tmp >> 16) & 0xff);
2601 HAL_WriteByte((VOP_JPG_UVSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2602
2603 if( !stEVDBaseAddInfo->bProgressive )
2604 { //UV offset of bottom field if interlace
2605 HAL_WriteByte(VOP_JPG_UVSTR1_L, u64tmp & 0xff);
2606 HAL_WriteByte((VOP_JPG_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
2607 HAL_WriteByte((VOP_JPG_UVSTR1_H), (u64tmp >> 16) & 0xff);
2608 HAL_WriteByte((VOP_JPG_UVSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2609 }
2610
2611 //----------------------------------------------------
2612 // Set MSB YUV Address
2613 //----------------------------------------------------
2614 if(stEVDBaseAddInfo->bEnLSB)
2615 {
2616 //Enable LSB
2617 HAL_WriteRegBit(VOP_EVD_10B_EN, 1, VOP_EVD_10B_Y_EN);
2618 HAL_WriteRegBit(VOP_EVD_10B_EN, 1, VOP_EVD_10B_UV_EN);
2619 HAL_WriteRegBit(VOP_REG_MASK, 0, VOP_LSB_REQ_MASK);
2620
2621 // Y offset
2622 u64tmp = stEVDBaseAddInfo->u32LSBYOffset >> 3;
2623 if ( !stEVDBaseAddInfo->bProgressive)
2624 { //Refine Y offset for interlace repeat bottom field
2625 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
2626 {
2627 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2628 u64tmp += 2;
2629 }
2630 else
2631 {
2632 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2633 }
2634 }
2635 HAL_WriteByte(VOP_LSB_YSTR0_L, u64tmp & 0xff);
2636 HAL_WriteByte((VOP_LSB_YSTR0_L+1), (u64tmp >> 8) & 0xff);
2637 HAL_WriteByte((VOP_LSB_YSTR0_L), (u64tmp >> 16) & 0xff);
2638 HAL_WriteByte((VOP_LSB_YSTR0_L+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2639
2640 if (!stEVDBaseAddInfo->bProgressive )
2641 { //Y offset of bottom field if interlace
2642 HAL_WriteByte(VOP_LSB_YSTR1_L, u64tmp & 0xff);
2643 HAL_WriteByte((VOP_LSB_YSTR1_L+1), (u64tmp >> 8) & 0xff);
2644 HAL_WriteByte((VOP_LSB_YSTR1_H), (u64tmp >> 16) & 0xff);
2645 HAL_WriteByte((VOP_LSB_YSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2646 }
2647
2648 if (stEVDBaseAddInfo->b422Pack)
2649 {
2650 stEVDBaseAddInfo->u32LSBUVOffset = stEVDBaseAddInfo->u32LSBYOffset + 16; //add 16 for 128bit; add 8 for 64bit
2651 }
2652 // UV offset
2653 u64tmp = stEVDBaseAddInfo->u32LSBUVOffset >> 3;
2654 if( !stEVDBaseAddInfo->bProgressive )
2655 { //Refine UV offset for interlace repeat bottom field
2656 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
2657 {
2658 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2659 u64tmp += 2;
2660 }
2661 else
2662 {
2663 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2664 }
2665 }
2666 HAL_WriteByte(VOP_LSB_UVSTR0_L, u64tmp & 0xff);
2667 HAL_WriteByte((VOP_LSB_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
2668 HAL_WriteByte((VOP_LSB_UVSTR0_H), (u64tmp >> 16) & 0xff);
2669 HAL_WriteByte((VOP_LSB_UVSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2670
2671 if( !stEVDBaseAddInfo->bProgressive )
2672 { //UV offset of bottom field if interlace
2673 HAL_WriteByte(VOP_LSB_UVSTR1_L, u64tmp & 0xff);
2674 HAL_WriteByte((VOP_LSB_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
2675 HAL_WriteByte((VOP_LSB_UVSTR1_H), (u64tmp >> 16) & 0xff);
2676 HAL_WriteByte((VOP_LSB_UVSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2677 }
2678 }
2679
2680 return TRUE;
2681 }
2682
2683 /******************************************************************************/
2684 /// Set MVOP repeat previous frame IF VDEC can not finish vsync.
2685 /// this command should be set disable as call VDEC Exit.
2686 /******************************************************************************/
HAL_MVOP_SetRptPreVsyncFrame(MVOP_DevID eID,MS_BOOL bEnable)2687 void HAL_MVOP_SetRptPreVsyncFrame(MVOP_DevID eID, MS_BOOL bEnable)
2688 {
2689 switch(eID)
2690 {
2691 case E_MVOP_DEV_0:
2692 {
2693 g_pHalMVOPCtx->bRptPreVsync = bEnable;
2694 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3);
2695 break;
2696 }
2697 case E_MVOP_DEV_1:
2698 {
2699 #if MVOP_SUPPORT_SUB
2700 g_pHalMVOPCtx->bSubRptPreVsync = bEnable;
2701 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3);
2702 #endif
2703 break;
2704 }
2705 default:
2706 MVOP_PRINTF("[Warning] MVOP_DevID not support!\n");
2707 break;
2708 }
2709 }
2710
HAL_MVOP_PowerStateSuspend(void)2711 void HAL_MVOP_PowerStateSuspend(void)
2712 {
2713 g_pHalMVOPCtx->bIsInit = 0;
2714 #if MVOP_SUPPORT_SUB
2715 g_pHalMVOPCtx->bSubIsInit = 0;
2716 #endif
2717 }
2718
HAL_MVOP_GetHandShakeMode(MVOP_DevID eID)2719 MVOP_HSMode HAL_MVOP_GetHandShakeMode(MVOP_DevID eID)
2720 {
2721 MVOP_HSMode eRet = E_MVOP_HS_NOT_SUPPORT;
2722 switch(eID)
2723 {
2724 case E_MVOP_DEV_0:
2725 eRet = E_MVOP_HS_NOT_SUPPORT;
2726 break;
2727 case E_MVOP_DEV_1:
2728 #if MVOP_SUPPORT_SUB
2729 eRet = E_MVOP_HS_NOT_SUPPORT;
2730 #endif
2731 break;
2732 default:
2733 eRet = E_MVOP_HS_INVALID_PARAM;
2734 break;
2735 }
2736 return eRet;
2737 }
2738
HAL_MVOP_CheckSTCCW(void)2739 MS_BOOL HAL_MVOP_CheckSTCCW(void)
2740 {
2741 MS_U16 u16STC_CW_L = 0;
2742 MS_U16 u16STC_CW_H = 0;
2743 MS_BOOL u16STC_CW_SEL = 0;
2744 MS_BOOL u16TSP_CLK_EN = 0;
2745
2746 u16STC_CW_L = HAL_Read2Byte(REG_STC0_CW_L)&0xffff;
2747 u16STC_CW_H = HAL_Read2Byte(REG_STC0_CW_H)&0xffff;
2748
2749 u16STC_CW_SEL = (HAL_ReadRegBit(REG_STC_CW_SLE_L, BIT1) == BIT1);
2750 u16TSP_CLK_EN = !(HAL_ReadRegBit(REG_TSP_CLK, BIT0) == BIT0);
2751
2752 if((((u16STC_CW_L || u16STC_CW_H) == 0) && (u16STC_CW_SEL == 0)) || ((u16STC_CW_SEL == 1) && (u16TSP_CLK_EN == 0)))
2753 return FALSE;
2754 else
2755 return TRUE;
2756
2757 }
2758
2759 #define MIU1_REG_BASE 0x0600
HAL_MVOP_GetIsMiuIPControl(HALMVOPMIUCLIENTINFO stInfo)2760 MS_BOOL HAL_MVOP_GetIsMiuIPControl(HALMVOPMIUCLIENTINFO stInfo)
2761 {
2762 MS_U32 u32RegMiu = 0;
2763 MS_U16 u16Mask = 0;
2764 MS_BOOL bRet = FALSE;
2765
2766 u32RegMiu = MIU1_REG_BASE + (0xF0+(stInfo.u8Gp * 2));
2767 if(stInfo.u8BitPos < 8)
2768 {
2769 u16Mask = 1<<stInfo.u8BitPos;
2770 }
2771 else
2772 {
2773 u16Mask = 1<<(stInfo.u8BitPos-8);
2774 u32RegMiu += 1;
2775 }
2776 MVOP_DBG(MVOP_PRINTF("[%s] u32RegMiu = 0x%lx, u16Mask = 0x%x\n",__FUNCTION__, u32RegMiu,u16Mask);)
2777 if(HAL_ReadRegBit(u32RegMiu, u16Mask))
2778 {
2779 bRet = TRUE;
2780 }
2781
2782 return bRet;
2783 }
2784
HAL_MVOP_SelMIU(MVOP_DevID eDevID,HALMVOPMIUSEL eMiuMSB0,HALMVOPMIUSEL eMiuMSB1,HALMVOPMIUSEL eMiuLSB0,HALMVOPMIUSEL eMiuLSB1)2785 void HAL_MVOP_SelMIU(MVOP_DevID eDevID, HALMVOPMIUSEL eMiuMSB0, HALMVOPMIUSEL eMiuMSB1, HALMVOPMIUSEL eMiuLSB0, HALMVOPMIUSEL eMiuLSB1)
2786 {
2787 MS_U8 u8MSBVlue = 0;
2788 MS_U8 u8LSBVlue = 0;
2789
2790 if(eMiuMSB0 != eMiuMSB1)
2791 HAL_WriteRegBit(VOP_MIU_SEL, TRUE, BIT0);
2792 else
2793 HAL_WriteRegBit(VOP_MIU_SEL, FALSE, BIT0);
2794
2795 if(eMiuLSB0 != eMiuLSB1)
2796 HAL_WriteRegBit(VOP_MIU_SEL, TRUE, BIT1);
2797 else
2798 HAL_WriteRegBit(VOP_MIU_SEL, FALSE, BIT1);
2799
2800 u8MSBVlue |= (eMiuMSB0 << 4);
2801 u8MSBVlue |= (eMiuMSB1 << 6);
2802
2803 u8LSBVlue |= (eMiuLSB0 << 4);
2804 u8LSBVlue |= (eMiuLSB1 << 6);
2805
2806 switch(eDevID)
2807 {
2808 case E_MVOP_DEV_0:
2809 {
2810 // MSB
2811 HAL_WriteByteMask(VOP_MIU_SEL, u8MSBVlue, VOP_MSB_BUF0_MIU_SEL | VOP_MSB_BUF1_MIU_SEL);
2812 // LSB
2813 HAL_WriteByteMask(VOP_MIU_SEL_LSB, u8LSBVlue, VOP_LSB_BUF0_MIU_SEL | VOP_LSB_BUF1_MIU_SEL);
2814 break;
2815 }
2816 #if MVOP_SUPPORT_SUB
2817 case E_MVOP_DEV_1:
2818 {
2819 // MSB
2820 HAL_WriteByteMask(SUB_REG(VOP_MIU_SEL), u8MSBVlue, VOP_MSB_BUF0_MIU_SEL | VOP_MSB_BUF1_MIU_SEL);
2821 // LSB
2822 HAL_WriteByteMask(SUB_REG(VOP_MIU_SEL_LSB), u8LSBVlue, VOP_LSB_BUF0_MIU_SEL | VOP_LSB_BUF1_MIU_SEL);
2823 break;
2824 }
2825 #endif
2826 default:
2827 break;
2828 }
2829 }
2830
HAL_MVOP_GetIsOnlyMiuIPControl(void)2831 MS_BOOL HAL_MVOP_GetIsOnlyMiuIPControl(void)
2832 {
2833 return TRUE;
2834 }
2835
HAL_MVOP_GetMaxFramerate(MVOP_DevID eDevID,MVOP_GetMaxFps * stStreamInfo)2836 void HAL_MVOP_GetMaxFramerate(MVOP_DevID eDevID, MVOP_GetMaxFps* stStreamInfo)
2837 {
2838 MS_U64 u64MaxClk = 0;
2839 MS_U16 u16HsizeTiming = 0;
2840 MS_U16 u16VsizeTiming = 0;
2841
2842 if(NULL == stStreamInfo)
2843 {
2844 MVOP_PRINTF("[%s] Input parameter is NULL!\n",__FUNCTION__);
2845 return;
2846 }
2847
2848 switch(eDevID)
2849 {
2850 case E_MVOP_DEV_0:
2851 #if MVOP_SUPPORT_SUB
2852 case E_MVOP_DEV_1:
2853 #endif
2854 {
2855 if(_HAL_MVOP_IsSupport4k2k2P())
2856 {
2857 u16HsizeTiming = stStreamInfo->u16HSize >> 1;
2858 }
2859 else
2860 {
2861 u16HsizeTiming = stStreamInfo->u16HSize;
2862 u16HsizeTiming = ALIGN_UPTO_2(u16HsizeTiming);
2863 }
2864 if(stStreamInfo->b3DSBS)
2865 {
2866 u16HsizeTiming *= 2;
2867 }
2868 if(stStreamInfo->u16HSize > 720)
2869 {
2870 u16HsizeTiming += MVOP_HBlank_HD;
2871 }
2872 else
2873 {
2874 u16HsizeTiming += MVOP_HBlank_SD;
2875 }
2876
2877 u64MaxClk = HAL_MVOP_GetMaximumClk();
2878 if(stStreamInfo->b3DTB)
2879 {
2880 u16VsizeTiming = stStreamInfo->u16VSize*2 + MVOP_VBlank;
2881 }
2882 else
2883 {
2884 u16VsizeTiming = stStreamInfo->u16VSize + MVOP_VBlank;
2885 }
2886 do_div(u64MaxClk, u16HsizeTiming);
2887 do_div(u64MaxClk, u16VsizeTiming);
2888 stStreamInfo->u32Framerate = (MS_U32)u64MaxClk * 1000;
2889 }
2890 break;
2891 default:
2892 break;
2893 }
2894
2895 }
2896
HAL_MVOP_ResetReg(MVOP_DevID eDevID,MS_U16 u16ECOVersion)2897 void HAL_MVOP_ResetReg(MVOP_DevID eDevID, MS_U16 u16ECOVersion)
2898 {
2899
2900 switch(eDevID)
2901 {
2902 case E_MVOP_DEV_0:
2903 {
2904 #if ENABLE_3D_LR_MODE
2905 HAL_MVOP_Enable3DLR(DISABLE);
2906 #endif
2907 #if SUPPORT_3DLR_ALT_SBS
2908 HAL_MVOP_Set3DLRAltOutput(DISABLE);
2909 HAL_MVOP_Set3DLRAltSBSOutput(DISABLE);
2910 #endif
2911
2912 /*****************************************************/
2913 // Reset MVOP setting
2914 HAL_WriteByte(VOP_TST_IMG, 0x40); //reset test pattern or BG
2915 HAL_MVOP_Set3DLRAltOutput_VHalfScaling(DISABLE); //reset to default: disable 3D L/R alternative output.
2916 HAL_MVOP_Set3DLR2ndCfg(DISABLE); //reset to default: disable 3D L/R 2nd pitch.
2917 HAL_MVOP_SetRgbFormat(E_MVOP_RGB_NONE); //reset rgb format
2918 HAL_WriteRegBit(VOP_CTRL1, 0, VOP_MVD_VS_MD); //default use original vsync
2919 // Only for Monaco: Enable deciding bot by top address + 2
2920 HAL_WriteRegBit(VOP_MIRROR_CFG, 1, VOP_FIELD_FROM_ADDR);
2921 // Reset Mono mode
2922 HAL_MVOP_SetMonoMode(FALSE);
2923
2924 //set MVOP test pattern to black
2925 HAL_MVOP_SetBlackBG();
2926
2927 // clear extend strip len bit by default
2928 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
2929
2930 // set mvop to 128bit_i128 interface
2931 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
2932
2933 // Disable H264 or RM Input
2934 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 0, BIT2|BIT3);
2935 // Clear 422 Flag
2936 g_pHalMVOPCtx->bIs422 = 0;
2937 // Clear evd Flag for interlace mode setting
2938 g_pHalMVOPCtx->bIsH265 = 0;
2939 HAL_WriteRegBit(VOP_INT_TYPE, 0, VOP_EVD_INT_SEP);
2940 //8*32 tile format
2941 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
2942 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD);
2943 HAL_MVOP_SetFieldInverse(ENABLE, ENABLE);
2944 // EVD mode disable
2945 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, EVD_ENABLE);
2946 // EVD 10 bits disable
2947 //HAL_WriteByteMask(VOP_REG_MASK, BIT1, VOP_LSB_REQ_MASK);
2948 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_Y_EN);
2949 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_UV_EN);
2950 // Enable 420 BW Saving mode
2951 HAL_MVOP_Set420BWSaveMode(TRUE);
2952 // Disable New Vsync Mode
2953 g_pHalMVOPCtx->bNewVSyncMode = FALSE;
2954 // VP9 MODE disable
2955 //HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, VOP_R2_WISHBONE);
2956 HAL_WriteRegBit(VOP_MPG_JPG_SWITCH, 0, VOP_DRAM_RD_MODE);
2957 // Disable 2p mode
2958 HAL_MVOP_SetEnable4k2k2P(FALSE);
2959 // Setting MF burst len
2960 HAL_WriteByteMask(VOP_REG_MFDEC_0_L, 0x70, VOP_MF1_BURST|VOP_MF0_BURST|VOP_MFDEC_EN);
2961 // Only for monaco: Disable mfdec setting from wb
2962 HAL_WriteRegBit(VOP_REG_MFDEC_2_L, 0, VOP_MF_FROM_WB);
2963 // MIU select from WB
2964 HAL_WriteByteMask(VOP_INFO_FROM_CODEC_H, 0x30, VOP_INFO_FROM_CODEC_MIU_BUF0_SEL|VOP_INFO_FROM_CODEC_MIU_BUF1_SEL);
2965 HAL_WriteRegBit(VOP_UV_SHIFT, 0, VOP_GCLK_MIU_ON);// yc seperate can not enable(1: saving power)
2966 // All codec use WISHBONE(R2) interface in manhathan
2967 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, VOP_R2_WISHBONE);
2968 // MUJI default not support 10 bits display
2969 // Disable 10 bits from codec
2970 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_H, 0, VOP_INFO_FROM_CODEC_10BIT);
2971 HAL_MVOP_SetHandShakeMode(E_MVOP_DEV_0, DISABLE, 25);
2972 HAL_MVOP_SetStartX(E_MVOP_DEV_0, 0);
2973 HAL_MVOP_SetStartY(E_MVOP_DEV_0, 0, 0);
2974 HAL_MVOP_SetPicWidthMinus(E_MVOP_DEV_0, 0, 0);
2975 HAL_MVOP_SetPicHeightMinus(E_MVOP_DEV_0, 0, 0);
2976 //HAL_WriteRegBit(VOP_REG_MRQ, 1, VOP_MRQ_EN); //Manhathan only: merge mvop0/1 miu client
2977 //HAL_SetSCFEMIUIPSel(NULL);
2978 g_pHalMVOPCtx->eRepeatField = E_MVOP_RPTFLD_NONE;
2979 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_32x32_WB);
2980 g_pHalMVOPCtx->eInterlaceType = E_MVOP_PRO;
2981 //Disable DV vision
2982 g_pHalMVOPCtx->bIs265DV = 0;
2983 HAL_WriteRegBit(VOP_REG_4K2K_2P, 0, VOP_TRIG_REFER_VB_END);
2984 #if SUPPORT_FILED_DB // t/b signal 30 lines forwarding
2985 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_DC2MVD_FLD_SEL);
2986 HAL_WriteRegBit(VOP_REG_BW_THD_H, 0, REG_MVD_FLD_SEL);
2987
2988 HAL_WriteByte((VOP_TF_STR_MVD ), 0);
2989 HAL_WriteByte((VOP_TF_STR_MVD + 1), 0);
2990 HAL_WriteByte((VOP_BF_STR_MVD ), 0);
2991 HAL_WriteByte((VOP_BF_STR_MVD + 1), 0);
2992 #endif
2993 HAL_WriteRegBit(VOP_REG_DUMMY_5D_L, 0, XC_RESET_HCOUNT); //disable hw patch for kano gop, only enable at xc gen timing+de mode
2994 //set for miu 16+16 in hsk mode
2995 HAL_WriteByte(VOP_LSB_DMA0, 0x10);
2996 HAL_WriteByte(VOP_LSB_DMA1, 0x07);
2997 HAL_MVOP_LoadReg();
2998 /*****************************************************/
2999 break;
3000 }
3001 #if MVOP_SUPPORT_SUB
3002 case E_MVOP_DEV_1:
3003 {
3004 #if ENABLE_3D_LR_MODE
3005 HAL_MVOP_SubEnable3DLR(DISABLE);
3006 #endif
3007 #if SUPPORT_3DLR_ALT_SBS
3008 HAL_MVOP_SubSet3DLRAltOutput(DISABLE);
3009 HAL_MVOP_SubSet3DLRAltSBSOutput(DISABLE);
3010 #endif
3011 HAL_MVOP_SubEnableMVDInterface(FALSE);
3012
3013 /*****************************************************/
3014 // Reset MVOP setting
3015 //Reset share mem
3016 _HAL_MVOP_SubInitVarCtx();
3017 HAL_WriteByte(SUB_REG(VOP_TST_IMG), 0x40);
3018 HAL_MVOP_SubSetRgbFormat(E_MVOP_RGB_NONE);
3019 HAL_WriteRegBit(SUB_REG(VOP_CTRL1), 0, VOP_MVD_VS_MD); //default use original vsync
3020 // Only for Monaco: Enable deciding bot by top address + 2
3021 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 1, VOP_FIELD_FROM_ADDR);
3022 // Reset Mono mode
3023 HAL_MVOP_SubSetMonoMode(FALSE);
3024
3025 //set MVOP test pattern to black
3026 HAL_MVOP_SubSetBlackBG();
3027
3028 // clear extend strip len bit by default
3029 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
3030
3031 // set mvop to 128bit_i128 interface
3032 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
3033
3034 // Disable H264 or RM Input
3035 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH1), 0, BIT2|BIT3);
3036 // Clear 422 Flag
3037 g_pHalMVOPCtx->bSubIs422 = 0;
3038 // Clear evd Flag for interlace mode setting
3039 g_pHalMVOPCtx->bSubIsH265 = 0;
3040 HAL_WriteRegBit(SUB_REG(VOP_INT_TYPE), 0, VOP_EVD_INT_SEP);
3041 //8*32 tile format
3042 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
3043 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD);
3044 HAL_MVOP_SubSetFieldInverse(ENABLE, ENABLE);
3045 // EVD mode disable
3046 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, EVD_ENABLE);
3047 // EVD 10 bits
3048 //HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), BIT1, VOP_LSB_REQ_MASK);
3049 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_Y_EN);
3050 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_UV_EN);
3051 // Enable 420 BW Saving mode
3052 HAL_MVOP_SubSet420BWSaveMode(TRUE);
3053 // VP9 MODE disable
3054 //HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, VOP_R2_WISHBONE);
3055 HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 0, VOP_DRAM_RD_MODE);
3056 // Disable 2p mode
3057 HAL_MVOP_SubSetEnable4k2k2P(FALSE);
3058 // Disable New Vsync Mode
3059 g_pHalMVOPCtx->bSubNewVSyncMode = FALSE;
3060 // Sub mvop ds idx from DIU
3061 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), 1, VOP_INFO_FROM_CODEC_DS_IDX);
3062 // Setting MF burst len
3063 HAL_WriteByteMask(SUB_REG(VOP_REG_MFDEC_0_L), 0x70, VOP_MF1_BURST|VOP_MF0_BURST|VOP_MFDEC_EN);
3064 // Only for monaco: Disable mfdec setting from wb
3065 HAL_WriteRegBit(SUB_REG(VOP_REG_MFDEC_2_L), 0, VOP_MF_FROM_WB);
3066 // MIU select from WB
3067 HAL_WriteByteMask(SUB_REG(VOP_INFO_FROM_CODEC_H), 0x30, VOP_INFO_FROM_CODEC_MIU_BUF0_SEL|VOP_INFO_FROM_CODEC_MIU_BUF1_SEL);
3068 HAL_WriteRegBit(SUB_REG(VOP_UV_SHIFT), 0, VOP_GCLK_MIU_ON);// yc seperate can not enable(1: saving power)
3069 // All codec use WISHBONE(R2) interface in manhathan
3070 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, VOP_R2_WISHBONE);
3071 // MUJI default not support 10 bits display
3072 // Disable 10 bits from codec
3073 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), 0, VOP_INFO_FROM_CODEC_10BIT);
3074 HAL_MVOP_SetHandShakeMode(E_MVOP_DEV_1, DISABLE, 25);
3075 HAL_MVOP_SetStartX(E_MVOP_DEV_1, 0);
3076 HAL_MVOP_SetStartY(E_MVOP_DEV_1, 0, 0);
3077 HAL_MVOP_SetPicWidthMinus(E_MVOP_DEV_1, 0, 0);
3078 HAL_MVOP_SetPicHeightMinus(E_MVOP_DEV_1, 0, 0);
3079 //HAL_WriteRegBit(SUB_REG(VOP_REG_MRQ), 1, VOP_MRQ_EN); //Manhathan only: merge mvop0/1 miu client
3080 //HAL_SetSCFEMIUIPSel(NULL);
3081 g_pHalMVOPCtx->eSubRepeatField = E_MVOP_RPTFLD_NONE;
3082 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 0, VOP_32x32_WB);
3083 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_PRO;
3084 #if SUPPORT_FILED_DB // t/b signal 30 lines forwarding
3085 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 1, VOP_DC2MVD_FLD_SEL);
3086 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_THD_H), 0, REG_MVD_FLD_SEL);
3087
3088 HAL_WriteByte(SUB_REG(VOP_TF_STR_MVD ), 0);
3089 HAL_WriteByte(SUB_REG(VOP_TF_STR_MVD + 1), 0);
3090 HAL_WriteByte(SUB_REG(VOP_BF_STR_MVD ), 0);
3091 HAL_WriteByte(SUB_REG(VOP_BF_STR_MVD + 1), 0);
3092 #endif
3093
3094 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY_5D_L), 0, XC_RESET_HCOUNT); //disable hw patch for kano gop, only enable at xc gen timing+de mode
3095 //set for miu 16+16 in hsk mode
3096 HAL_WriteByte(SUB_REG(VOP_LSB_DMA0), 0x10);
3097 HAL_WriteByte(SUB_REG(VOP_LSB_DMA1), 0x07);
3098 HAL_MVOP_SubLoadReg();
3099 /*****************************************************/
3100 break;
3101 }
3102 #endif
3103 default:
3104 MVOP_PRINTF("[%s] Input Device ID is Error!\n",__FUNCTION__);
3105 break;
3106 }
3107 }
3108
3109 /******************************************************************************/
3110 /// Set MVOP Handshake Mode, XC should be synchronous with MVOP.
3111 /// this command should be before mvop enable.(before 1st frame)
3112 /******************************************************************************/
HAL_MVOP_SetHandShakeMode(MVOP_DevID eID,MS_BOOL bEnable,MS_U8 u8Framerate)3113 void HAL_MVOP_SetHandShakeMode(MVOP_DevID eID, MS_BOOL bEnable, MS_U8 u8Framerate)
3114 {
3115 #if 0 //remove patch
3116 MS_U8 u8FrmDur = 40;
3117 MS_BOOL bMCU = FALSE;
3118
3119 if(u8Framerate != 0)
3120 {
3121 u8FrmDur = 1000/u8Framerate; //time of one frame(ms).
3122 }
3123 #endif
3124 switch(eID)
3125 {
3126 case E_MVOP_DEV_0:
3127 {
3128 if(!((bEnable == FALSE) && (g_pHalMVOPCtx->bIsHS == FALSE)) && !(g_pHalMVOPCtx->bIs265DV)) //prevent switch VOP_CTRL0 (mvop enable), for MHEG5 verify
3129 {
3130
3131 HAL_WriteRegBit(VOP_CTRL0, 0, BIT0);
3132 g_pHalMVOPCtx->bIsHS = bEnable;
3133 HAL_WriteRegBit(VOP_REG_HS_OUTPUT, bEnable, VOP_HS_MODE);
3134 HAL_WriteRegBit(VOP_REG_HS_OUTPUT, bEnable, BIT2);//reg_vsync_from_sc
3135 HAL_WriteRegBit(VOP_REG_HS_OUTPUT, bEnable, BIT1);//reg_vsync_from_sc
3136 HAL_WriteRegBit(VOP_CTRL0, bEnable, BIT4);
3137
3138 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background
3139 if(!g_pHalMVOPCtx->bIs2p)
3140 HAL_MVOP_SetEnable4k2k2P(bEnable);
3141 HAL_WriteRegBit(VOP_CTRL0, 1, BIT0);
3142 g_pHalMVOPCtx->bIsXcTrig = TRUE;
3143 HAL_MVOP_LoadReg();
3144 }
3145 break;
3146 }
3147 case E_MVOP_DEV_1:
3148 {
3149 #if MVOP_SUPPORT_SUB
3150 if(!((bEnable == FALSE) && (g_pHalMVOPCtx->bSubIsHS == FALSE)) && !(g_pHalMVOPCtx->bIs265DV)) //prevent switch VOP_CTRL0 (mvop enable), for MHEG5 verify
3151 {
3152 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 0, BIT0);
3153 g_pHalMVOPCtx->bSubIsHS = bEnable;
3154 HAL_WriteRegBit(SUB_REG(VOP_REG_HS_OUTPUT), bEnable, VOP_HS_MODE);
3155 HAL_WriteRegBit(SUB_REG(VOP_REG_HS_OUTPUT), bEnable, BIT2);//reg_vsync_from_sc
3156 HAL_WriteRegBit(SUB_REG(VOP_REG_HS_OUTPUT), bEnable, BIT1);//reg_vsync_from_sc
3157 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), bEnable, BIT4);
3158
3159 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, VOP_HK_MASK); //bk background
3160 if(!g_pHalMVOPCtx->bSubIs2p)
3161 HAL_MVOP_SubSetEnable4k2k2P(bEnable);
3162 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 1, BIT0);
3163 g_pHalMVOPCtx->bSubIsXcTrig = TRUE;
3164 HAL_MVOP_SubLoadReg();
3165 }
3166 #endif
3167 break;
3168 }
3169 default:
3170 MVOP_PRINTF("[Warning] MVOP_DevID not support!\n");
3171 break;
3172 }
3173 }
3174
HAL_MVOP_SetCropforXC(MVOP_DevID eID,MVOP_XCGetCrop * stXCCrop,MS_U16 u16Width,MS_U16 u16Height)3175 void HAL_MVOP_SetCropforXC(MVOP_DevID eID, MVOP_XCGetCrop* stXCCrop, MS_U16 u16Width, MS_U16 u16Height)
3176 {
3177 MVOP_DBG(MVOP_PRINTF("%s [crop info] xst: 0x%x yst: 0x%x xsize: 0x%x ysize: 0x%x Width: 0x%x Height: 0x%x\n", __FUNCTION__,
3178 stXCCrop->u16XStart, stXCCrop->>u16YStart, stXCCrop->>u16XSize, stXCCrop->u16YSize, u16Width, u16Height);)
3179
3180 switch(eID)
3181 {
3182 case E_MVOP_DEV_0:
3183 {
3184 if(g_pHalMVOPCtx->u16CropXSize == 0)
3185 g_pHalMVOPCtx->u16CropXSize = u16Width;
3186
3187 if((stXCCrop->u16XStart + stXCCrop->u16XSize) > u16Width)
3188 {
3189 MVOP_PRINTF("[Warning] crop x size or start out of boundary.");
3190 return;
3191 }
3192
3193 if(g_pHalMVOPCtx->u16CropYSize == 0)
3194 g_pHalMVOPCtx->u16CropYSize = u16Height;
3195
3196 if((stXCCrop->u16YStart + stXCCrop->u16YSize) > u16Height)
3197 {
3198 MVOP_PRINTF("[Warning] crop y size or start out of boundary.");
3199 return;
3200 }
3201
3202 stXCCrop->u16XStart = ALIGN_UPTO_2(stXCCrop->u16XStart);
3203 stXCCrop->u16XSize = ALIGN_UPTO_2(stXCCrop->u16XSize);
3204 g_pHalMVOPCtx->u16CropXStart = stXCCrop->u16XStart;
3205 g_pHalMVOPCtx->u16CropXSize = stXCCrop->u16XSize;
3206
3207 #if 0 //sw patch, for monet/manhattan: maserati fix
3208 if((stXCCrop->u16YSize <= 512) && (stXCCrop->u16YStart == 0) && (g_pHalMVOPCtx->bMirrorModeVer == TRUE))
3209 {
3210 MVOP_PRINTF("[MVOP][Dbg] crop + mirror patch\n");
3211 stXCCrop->u16YStart = 1;
3212 stXCCrop->u16YStart = stXCCrop->u16YStart | 0x2000;
3213
3214 g_pHalMVOPCtx->u16CropYSize = stXCCrop->u16YSize;
3215 if(g_pHalMVOPCtx->bIsH265 == FALSE)
3216 {
3217 stXCCrop->u16YSize -= 1;
3218 }
3219 }
3220 else
3221 #endif
3222 g_pHalMVOPCtx->u16CropYStart = stXCCrop->u16YStart;
3223 //from maserati
3224 if(g_pHalMVOPCtx->bMirrorModeVer == TRUE)
3225 {
3226 stXCCrop->u16YStart |= 0x2000;
3227 }
3228 if(stXCCrop->u16YStart == 0)
3229 {
3230 stXCCrop->u16YStart |= 0x4000;
3231 }
3232 g_pHalMVOPCtx->u16CropYSize = stXCCrop->u16YSize;
3233
3234 break;
3235 }
3236 case E_MVOP_DEV_1:
3237 {
3238 #if MVOP_SUPPORT_SUB
3239 if(g_pHalMVOPCtx->u16SubCropXSize == 0)
3240 g_pHalMVOPCtx->u16SubCropXSize = u16Width;
3241
3242 if((stXCCrop->u16XStart + stXCCrop->u16XSize) > u16Width)
3243 {
3244 MVOP_PRINTF("[Warning] crop x size or start out of boundary.");
3245 return;
3246 }
3247
3248 if(g_pHalMVOPCtx->u16SubCropYSize == 0)
3249 g_pHalMVOPCtx->u16SubCropYSize = u16Height;
3250
3251 if((stXCCrop->u16YStart + stXCCrop->u16YSize) > u16Height)
3252 {
3253 MVOP_PRINTF("[Warning] crop y size or start out of boundary.");
3254 return;
3255 }
3256
3257 stXCCrop->u16XStart = ALIGN_UPTO_2(stXCCrop->u16XStart);
3258 stXCCrop->u16XSize = ALIGN_UPTO_2(stXCCrop->u16XSize);
3259 g_pHalMVOPCtx->u16SubCropXStart = stXCCrop->u16XStart;
3260 g_pHalMVOPCtx->u16SubCropXSize = stXCCrop->u16XSize;
3261
3262 #if 0 //sw patch, for monet/manhattan: maserati fix
3263 if((stXCCrop->u16YSize <= 512) && (stXCCrop->u16YStart == 0) && (g_pHalMVOPCtx->bSubMirrorModeVer == TRUE))
3264 {
3265 MVOP_PRINTF("[MVOP][Dbg] crop + mirror patch\n");
3266 stXCCrop->u16YStart = 1;
3267 stXCCrop->u16YStart = stXCCrop->u16YStart | 0x2000;
3268
3269 g_pHalMVOPCtx->u16SubCropYSize = stXCCrop->u16YSize;
3270 if(g_pHalMVOPCtx->bSubIsH265 == FALSE)
3271 {
3272 stXCCrop->u16YSize -= 1;
3273 }
3274 }
3275 else
3276 #endif
3277 g_pHalMVOPCtx->u16SubCropYStart = stXCCrop->u16YStart;
3278 //from maserati
3279 if(g_pHalMVOPCtx->bSubMirrorModeVer == TRUE)
3280 {
3281 stXCCrop->u16YStart |= 0x2000;
3282 }
3283 if(stXCCrop->u16YStart == 0)
3284 {
3285 stXCCrop->u16YStart |= 0x4000;
3286 }
3287 g_pHalMVOPCtx->u16SubCropYSize = stXCCrop->u16YSize;
3288
3289 #endif
3290 break;
3291 }
3292 default:
3293 MVOP_PRINTF("[Warning] MVOP_DevID not support!\n");
3294 break;
3295 }
3296 MVOP_DBG(MVOP_PRINTF("[Debug][Crop to XC] xsize = %d, ysize = %d, xstart = %d, ystart=%d\n",stXCCrop->u16XSize,stXCCrop->u16YSize,stXCCrop->u16XStart,stXCCrop->u16YStart);)
3297 return;
3298 }
3299
3300
HAL_MVOP_SupportFRCOutputFPS(MVOP_DevID eID)3301 MS_BOOL HAL_MVOP_SupportFRCOutputFPS(MVOP_DevID eID)
3302 {
3303 MS_BOOL bRet = FALSE;
3304 switch(eID)
3305 {
3306 case E_MVOP_DEV_0:
3307 bRet = TRUE;
3308 break;
3309 #if MVOP_SUPPORT_SUB
3310 case E_MVOP_DEV_1:
3311 bRet = TRUE;
3312 break;
3313 #endif
3314 default:
3315 break;
3316 }
3317 return bRet;
3318 }
3319
HAL_MVOP_GetIsCurrentHSK(MVOP_DevID eID)3320 MS_BOOL HAL_MVOP_GetIsCurrentHSK(MVOP_DevID eID)
3321 {
3322 MS_BOOL bRet = FALSE;
3323 switch(eID)
3324 {
3325 case E_MVOP_DEV_0:
3326 bRet = g_pHalMVOPCtx->bIsHS;
3327 break;
3328 case E_MVOP_DEV_1:
3329 #if MVOP_SUPPORT_SUB
3330 bRet = g_pHalMVOPCtx->bSubIsHS;
3331 #endif
3332 break;
3333 default:
3334 bRet = E_MVOP_HS_INVALID_PARAM;
3335 break;
3336 }
3337 return bRet;
3338 }
HAL_MVOP_ReadBank(MVOP_DevID eID,MS_U16 u16Length)3339 MS_U16 HAL_MVOP_ReadBank(MVOP_DevID eID ,MS_U16 u16Length)
3340 {
3341 MS_U16 u16Reg = 0;
3342 if(eID == E_MVOP_DEV_0)
3343 {
3344 u16Reg = HAL_Read2Byte(MVOP_REG_BASE + (u16Length << 1));
3345 }
3346 #ifdef MVOP_SUPPORT_SUB
3347 else if(eID == E_MVOP_DEV_1)
3348 {
3349 u16Reg = HAL_Read2Byte(SUB_REG(MVOP_REG_BASE + (u16Length << 1)));
3350 }
3351 #endif
3352 return u16Reg;
3353 }
3354
HAL_MVOP_SetInterlaceType(MVOP_DevID eDevID,MS_U8 u8Interlace)3355 void HAL_MVOP_SetInterlaceType(MVOP_DevID eDevID, MS_U8 u8Interlace)
3356 {
3357 MVOP_DBG(MVOP_PRINTF("%s u8Interlace = %d\n", __FUNCTION__ ,u8Interlace);)
3358
3359 switch(eDevID)
3360 {
3361 case E_MVOP_DEV_0:
3362
3363 switch(u8Interlace)
3364 {
3365 case 0:
3366 g_pHalMVOPCtx->eInterlaceType = E_MVOP_PRO;
3367 break;
3368 case 0x1:
3369 if(g_pHalMVOPCtx->bIsH265)
3370 {
3371 g_pHalMVOPCtx->eInterlaceType = E_MVOP_INT_TB_SEP_FRAME;
3372 }
3373 else
3374 {
3375 g_pHalMVOPCtx->eInterlaceType = E_MVOP_INT_TB_ONE_FRAME;
3376 }
3377 break;
3378 case 0x2:
3379 if(g_pHalMVOPCtx->bIsH265)
3380 {
3381 g_pHalMVOPCtx->eInterlaceType = E_MVOP_INT_TB_ONE_FRAME;
3382 }
3383 else
3384 {
3385 g_pHalMVOPCtx->eInterlaceType = E_MVOP_INT_TB_SEP_FRAME;
3386 }
3387 break;
3388 default:
3389 g_pHalMVOPCtx->eInterlaceType = E_MVOP_PRO;
3390 break;
3391 }
3392
3393 if((g_pHalMVOPCtx->eInterlaceType == E_MVOP_INT_TB_SEP_FRAME) && (g_pHalMVOPCtx->bIsH265))
3394 {
3395 HAL_WriteRegBit(VOP_INT_TYPE, 1, VOP_EVD_INT_SEP);
3396 }
3397 else if((g_pHalMVOPCtx->eInterlaceType == E_MVOP_INT_TB_ONE_FRAME) && (g_pHalMVOPCtx->bIsH265))
3398 {
3399 HAL_WriteRegBit(VOP_INT_TYPE, 0, VOP_EVD_INT_SEP);
3400 HAL_WriteRegBit(VOP_MIRROR_CFG, 0, VOP_FIELD_FROM_ADDR);
3401 }
3402 HAL_MVOP_LoadReg();
3403 break;
3404 #if MVOP_SUPPORT_SUB
3405 case E_MVOP_DEV_1:
3406
3407 switch(u8Interlace)
3408 {
3409 case 0:
3410 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_PRO;
3411 break;
3412 case 0x1:
3413 if(g_pHalMVOPCtx->bSubIsH265)
3414 {
3415 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_INT_TB_SEP_FRAME;
3416 }
3417 else
3418 {
3419 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_INT_TB_ONE_FRAME;
3420 }
3421 break;
3422 case 0x2:
3423 if(g_pHalMVOPCtx->bSubIsH265)
3424 {
3425 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_INT_TB_ONE_FRAME;
3426 }
3427 else
3428 {
3429 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_INT_TB_SEP_FRAME;
3430 }
3431 break;
3432 default:
3433 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_PRO;
3434 break;
3435 }
3436
3437 if((g_pHalMVOPCtx->eSubInterlaceType == E_MVOP_INT_TB_SEP_FRAME) && (g_pHalMVOPCtx->bSubIsH265))
3438 {
3439 HAL_WriteRegBit(SUB_REG(VOP_INT_TYPE), 1, VOP_EVD_INT_SEP);
3440 }
3441 else if((g_pHalMVOPCtx->eSubInterlaceType == E_MVOP_INT_TB_ONE_FRAME) && (g_pHalMVOPCtx->bSubIsH265))
3442 {
3443 HAL_WriteRegBit(SUB_REG(VOP_INT_TYPE), 0, VOP_EVD_INT_SEP);
3444 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 0, VOP_FIELD_FROM_ADDR);
3445 }
3446 HAL_MVOP_SubLoadReg();
3447 break;
3448 #endif
3449 default:
3450 MVOP_PRINTF("[Warning][%s] MVOP_DevID not support\n",__FUNCTION__);
3451 break;
3452 }
3453 }
3454
3455 #ifdef UFO_MVOP_GET_IS_XC_GEN_TIMING
HAL_MVOP_GetIsCurrentXCGenTiming(MVOP_DevID eID)3456 MS_BOOL HAL_MVOP_GetIsCurrentXCGenTiming(MVOP_DevID eID)
3457 {
3458 MS_BOOL bRet = FALSE;
3459 switch(eID)
3460 {
3461 case E_MVOP_DEV_0:
3462 bRet = g_pHalMVOPCtx->bIsXcTrig;
3463 break;
3464 case E_MVOP_DEV_1:
3465 #if MVOP_SUPPORT_SUB
3466 bRet = g_pHalMVOPCtx->bSubIsXcTrig;
3467 #endif
3468 break;
3469 default:
3470 bRet = E_MVOP_HS_INVALID_PARAM;
3471 break;
3472 }
3473 return bRet;
3474 }
3475 #endif
3476
3477 #ifdef UFO_MVOP_GET_IS_MVOP_AUTO_GEN_BLACK
HAL_MVOP_GetIsMVOPSupportBLKBackground(MVOP_DevID eID)3478 MS_BOOL HAL_MVOP_GetIsMVOPSupportBLKBackground(MVOP_DevID eID)
3479 {
3480 MS_BOOL bRet = FALSE;
3481 switch(eID)
3482 {
3483 case E_MVOP_DEV_0:
3484 bRet = TRUE;
3485 break;
3486 case E_MVOP_DEV_1:
3487 #if MVOP_SUPPORT_SUB
3488 bRet = TRUE;
3489 #endif
3490 break;
3491 default:
3492 bRet = E_MVOP_HS_INVALID_PARAM;
3493 break;
3494 }
3495 return bRet;
3496 }
3497 #endif
3498
HAL_MVOP_SetSramPower(MVOP_DevID eID,MS_BOOL bEnable)3499 void HAL_MVOP_SetSramPower(MVOP_DevID eID ,MS_BOOL bEnable)
3500 {
3501 switch(eID)
3502 {
3503 case E_MVOP_DEV_0:
3504 #if MVOP_SUPPORT_SUB
3505 if((bEnable== FALSE) && (g_pHalMVOPCtx->bSubIsEnable == FALSE)) //check sub disable -> mfdec sram disable
3506 {
3507 HAL_WriteRegBit(VOP_DC_STRIP_H, 1, MFDEC_SRAM_SD_MASK);
3508 HAL_WriteRegBit(VOP_DC_STRIP_H, 1, VOP_SRAM_SD_MASK);
3509 }
3510 else
3511 {
3512 HAL_WriteRegBit(VOP_DC_STRIP_H, 0, MFDEC_SRAM_SD_MASK);
3513 HAL_WriteRegBit(VOP_DC_STRIP_H, 0, VOP_SRAM_SD_MASK);
3514 }
3515 #else
3516 HAL_WriteRegBit(VOP_DC_STRIP_H, !bEnable, VOP_SRAM_SD_MASK);
3517 #endif
3518 break;
3519 #if MVOP_SUPPORT_SUB
3520 case E_MVOP_DEV_1:
3521 if((bEnable== FALSE) && (g_pHalMVOPCtx->bIsEnable == FALSE))
3522 {
3523 HAL_WriteRegBit(VOP_DC_STRIP_H, 1, MFDEC_SRAM_SD_MASK);
3524 HAL_WriteRegBit(VOP_DC_STRIP_H, 1, VOP_SRAM_SD_MASK);
3525 HAL_WriteRegBit(SUB_REG(VOP_DC_STRIP_H), 1, VOP_SRAM_SD_MASK);
3526 }
3527 else
3528 {
3529 HAL_WriteRegBit(VOP_DC_STRIP_H, 0, MFDEC_SRAM_SD_MASK);
3530 HAL_WriteRegBit(VOP_DC_STRIP_H, 0, VOP_SRAM_SD_MASK); //main need to enable, if sub enable.
3531 HAL_WriteRegBit(SUB_REG(VOP_DC_STRIP_H), 0, VOP_SRAM_SD_MASK);
3532 }
3533 break;
3534 #endif
3535 default:
3536 break;
3537 }
3538 return;
3539 }
3540
3541 /******************************************************************************/
3542 /// Set MVOP Handshake Mode, XC should be synchronous with MVOP.
3543 /// this command should be before mvop enable.(before 1st frame)
3544 /******************************************************************************/
HAL_MVOP_SetTimingFromXC(MVOP_DevID eID,MS_BOOL bEnable)3545 void HAL_MVOP_SetTimingFromXC(MVOP_DevID eID, MS_BOOL bEnable)
3546 {
3547 switch(eID)
3548 {
3549 MVOP_DBG(MVOP_PRINTF("[MVOP] HAL_MVOP_SetTimingFromXC = %d\n",bEnable);)
3550 case E_MVOP_DEV_0:
3551 {
3552 g_pHalMVOPCtx->bIsXcTrig = bEnable;
3553 if(bEnable)
3554 {
3555 HAL_WriteByteMask(VOP_REG_HS_OUTPUT, 0x06, VOP_TRIG_FROM_XC|VOP_VSUNC_FROM_XC);
3556 //HAL_WriteRegBit(VOP_CTRL1, 0, BIT4); // disable inverse the field to IP - not in kano
3557
3558 }
3559 else
3560 {
3561 HAL_WriteByteMask(VOP_REG_HS_OUTPUT, 0x00, VOP_TRIG_FROM_XC|VOP_VSUNC_FROM_XC);
3562 //HAL_WriteRegBit(VOP_CTRL1, 1, BIT4); // inverse the field to IP - not in kano
3563 }
3564 HAL_MVOP_LoadReg();
3565 break;
3566 }
3567 case E_MVOP_DEV_1:
3568 {
3569 #if MVOP_SUPPORT_SUB
3570 g_pHalMVOPCtx->bSubIsXcTrig = bEnable;
3571 if(bEnable)
3572 {
3573 HAL_WriteByteMask(SUB_REG(VOP_REG_HS_OUTPUT), 0x06, VOP_TRIG_FROM_XC|VOP_VSUNC_FROM_XC);
3574 }
3575 else
3576 {
3577 HAL_WriteByteMask(SUB_REG(VOP_REG_HS_OUTPUT), 0x00, VOP_TRIG_FROM_XC|VOP_VSUNC_FROM_XC);
3578 }
3579 HAL_MVOP_SubLoadReg();
3580 #endif
3581 break;
3582 }
3583 default:
3584 MVOP_PRINTF("[Warning] MVOP_DevID not support!\n");
3585 break;
3586 }
3587 }
3588
3589
3590 /////////////////////// Sub MVOP ////////////////////////
3591 #if MVOP_SUPPORT_SUB
HAL_MVOP_SubRegSetBase(MS_VIRT u32Base)3592 void HAL_MVOP_SubRegSetBase(MS_VIRT u32Base)
3593 {
3594 u32RiuBaseAdd = u32Base;
3595 }
3596
HAL_MVOP_SubInitMirrorMode(MS_BOOL bMir)3597 void HAL_MVOP_SubInitMirrorMode(MS_BOOL bMir)
3598 {
3599 //set bit[3:7] to support mirror mode
3600 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bMir, VOP_MIRROR_CFG_ENABLE);
3601 }
3602
HAL_MVOP_SubInit(void)3603 void HAL_MVOP_SubInit(void)
3604 {
3605 MVOP_HalInitCtxResults eRet;
3606 MS_BOOL pbFirstDrvInstant;
3607
3608 eRet = _HAL_MVOP_InitContext(&pbFirstDrvInstant);
3609 if(eRet == E_MVOP_INIT_FAIL)
3610 {
3611 MVOP_DBG(MVOP_PRINTF("[%s] MVOP Context Init failed!\n",__FUNCTION__);)
3612 return;
3613 }
3614 else if(eRet == E_MVOP_INIT_ALREADY_EXIST)
3615 {
3616 if(g_pHalMVOPCtx->bSubIsInit)
3617 {
3618 MVOP_DBG(MVOP_PRINTF("[%s] Sub MVOP Context has Initialized!\n",__FUNCTION__);)
3619 return;
3620 }
3621 }
3622 HAL_MVOP_SubInitMirrorMode(TRUE);
3623 //Enable dynamic clock gating
3624 //Note: cannot enable VOP_GCLK_VCLK_ON, or hsync cannot be sent out.
3625 HAL_WriteByteMask(SUB_REG(VOP_GCLK), VOP_GCLK_MIU_ON, VOP_GCLK_MIU_ON|VOP_GCLK_VCLK_ON);
3626 g_pHalMVOPCtx->bSubIsInit = 1;
3627 }
3628
HAL_MVOP_SubSetVerticalMirrorMode(MS_BOOL bEnable)3629 void HAL_MVOP_SubSetVerticalMirrorMode(MS_BOOL bEnable)
3630 {
3631 if (g_pHalMVOPCtx == NULL)
3632 {
3633 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
3634 return;
3635 }
3636 if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(SUB_REG(VOP_MIRROR_CFG), VOP_MIRROR_CFG_ENABLE))
3637 {
3638 //MVOP_PRINTF("Setup mirror mode\n");
3639 HAL_MVOP_SubInitMirrorMode(TRUE);
3640 }
3641
3642 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnable, VOP_MIRROR_CFG_VEN);
3643 g_pHalMVOPCtx->bSubMirrorModeVer = bEnable;
3644 }
3645
HAL_MVOP_SubSetHorizontallMirrorMode(MS_BOOL bEnable)3646 void HAL_MVOP_SubSetHorizontallMirrorMode(MS_BOOL bEnable)
3647 {
3648 if (g_pHalMVOPCtx == NULL)
3649 {
3650 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
3651 return;
3652 }
3653 if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(SUB_REG(VOP_MIRROR_CFG), VOP_MIRROR_CFG_ENABLE))
3654 {
3655 //MVOP_PRINTF("Setup mirror mode\n");
3656 HAL_MVOP_SubInitMirrorMode(TRUE);
3657 }
3658
3659 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnable, VOP_MIRROR_CFG_HEN);
3660 g_pHalMVOPCtx->bSubMirrorModeHor = bEnable;
3661 }
3662
HAL_MVOP_SubSetFieldInverse(MS_BOOL b2MVD,MS_BOOL b2IP)3663 void HAL_MVOP_SubSetFieldInverse(MS_BOOL b2MVD, MS_BOOL b2IP)
3664 {
3665 // Set fld inv & ofld_inv
3666 HAL_WriteRegBit(SUB_REG(VOP_CTRL0+1), b2MVD, BIT3); //inverse the field to MVD
3667 HAL_WriteRegBit(SUB_REG(VOP_CTRL0+1), b2IP, BIT4); //inverse the field to IP
3668 }
3669
HAL_MVOP_SubSetChromaWeighting(MS_BOOL bEnable)3670 void HAL_MVOP_SubSetChromaWeighting(MS_BOOL bEnable)
3671 {
3672 HAL_WriteRegBit(SUB_REG(VOP_REG_WEIGHT_CTRL), bEnable, BIT1);
3673 }
3674
3675 //load new value into active registers 0x20-0x26
HAL_MVOP_SubLoadReg(void)3676 void HAL_MVOP_SubLoadReg(void)
3677 {
3678 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT0);
3679 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT0);
3680
3681 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT4);
3682 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT4);
3683 }
3684
HAL_MVOP_SubSetMIUReqMask(MS_BOOL bEnable)3685 void HAL_MVOP_SubSetMIUReqMask(MS_BOOL bEnable)
3686 {
3687 #if 0
3688 if (bEnable)
3689 { // mask MVOP2MI to protect MIU
3690 HAL_MIU_SubSetReqMask(SUBMVOP_R, 1);
3691 MsOS_DelayTask(1);
3692 }
3693 else
3694 { // unmask MVOP2MI
3695 MsOS_DelayTask(1);
3696 HAL_MIU_SubSetReqMask(SUBMVOP_R, 0);
3697 }
3698 #endif
3699 MS_U8 u8Miu;
3700 if(HAL_MVOP_GetIsOnlyMiuIPControl() == TRUE)
3701 {
3702 // mask msb mvop
3703 u8Miu = (HAL_ReadByte(SUB_REG(VOP_MIU_SEL)) & VOP_MSB_BUF0_MIU_SEL) >> 4;
3704 }
3705 else
3706 {
3707 u8Miu = SUBVOP_ON_MIU1;
3708 }
3709 eMIUClientID eClientID = MIU_CLIENT_MVOP1_R;
3710 //MVOP_PRINTF("Enter %s bEnable=%x ReqMask=0x%x, 0x%x, u8Miu=%x\n", __FUNCTION__, bEnable,
3711 // HAL_ReadByte(0x1266), HAL_ReadByte(0x0666), u8Miu);
3712
3713 if (bEnable)
3714 { // mask MVOP2MI to protect MIU
3715 MDrv_MIU_MaskReq(u8Miu, eClientID);
3716 MsOS_DelayTask(1);
3717 }
3718 else
3719 { // unmask MVOP2MI
3720 MsOS_DelayTask(1);
3721 MDrv_MIU_UnMaskReq(u8Miu, eClientID);
3722 }
3723
3724 //MVOP_PRINTF(">Exit %s bEnable=%x ReqMask=0x%x, 0x%x, u8Miu=%x\n", __FUNCTION__, bEnable,
3725 // HAL_ReadByte(0x1266), HAL_ReadByte(0x0666), u8Miu);
3726 }
3727
HAL_MVOP_SubRst(void)3728 void HAL_MVOP_SubRst(void)
3729 {
3730 #if 0
3731 MS_BOOL bMCU = FALSE;
3732
3733 bMCU = HAL_ReadRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), BIT1);
3734 #endif
3735 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 0, BIT0);
3736 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 1, BIT0);
3737
3738 g_pHalMVOPCtx->bSubIsEnable = 1;
3739 #if 0
3740 // sw patch: for mvop hsk mode, switching mvop enable/disable may cause video was stuck.
3741 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] HAL_MVOP_Enable patch \n");)
3742 HAL_MVOP_SubSetBlackBG();
3743 HAL_MVOP_SubSetPattern(MVOP_PATTERN_FRAMECOLOR);
3744 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT4);
3745 HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 1, BIT1);
3746 MsOS_DelayTask(40);
3747 if(bMCU == FALSE)
3748 {
3749 HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 0, BIT1);
3750 }
3751 HAL_MVOP_SubSetPattern(MVOP_PATTERN_NORMAL);
3752 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT4);
3753 #endif
3754 }
3755
HAL_MVOP_SubEnable(MS_BOOL bEnable,MS_U8 u8Framerate)3756 void HAL_MVOP_SubEnable(MS_BOOL bEnable, MS_U8 u8Framerate)
3757 {
3758 MS_U8 regval;
3759 #if 0
3760 MS_U8 u8FrmDur = 40;
3761 MS_BOOL bMCU = FALSE;
3762
3763 bMCU = HAL_ReadRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), BIT1);
3764
3765 if(u8Framerate != 0)
3766 {
3767 u8FrmDur = 1000/u8Framerate; //time of one frame(ms).
3768 }
3769 #endif
3770 regval = HAL_ReadByte(SUB_REG(VOP_CTRL0));
3771
3772 if ( bEnable )
3773 {
3774 regval |= 0x1;
3775 }
3776 else
3777 {
3778 regval &= ~0x1;
3779 HAL_Write2Byte(SUB_REG(VOP_BF_VS_MVD), 0x200);
3780 HAL_Write2Byte(SUB_REG(VOP_TF_VS_MVD), 0x200);
3781 }
3782 #if 0
3783 // sw patch: for mvop hsk mode, switching mvop enable/disable may cause video was stuck.
3784 if ( bEnable && (g_pHalMVOPCtx->bSubIsEnable == FALSE)) // need patch only from off to on
3785 {
3786 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] HAL_MVOP_Enable patch \n");)
3787 HAL_MVOP_SubSetBlackBG();
3788 HAL_MVOP_SubSetPattern(MVOP_PATTERN_FRAMECOLOR);
3789 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT4);
3790 HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 1, BIT1);
3791 MsOS_DelayTask(u8FrmDur);
3792 if(bMCU == FALSE)
3793 {
3794 HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 0, BIT1);
3795 }
3796 HAL_MVOP_SubSetPattern(MVOP_PATTERN_NORMAL);
3797 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT4);
3798 }
3799 #endif
3800 g_pHalMVOPCtx->bSubIsEnable = bEnable;
3801
3802 HAL_WriteByte(SUB_REG(VOP_CTRL0), regval);
3803
3804 }
3805
HAL_MVOP_SubGetEnableState(void)3806 MS_BOOL HAL_MVOP_SubGetEnableState(void)
3807 {
3808 return (HAL_ReadRegBit(SUB_REG(VOP_CTRL0), BIT0));
3809 }
3810
HAL_MVOP_SubGetMaxFreerunClk()3811 HALMVOPFREQUENCY HAL_MVOP_SubGetMaxFreerunClk()
3812 {
3813 return HALMVOP_160MHZ;
3814 }
3815
HAL_MVOP_SubGet4k2kClk()3816 HALMVOPFREQUENCY HAL_MVOP_SubGet4k2kClk()
3817 {
3818 return HALMVOP_320MHZ;
3819 }
3820
3821 //FIXME
HAL_MVOP_SubSetFrequency(HALMVOPFREQUENCY enFrequency)3822 void HAL_MVOP_SubSetFrequency(HALMVOPFREQUENCY enFrequency)
3823 {
3824 // clear
3825 HAL_WriteByteMask(REG_CKG_SUB_DC0, 0, CKG_SUB_DC0_MASK);
3826 switch(enFrequency)
3827 {
3828 case HALMVOP_SYNCMODE:
3829 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_SYNCHRONOUS, CKG_SUB_DC0_MASK);
3830 break;
3831 case HALMVOP_FREERUNMODE:
3832 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_FREERUN, CKG_SUB_DC0_MASK);
3833 break;
3834 case HALMVOP_160MHZ:
3835 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_160MHZ, CKG_SUB_DC0_MASK);
3836 break;
3837 case HALMVOP_144MHZ:
3838 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_144MHZ, CKG_SUB_DC0_MASK);
3839 break;
3840 case HALMVOP_320MHZ:
3841 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_320MHZ, CKG_SUB_DC0_MASK);
3842 break;
3843 default:
3844 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_SYNCHRONOUS, CKG_SUB_DC0_MASK);
3845 MVOP_PRINTF("Attention! In HAL_MVOP_SubSetFrequency default path!\n");
3846 break;
3847 }
3848 }
3849
HAL_MVOP_SubSetOutputInterlace(MS_BOOL bEnable)3850 void HAL_MVOP_SubSetOutputInterlace(MS_BOOL bEnable)
3851 {
3852 MS_U8 regval;
3853
3854 regval = HAL_ReadByte(SUB_REG(VOP_CTRL0));
3855
3856 if ( bEnable )
3857 {
3858 regval |= 0x80;
3859 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
3860 }
3861 else
3862 {
3863 regval &= ~0x80;
3864 }
3865
3866 HAL_WriteByte(SUB_REG(VOP_CTRL0), regval);
3867 }
3868
HAL_MVOP_SubSetPattern(MVOP_Pattern enMVOPPattern)3869 void HAL_MVOP_SubSetPattern(MVOP_Pattern enMVOPPattern)
3870 {
3871 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), enMVOPPattern, BIT2 | BIT1 | BIT0);
3872 }
3873
HAL_MVOP_SubSetTileFormat(MVOP_TileFormat eTileFmt)3874 MS_BOOL HAL_MVOP_SubSetTileFormat(MVOP_TileFormat eTileFmt)
3875 {
3876 if (eTileFmt == E_MVOP_TILE_8x32)
3877 {
3878 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
3879 return TRUE;
3880 }
3881 else if (eTileFmt == E_MVOP_TILE_16x32)
3882 {
3883 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
3884 return TRUE;
3885 }
3886 else
3887 {
3888 return FALSE;
3889 }
3890 }
3891
HAL_MVOP_SubSetRgbFormat(MVOP_RgbFormat eRgbFmt)3892 MS_BOOL HAL_MVOP_SubSetRgbFormat(MVOP_RgbFormat eRgbFmt)
3893 {
3894 MS_BOOL bRet = FALSE;
3895
3896 if (g_pHalMVOPCtx == NULL)
3897 {
3898 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
3899 return FALSE;
3900 }
3901 if (eRgbFmt == E_MVOP_RGB_NONE)
3902 {
3903 HAL_WriteByteMask(SUB_REG(VOP_RGB_FMT), 0, VOP_RGB_FMT_SEL);
3904 bRet = TRUE;
3905 }
3906 else if (eRgbFmt == E_MVOP_RGB_565)
3907 {
3908 HAL_WriteByteMask(SUB_REG(VOP_RGB_FMT), VOP_RGB_FMT_565, VOP_RGB_FMT_SEL);
3909 bRet = TRUE;
3910 }
3911 else if (eRgbFmt == E_MVOP_RGB_888)
3912 {
3913 HAL_WriteByteMask(SUB_REG(VOP_RGB_FMT), VOP_RGB_FMT_888, VOP_RGB_FMT_SEL);
3914 bRet = TRUE;
3915 }
3916
3917 if (bRet == TRUE)
3918 {
3919 g_pHalMVOPCtx->eSubRgbFmt = eRgbFmt;
3920 }
3921 return bRet;
3922 }
3923
HAL_MVOP_SubSetBlackBG(void)3924 void HAL_MVOP_SubSetBlackBG(void)
3925 {
3926 MS_U8 regval;
3927
3928 //set MVOP test pattern to black
3929 HAL_WriteByte(SUB_REG(VOP_TST_IMG + 1), 0x10);
3930 HAL_WriteByte(SUB_REG(VOP_U_PAT ), 0x80);
3931 HAL_WriteByte(SUB_REG(VOP_U_PAT + 1), 0x80);
3932
3933 regval = HAL_ReadByte(SUB_REG(VOP_TST_IMG));
3934 HAL_WriteByte(SUB_REG(VOP_TST_IMG), 0x02);
3935 HAL_WriteByte(SUB_REG(VOP_TST_IMG), 0x00);
3936 HAL_WriteByte(SUB_REG(VOP_TST_IMG), regval);
3937 }
3938
HAL_MVOP_SubSetCropWindow(MVOP_InputCfg * pparam)3939 void HAL_MVOP_SubSetCropWindow(MVOP_InputCfg *pparam)
3940 {
3941 #if 1
3942 UNUSED(pparam);
3943 #else // enable it when test code is ready
3944 MS_U32 x, y;
3945 MS_U32 u32offset;
3946
3947 if(!pparam)
3948 {
3949 return;
3950 }
3951 //set MVOP test pattern to black
3952 HAL_MVOP_SubSetBlackBG();
3953 #if 0
3954 if((pparam->enVideoType == MVOP_H264) && (pparam->u16StripSize == 1920))
3955 {
3956 pparam->u16StripSize = 1952;
3957 }
3958 #endif
3959 if((pparam->enVideoType == MVOP_MPG) || (pparam->enVideoType == MVOP_MPEG4))
3960 {
3961 pparam->u16CropX = (pparam->u16CropX >> 3) << 3; // 8 bytes align
3962 pparam->u16CropY = (pparam->u16CropY >> 6) << 6; // 64 bytes align
3963 }
3964 else if((pparam->enVideoType == MVOP_H264) || (pparam->enVideoType == MVOP_RM))
3965 {
3966 pparam->u16CropX = (pparam->u16CropX >> 4) << 4; // 16 bytes align
3967 pparam->u16CropY = (pparam->u16CropY >> 6) << 6; // 64 bytes align
3968 }
3969 else
3970 {
3971 MS_ASSERT(0);
3972 }
3973
3974 x = (MS_U32)pparam->u16CropX;
3975 y = (MS_U32)pparam->u16CropY;
3976
3977 // y offset
3978 u32offset = ((y * pparam->u16StripSize + (x << 5)) >> 3);
3979 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L ), (MS_U8)(u32offset));
3980 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L + 1), (MS_U8)(u32offset >> 8));
3981 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_H ), (MS_U8)(u32offset >> 16));
3982 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_H + 1), (MS_U8)((u32offset >> 24) & VOP_YUV_STR_HIBITS));
3983
3984 // uv offset
3985 u32offset = ((y >> 1) * pparam->u16StripSize + (x << 5)) >> 3;
3986 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L ), (MS_U8)(u32offset));
3987 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L + 1), (MS_U8)(u32offset >> 8));
3988 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_H ), (MS_U8)(u32offset >> 16));
3989 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_H + 1), (MS_U8)((u32offset >> 24) & VOP_YUV_STR_HIBITS));
3990
3991 pparam->u16CropWidth= (pparam->u16CropWidth >> 3) << 3;
3992 // HSize, VSize
3993 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE ), LOWBYTE(pparam->u16CropWidth ));
3994 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE + 1), HIGHBYTE(pparam->u16CropWidth ));
3995 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE ), LOWBYTE(pparam->u16CropHeight));
3996 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE + 1), HIGHBYTE(pparam->u16CropHeight ));
3997
3998 HAL_WriteByteMask(SUB_REG(VOP_MPG_JPG_SWITCH), BIT0, BIT1|BIT0);
3999
4000 // clear extend strip len bit by default
4001 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4002 if((pparam->enVideoType == MVOP_MPG) || (pparam->enVideoType == MVOP_MPEG4))
4003 {
4004 // Disable H264 or RM Input
4005 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH), 0, BIT2|BIT3);
4006 //8*32 tile format
4007 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
4008 }
4009 else if((pparam->enVideoType == MVOP_H264) || (pparam->enVideoType == MVOP_RM))
4010 {
4011 //16*32 tile format
4012 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
4013 // SVD mode enable
4014 HAL_WriteByteMask(SUB_REG(VOP_INPUT_SWITCH), BIT3, BIT2|BIT3);
4015 // set mvop to 128bit_i128 interface
4016 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4017 }
4018 HAL_MVOP_SubLoadReg();
4019 #endif
4020 }
4021
HAL_MVOP_SubSetRepeatField(MVOP_RptFldMode eMode)4022 void HAL_MVOP_SubSetRepeatField(MVOP_RptFldMode eMode)
4023 {
4024 if (g_pHalMVOPCtx == NULL)
4025 {
4026 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4027 return;
4028 }
4029 g_pHalMVOPCtx->eSubRepeatField = eMode;
4030 }
4031
HAL_MVOP_SubSetInputMode(VOPINPUTMODE mode,MVOP_InputCfg * pparam,MS_U16 u16ECOVersion)4032 void HAL_MVOP_SubSetInputMode( VOPINPUTMODE mode, MVOP_InputCfg *pparam, MS_U16 u16ECOVersion )
4033 {
4034 MS_U8 regval;
4035 MS_U16 u16strip, u16strip_lsb;
4036
4037 if (g_pHalMVOPCtx == NULL)
4038 {
4039 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4040 return;
4041 }
4042
4043 #if 0
4044 /*****************************************************/
4045 // Reset MVOP setting
4046 HAL_WriteByte(SUB_REG(VOP_TST_IMG), 0x40);
4047 HAL_MVOP_SubSetRgbFormat(E_MVOP_RGB_NONE);
4048 HAL_WriteRegBit(SUB_REG(VOP_CTRL1), 0, VOP_MVD_VS_MD); //default use original vsync
4049 // Only for Monaco: Enable deciding bot by top address + 2
4050 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 1, VOP_FIELD_FROM_ADDR);
4051
4052 //set MVOP test pattern to black
4053 HAL_MVOP_SubSetBlackBG();
4054
4055 // clear extend strip len bit by default
4056 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4057
4058 // set mvop to 128bit_i128 interface
4059 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4060
4061 // Disable H264 or RM Input
4062 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH1), 0, BIT2|BIT3);
4063 // Clear 422 Flag
4064 g_pHalMVOPCtx->bSubIs422 = 0;
4065 // Clear evd Flag for interlace mode setting
4066 g_pHalMVOPCtx->bSubIsH265 = 0;
4067 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_L), 1, BIT3);
4068 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 1, BIT5);
4069 //8*32 tile format
4070 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
4071 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD);
4072 HAL_MVOP_SubSetFieldInverse(ENABLE, ENABLE);
4073 // EVD mode disable
4074 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, EVD_ENABLE);
4075 // EVD 10 bits
4076 HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), BIT1, VOP_LSB_REQ_MASK);
4077 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_Y_EN);
4078 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_UV_EN);
4079 HAL_WriteRegBit(SUB_REG(VOP_UV_SHIFT), 1, VOP_GCLK_MIU_ON);
4080 // VP9 MODE disable
4081 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, VOP_R2_WISHBONE);
4082 HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 0, VOP_DRAM_RD_MODE);
4083 // Disable 2p mode
4084 HAL_MVOP_SubSetEnable4k2k2P(FALSE);
4085 /*****************************************************/
4086 #endif
4087 regval = 0;
4088 regval |= ( mode & 0x3 );
4089
4090 if ( mode == VOPINPUT_HARDWIRE )
4091 {
4092 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), regval);
4093 }
4094 else if ( mode == VOPINPUT_HARDWIRECLIP )
4095 {
4096 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), regval);
4097
4098 // HSize, VSize
4099 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE ), LOWBYTE( pparam->u16HSize ));
4100 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE + 1), HIGHBYTE( pparam->u16HSize ));
4101 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE ), LOWBYTE( pparam->u16VSize ));
4102 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE + 1), HIGHBYTE( pparam->u16VSize ));
4103 }
4104 else if (mode == VOPINPUT_MCUCTRL)
4105 {
4106 // disable from wb
4107 HAL_WriteRegBit(SUB_REG(VOP_REG_MFDEC_2_L), 0, VOP_MF_FROM_WB);
4108 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, VOP_R2_WISHBONE);
4109 g_pHalMVOPCtx->bSubMirrorMode = (g_pHalMVOPCtx->bSubMirrorModeVer||g_pHalMVOPCtx->bSubMirrorModeHor);
4110 if ( pparam->bProgressive )
4111 regval |= 0x4;
4112 else
4113 {
4114 regval &= ~0x4;
4115 regval |= 0x1; //reg_dc_md=b'11 for interlace input
4116 if (E_MVOP_RPTFLD_NONE == g_pHalMVOPCtx->eSubRepeatField)
4117 {
4118 MVOP_DBG("%s normal NOT repeat field %x\n", __FUNCTION__, g_pHalMVOPCtx->eSubRepeatField);
4119 //To support mcu mode interlace, need to set h'3B[9]=1,
4120 //h'11[12]=0, and Y1/UV1 address equal to Y0/UV0 address.
4121 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 1, VOP_REF_SELF_FLD);
4122 HAL_MVOP_SubSetFieldInverse(ENABLE, DISABLE);
4123 }
4124 }
4125
4126 if ( pparam->bYUV422 )
4127 regval |= 0x10;
4128 else
4129 regval &= ~0x10;
4130
4131 if ( pparam->b422pack )
4132 regval |= 0x80;
4133
4134 if ( pparam->bDramRdContd == 1 )
4135 regval |= 0x20;
4136 else
4137 regval &= ~0x20;
4138
4139 // for backward compatable to saturn
4140 // [3] UV-7bit mode don't care
4141 // [5] dram_rd_md =0
4142 // [6] Fld don't care
4143 // [7] 422pack don'care
4144 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), regval);
4145 g_pHalMVOPCtx->bSubIs422 = pparam->bYUV422;
4146
4147 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), !pparam->bYUV422, VOP_420_BW_SAVE);
4148 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), !pparam->bYUV422, VOP_420_BW_SAVE_EX);
4149
4150 if (pparam->u16StripSize == 0)
4151 {
4152 if (pparam->bSD)
4153 {
4154 u16strip = 720;
4155 u16strip_lsb = 720;
4156 }
4157 else
4158 {
4159 u16strip = 1920;
4160 u16strip_lsb = 1920;
4161 }
4162 }
4163 else
4164 {
4165 u16strip = pparam->u16StripSize;
4166 u16strip_lsb = pparam->u16StripSize;
4167 }
4168
4169 // set dc_strip[7:0]
4170 if (pparam->bDramRdContd == 0)
4171 {
4172 u16strip = (u16strip + 31) / 32 * 32; //need align for monaco
4173 u16strip = u16strip/8;
4174 u16strip_lsb = (u16strip_lsb+127)/128;
4175 u16strip_lsb *= 4;
4176 }
4177 else
4178 {
4179 if ( pparam->b422pack )
4180 {
4181 if (E_MVOP_RGB_888 == g_pHalMVOPCtx->eSubRgbFmt)
4182 {
4183 u16strip *= 2;
4184 }
4185
4186 if ((u16strip < 1024) || g_pHalMVOPCtx->bSubMirrorMode)
4187 {
4188 u16strip = u16strip/4;
4189 // dont extend strip len
4190 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4191 }
4192 else
4193 {
4194 u16strip = u16strip/8;
4195 // extend strip len to 2048
4196 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 1, BIT0);
4197 }
4198 }
4199 else
4200 {
4201 u16strip = u16strip/8;
4202 }
4203 }
4204
4205 if (u16strip >= 256 )
4206 {
4207 HAL_WriteByte(SUB_REG(VOP_DC_STRIP_H), (u16strip>>8));
4208 //reg_dc_strip_h[2:0] = reg_dc_strip[10:8]
4209 }
4210 else
4211 {
4212 HAL_WriteByteMask(SUB_REG(VOP_DC_STRIP_H), 0, BIT0 | BIT1 | BIT2);
4213 }
4214
4215 regval = u16strip;
4216 HAL_WriteByte(SUB_REG(VOP_DC_STRIP), regval);
4217 //LSB strip
4218 HAL_WriteByte(SUB_REG(VOP_DC_STRIP_LSB), u16strip_lsb & 0x3ff);
4219
4220 HAL_MVOP_SubSetYUVBaseAdd(pparam->u32YOffset, pparam->u32UVOffset,
4221 pparam->bProgressive, pparam->b422pack);
4222
4223 if (E_MVOP_RPTFLD_NONE != g_pHalMVOPCtx->eSubRepeatField)
4224 {
4225 MVOP_DBG("%s reset eRepeatField=%x ==>", __FUNCTION__, g_pHalMVOPCtx->eSubRepeatField);
4226 //To output the same field for single field input,
4227 //do NOT set h'3B[9]=1 and h'11[12]=0
4228 g_pHalMVOPCtx->eSubRepeatField = E_MVOP_RPTFLD_NONE; //reset the flag to repeat field
4229 MVOP_DBG(" %x\n", g_pHalMVOPCtx->eSubRepeatField);
4230 }
4231
4232 // HSize
4233 MS_U16 u16HSize = ALIGN_UPTO_16(pparam->u16HSize);
4234 if (u16HSize != pparam->u16HSize)
4235 {
4236 MVOP_DBG(MVOP_PRINTF("\n\n Change HSize %d to %d\n", pparam->u16HSize, u16HSize);)
4237 }
4238 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE ), LOWBYTE( u16HSize ));
4239 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE + 1), HIGHBYTE( u16HSize ));
4240
4241 // VSize
4242 MS_U16 u16VSize = pparam->u16VSize;
4243 if (g_pHalMVOPCtx->bSubMirrorModeVer)
4244 {
4245 u16VSize = ALIGN_UPTO_4(pparam->u16VSize);
4246 MVOP_DBG(MVOP_PRINTF("\n\n Change VSize %d to %d\n", pparam->u16VSize, u16VSize);)
4247 }
4248 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE ), LOWBYTE( u16VSize ));
4249 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE + 1), HIGHBYTE( u16VSize ));
4250 }
4251
4252 HAL_MVOP_SubLoadReg();
4253 }
4254
4255
HAL_MVOP_SubEnableUVShift(MS_BOOL bEnable)4256 void HAL_MVOP_SubEnableUVShift(MS_BOOL bEnable)
4257 {
4258 MS_U8 regval;
4259
4260 regval = HAL_ReadByte(SUB_REG(VOP_MPG_JPG_SWITCH));
4261
4262 if (((regval & BIT4) == BIT4) && ((regval & 0x3)== 0x2))
4263 { // 422 with MCU control mode
4264 if (bEnable)
4265 {
4266 MS_ASSERT(0);
4267 }
4268 }
4269
4270 // output 420 and interlace
4271 //[IP - Sheet] : Main Page --- 420CUP
4272 //[Project] : Titania2
4273 //[Description]: Chroma artifacts when 420to422 is applied duplicate method.
4274 //[Root cause]: Apply 420to422 average algorithm to all DTV input cases.
4275 //The average algorithm must cooperate with MVOP.
4276 HAL_WriteByteMask(SUB_REG(VOP_UV_SHIFT), (bEnable)?1:0, 0x3);
4277 }
4278
4279 static MS_BOOL _bSubEnable60P = false;
HAL_MVOP_SubSetEnable60P(MS_BOOL bEnable)4280 void HAL_MVOP_SubSetEnable60P(MS_BOOL bEnable)
4281 {
4282 _bSubEnable60P = bEnable;
4283 }
4284
4285 static MS_BOOL _bSubEnable4k2kClk = false;
HAL_MVOP_SubSetEnable4k2kClk(MS_BOOL bEnable)4286 void HAL_MVOP_SubSetEnable4k2kClk(MS_BOOL bEnable)
4287 {
4288 _bSubEnable4k2kClk = bEnable;
4289 }
4290
4291
HAL_MVOP_SubSetEnable4k2k2P(MS_BOOL bEnable)4292 void HAL_MVOP_SubSetEnable4k2k2P(MS_BOOL bEnable)
4293 {
4294 g_pHalMVOPCtx->bSubIs2p = bEnable;
4295 HAL_WriteRegBit(SUB_REG(VOP_REG_4K2K_2P), bEnable, VOP_4K2K_2P);
4296
4297 }
4298
HAL_MVOP_SubEnableFreerunMode(MS_BOOL bEnable)4299 void HAL_MVOP_SubEnableFreerunMode(MS_BOOL bEnable)
4300 {
4301 if (g_pHalMVOPCtx == NULL)
4302 {
4303 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4304 return;
4305 }
4306 g_pHalMVOPCtx->bSubEnableFreerunMode = bEnable;
4307 }
4308
HAL_MVOP_SubSetOutputTiming(MVOP_Timing * ptiming)4309 void HAL_MVOP_SubSetOutputTiming( MVOP_Timing *ptiming )
4310 {
4311 MS_U8 regval;
4312
4313 HAL_WriteByte(SUB_REG(VOP_FRAME_VCOUNT ), LOWBYTE( ptiming->u16V_TotalCount ));
4314 HAL_WriteByte(SUB_REG(VOP_FRAME_VCOUNT + 1), HIGHBYTE( ptiming->u16V_TotalCount ));
4315 HAL_WriteByte(SUB_REG(VOP_FRAME_HCOUNT ), LOWBYTE( ptiming->u16H_TotalCount ));
4316 HAL_WriteByte(SUB_REG(VOP_FRAME_HCOUNT + 1), HIGHBYTE( ptiming->u16H_TotalCount ));
4317
4318 HAL_WriteByte(SUB_REG(VOP_VB0_STR ), LOWBYTE( ptiming->u16VBlank0_Start ));
4319 HAL_WriteByte(SUB_REG(VOP_VB0_STR + 1), HIGHBYTE( ptiming->u16VBlank0_Start ));
4320 HAL_WriteByte(SUB_REG(VOP_VB0_END ), LOWBYTE( ptiming->u16VBlank0_End ));
4321 HAL_WriteByte(SUB_REG(VOP_VB0_END + 1), HIGHBYTE( ptiming->u16VBlank0_End ));
4322 HAL_WriteByte(SUB_REG(VOP_VB1_STR ), LOWBYTE( ptiming->u16VBlank1_Start ));
4323 HAL_WriteByte(SUB_REG(VOP_VB1_STR + 1), HIGHBYTE( ptiming->u16VBlank1_Start ));
4324 HAL_WriteByte(SUB_REG(VOP_VB1_END ), LOWBYTE( ptiming->u16VBlank1_End ));
4325 HAL_WriteByte(SUB_REG(VOP_VB1_END + 1), HIGHBYTE( ptiming->u16VBlank1_End ));
4326 HAL_WriteByte(SUB_REG(VOP_TF_STR ), LOWBYTE( ptiming->u16TopField_Start ));
4327 HAL_WriteByte(SUB_REG(VOP_TF_STR + 1), HIGHBYTE( ptiming->u16TopField_Start ));
4328 HAL_WriteByte(SUB_REG(VOP_BF_STR ), LOWBYTE( ptiming->u16BottomField_Start ));
4329 HAL_WriteByte(SUB_REG(VOP_BF_STR + 1), HIGHBYTE( ptiming->u16BottomField_Start ));
4330 HAL_WriteByte(SUB_REG(VOP_HACT_STR ), LOWBYTE( ptiming->u16HActive_Start ));
4331 HAL_WriteByte(SUB_REG(VOP_HACT_STR + 1), HIGHBYTE( ptiming->u16HActive_Start ));
4332
4333 HAL_WriteByte(SUB_REG(VOP_TF_VS ), LOWBYTE( ptiming->u16TopField_VS ));
4334 HAL_WriteByte(SUB_REG(VOP_TF_VS + 1), HIGHBYTE( ptiming->u16TopField_VS ));
4335 HAL_WriteByte(SUB_REG(VOP_BF_VS ), LOWBYTE( ptiming->u16BottomField_VS ));
4336 HAL_WriteByte(SUB_REG(VOP_BF_VS + 1), HIGHBYTE( ptiming->u16BottomField_VS ));
4337
4338 if((ptiming->u16Height >= 2160 || ptiming->u16Width >= 3840) && (ptiming->bInterlace == FALSE))
4339 {
4340 //Monet 4k2k pmode default 30 lines forwarding.
4341 g_pHalMVOPCtx->bSubNewVSyncMode = TRUE;
4342 g_pHalMVOPCtx->u16SubVsyncLines = 0;
4343 }
4344
4345 if (g_pHalMVOPCtx->bSubNewVSyncMode)
4346 {
4347 #define SUB_NEW_VSYNC_MODE_ADVANCE_LINECNT 30
4348 MS_U16 u16BottomField_VS2MVD;
4349 MS_U16 u16TopField_VS2MVD;
4350 MVOP_DBG(MVOP_PRINTF("MVOP use new vync mode, forwarding %d lines\n",SUB_NEW_VSYNC_MODE_ADVANCE_LINECNT);)
4351
4352 if(g_pHalMVOPCtx->u16SubVsyncLines == 0)
4353 u16BottomField_VS2MVD = ptiming->u16BottomField_VS - SUB_NEW_VSYNC_MODE_ADVANCE_LINECNT;
4354 else
4355 u16BottomField_VS2MVD = ptiming->u16BottomField_VS - g_pHalMVOPCtx->u16SubVsyncLines;
4356 MVOP_DBG(MVOP_PRINTF("BottomField VS ori=0x%x, new=0x%x\n", ptiming->u16BottomField_VS, u16BottomField_VS2MVD);)
4357 HAL_WriteByte(SUB_REG(VOP_BF_VS_MVD), LOWBYTE( u16BottomField_VS2MVD ));
4358 HAL_WriteByte(SUB_REG((VOP_BF_VS_MVD + 1)), HIGHBYTE( u16BottomField_VS2MVD ));
4359
4360 if(g_pHalMVOPCtx->u16SubVsyncLines == 0)
4361 u16TopField_VS2MVD = ptiming->u16V_TotalCount - SUB_NEW_VSYNC_MODE_ADVANCE_LINECNT;
4362 else
4363 u16TopField_VS2MVD = ptiming->u16V_TotalCount - g_pHalMVOPCtx->u16SubVsyncLines;
4364 MVOP_DBG(MVOP_PRINTF("TopField VS Vtt=0x%x, new=0x%x\n", ptiming->u16V_TotalCount, u16TopField_VS2MVD);)
4365 HAL_WriteByte(SUB_REG(VOP_TF_VS_MVD), LOWBYTE( u16TopField_VS2MVD ));
4366 HAL_WriteByte(SUB_REG((VOP_TF_VS_MVD + 1)), HIGHBYTE( u16TopField_VS2MVD ));
4367
4368 #if SUPPORT_FILED_DB // t/b signal 30 lines forwarding
4369 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_DC2MVD_FLD_SEL);
4370 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_THD_H), 1, REG_MVD_FLD_SEL);
4371
4372 HAL_WriteByte(SUB_REG(VOP_TF_STR_MVD ), LOWBYTE( u16TopField_VS2MVD ));
4373 HAL_WriteByte(SUB_REG(VOP_TF_STR_MVD + 1), HIGHBYTE( u16TopField_VS2MVD ));
4374 HAL_WriteByte(SUB_REG(VOP_BF_STR_MVD ), LOWBYTE( u16BottomField_VS2MVD ));
4375 HAL_WriteByte(SUB_REG(VOP_BF_STR_MVD + 1), HIGHBYTE( u16BottomField_VS2MVD ));
4376 #endif
4377
4378 HAL_WriteRegBit(SUB_REG(VOP_GCLK), 0, VOP_GCLK_MIU_ON);
4379
4380 HAL_WriteRegBit(SUB_REG(VOP_CTRL1), 1, VOP_MVD_VS_MD); //Use new vsync
4381
4382 g_pHalMVOPCtx->bSubNewVSyncMode = FALSE; //restore to original mode
4383 }
4384
4385
4386 // + S3, set default IMG_HSTR, IMG_VSTR0, IMG_VSTR1
4387 #ifdef _SUPPORT_IMG_OFFSET_
4388 HAL_WriteByte(SUB_REG(VOP_IMG_HSTR ), LOWBYTE( ptiming->u16HImg_Start));
4389 HAL_WriteByte(SUB_REG(VOP_IMG_HSTR + 1), HIGHBYTE( ptiming->u16HImg_Start ));
4390 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR0 ), LOWBYTE( ptiming->u16VImg_Start0));
4391 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR0+ 1), HIGHBYTE( ptiming->u16VImg_Start0 ));
4392 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR1 ), LOWBYTE( ptiming->u16VImg_Start1 ));
4393 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR1+ 1), HIGHBYTE( ptiming->u16VImg_Start1 ));
4394 #else
4395 HAL_WriteByte(SUB_REG(VOP_IMG_HSTR ), LOWBYTE( ptiming->u16HActive_Start ));
4396 HAL_WriteByte(SUB_REG(VOP_IMG_HSTR + 1), HIGHBYTE( ptiming->u16HActive_Start ));
4397 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR0 ), LOWBYTE( ptiming->u16VBlank0_End ));
4398 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR0+ 1), HIGHBYTE( ptiming->u16VBlank0_End ));
4399 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR1 ), LOWBYTE( ptiming->u16VBlank1_End ));
4400 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR1+ 1), HIGHBYTE( ptiming->u16VBlank1_End ));
4401 #endif
4402 // select mvop output from frame color(black)
4403 HAL_WriteByte(SUB_REG(VOP_TST_IMG + 1), 0x10);
4404 HAL_WriteByte(SUB_REG(VOP_U_PAT ), 0x80);
4405 HAL_WriteByte(SUB_REG(VOP_U_PAT + 1), 0x80);
4406 // set mvop src to test pattern
4407 regval = HAL_ReadByte(SUB_REG(VOP_TST_IMG));
4408 HAL_WriteByte(SUB_REG(VOP_TST_IMG), 0x02);
4409 // make changed registers take effect
4410 HAL_MVOP_SubLoadReg();
4411
4412 HAL_MVOP_SubSetMIUReqMask(TRUE);
4413 // reset mvop to avoid timing change cause mvop hang-up
4414 HAL_MVOP_SubRst();
4415 HAL_MVOP_SubSetMIUReqMask(FALSE);
4416
4417 // select mvop output from mvd
4418 HAL_WriteByte(SUB_REG(VOP_TST_IMG), 0x00);
4419 HAL_WriteByte(SUB_REG(VOP_TST_IMG), regval);
4420 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), ptiming->bHDuplicate, BIT2);// H pixel duplicate
4421
4422 #if 0
4423 MVOP_DBG(MVOP_PRINTF("\nMVOP SetOutputTiming\n");)
4424 MVOP_DBG(MVOP_PRINTF(" VTot=%u,\t",ptiming->u16V_TotalCount);)
4425 MVOP_DBG(MVOP_PRINTF(" HTot=%u,\t",ptiming->u16H_TotalCount);)
4426 MVOP_DBG(MVOP_PRINTF(" I/P=%u\n",ptiming->bInterlace);)
4427 MVOP_DBG(MVOP_PRINTF(" W=%u,\t",ptiming->u16Width);)
4428 MVOP_DBG(MVOP_PRINTF(" H=%u,\t",ptiming->u16Height);)
4429 MVOP_DBG(MVOP_PRINTF(" FRate=%u,\t",ptiming->u8Framerate);)
4430 MVOP_DBG(MVOP_PRINTF(" HFreq=%u\n",ptiming->u16H_Freq);)
4431 MVOP_DBG(MVOP_PRINTF(" Num=0x%x,\t",ptiming->u16Num);)
4432 MVOP_DBG(MVOP_PRINTF(" Den=0x%x,\t",ptiming->u16Den);)
4433 MVOP_DBG(MVOP_PRINTF(" u16ExpFRate=%u #\n\n", ptiming->u16ExpFrameRate);)
4434 #endif
4435 }
4436
HAL_MVOP_SubSetDCClk(MS_U8 clkNum,MS_BOOL bEnable)4437 void HAL_MVOP_SubSetDCClk(MS_U8 clkNum, MS_BOOL bEnable)
4438 {
4439 MS_ASSERT( (clkNum==0) || (clkNum==1) );
4440 if (clkNum==0)
4441 {
4442 HAL_WriteRegBit(REG_CKG_SUB_DC0, !bEnable, CKG_SUB_DC0_GATED);
4443 }
4444 }
4445
HAL_MVOP_SubSetDCSRAMClk(MS_U8 clkNum,MS_BOOL bEnable)4446 void HAL_MVOP_SubSetDCSRAMClk(MS_U8 clkNum, MS_BOOL bEnable)
4447 {
4448 MS_ASSERT( (clkNum==0) || (clkNum==1) );
4449 if (clkNum==0)
4450 {
4451 HAL_WriteRegBit(REG_CKG_DC_SRAM, !bEnable, CKG_DC1_SRAM);
4452 }
4453 }
4454
HAL_MVOP_SubSetSynClk(MVOP_Timing * ptiming)4455 void HAL_MVOP_SubSetSynClk(MVOP_Timing *ptiming)
4456 {
4457 if (g_pHalMVOPCtx == NULL)
4458 {
4459 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4460 return;
4461 }
4462
4463 if ( g_pHalMVOPCtx->bIs265DV == 1)
4464 {
4465 g_pHalMVOPCtx->bSubEnableFreerunMode = g_pHalMVOPCtx->bEnableFreerunMode;
4466 _bSubEnable60P = _bEnable60P;
4467 _bSubEnable4k2kClk = _bEnable4k2kClk;
4468 }
4469
4470 if(g_pHalMVOPCtx->bSubEnableFreerunMode)
4471 {
4472 MS_U64 u64mpll_clock = MPLL_CLOCK_216 << 27 ; //mvop hw bug, tsp default use 216MHz mpll clock @ maserati
4473 if(HAL_ReadRegBit(REG_CLK_SYN_STC, BIT0) == BIT4) //check stc1 clock use 432 or 216
4474 {
4475 u64mpll_clock = MPLL_CLOCK_432 << 27 ;
4476 }
4477 MS_U64 u64exp_clock = (((MS_U64)ptiming->u16H_TotalCount * (MS_U64)ptiming->u16V_TotalCount * (MS_U64)ptiming->u16ExpFrameRate)/1000);
4478 do_div(u64mpll_clock, u64exp_clock);
4479 MS_U32 u32FreerunClk = (MS_U32)u64mpll_clock;
4480 HAL_MVOP_SubSetFrequency(HALMVOP_FREERUNMODE);
4481 HAL_WriteByte((REG_DC1_FREERUN_CW_L ), LOWBYTE((MS_U16)u32FreerunClk));
4482 HAL_WriteByte((REG_DC1_FREERUN_CW_L+1), HIGHBYTE((MS_U16)u32FreerunClk));
4483 HAL_WriteByte((REG_DC1_FREERUN_CW_H ), LOWBYTE((MS_U16)(u32FreerunClk >> 16)));
4484 HAL_WriteByte((REG_DC1_FREERUN_CW_H+1), HIGHBYTE((MS_U16)(u32FreerunClk >> 16)));
4485 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW);
4486 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW);
4487 }
4488 else if (_bSubEnable60P)
4489 {
4490 //Set DC1 Timing
4491 MS_U32 u32FrameRate = (MS_U32)ptiming->u16ExpFrameRate;
4492 MS_U32 u32VSize = 1024;
4493 MS_U32 u32HSize = ((86400000 / u32FrameRate) * 1000) / u32VSize;
4494
4495 if(u32HSize > 4096)
4496 MVOP_PRINTF("[Warning] xc support u32HSize > 4096 after CL 712830\n");
4497
4498
4499 HAL_MVOP_SubSetFrequency(HAL_MVOP_SubGetMaxFreerunClk());
4500
4501 HAL_WriteRegBit(SUB_REG(VOP_REG_YC422_EN_H), 0, VOP_FRAME_RST); // reg_frame_rst = 0
4502
4503 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), DISABLE, VOP_FSYNC_EN); // frame sync disable
4504 }
4505 else if (_bSubEnable4k2kClk)
4506 {
4507 HAL_MVOP_SubSetFrequency(HAL_MVOP_SubGet4k2kClk());
4508
4509 HAL_WriteRegBit(SUB_REG(VOP_REG_YC422_EN_H), 0, VOP_FRAME_RST); // reg_frame_rst = 0
4510
4511 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), DISABLE, VOP_FSYNC_EN); // frame sync disable
4512 }
4513 else
4514 {
4515 HAL_MVOP_SubSetFrequency(HALMVOP_SYNCMODE);
4516 HAL_WriteByte((REG_DC1_NUM ), LOWBYTE( ptiming->u16Num));
4517 HAL_WriteByte((REG_DC1_NUM+1), HIGHBYTE(ptiming->u16Num));
4518 HAL_WriteByte((REG_DC1_DEN ), LOWBYTE( ptiming->u16Den));
4519 HAL_WriteByte((REG_DC1_DEN+1), HIGHBYTE(ptiming->u16Den));
4520 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_SYNC_CW);
4521 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_SYNC_CW);
4522 }
4523 }
4524
4525
HAL_MVOP_SubSetMonoMode(MS_BOOL bEnable)4526 void HAL_MVOP_SubSetMonoMode(MS_BOOL bEnable)
4527 {
4528 if(bEnable)
4529 {
4530 HAL_WriteByte(SUB_REG(VOP_U_PAT ), 0x80);
4531 HAL_WriteByte(SUB_REG(VOP_U_PAT+1), 0x80);
4532
4533 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH1), 1, BIT1); // Mono mode enable
4534 }
4535 else
4536 {
4537 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH1), 0, BIT1); //Mono mode disable
4538 }
4539 }
4540
4541 /******************************************************************************/
4542 /// Set MVOP for H264 Hardwire Mode
4543 /******************************************************************************/
HAL_MVOP_SubSetH264HardwireMode(void)4544 void HAL_MVOP_SubSetH264HardwireMode(void)
4545 {
4546 // Hardwire mode
4547 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), 0x00);
4548
4549 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4550
4551 //16*32 tile format
4552 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
4553
4554 // SVD mode enable
4555 HAL_WriteByteMask(SUB_REG(VOP_INPUT_SWITCH1), BIT3, BIT2|BIT3);
4556
4557 // set mvop to 64bit interface
4558 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4559
4560 // Only for Monaco: Disable deciding bot by top address + 2
4561 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 0, VOP_FIELD_FROM_ADDR);
4562
4563 // Enable mfdec setting from wb from Manhattan
4564 HAL_WriteRegBit(SUB_REG(VOP_REG_MFDEC_2_L), 1, VOP_MF_FROM_WB);
4565 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 1, VOP_32x32_WB); //32x32 from wb
4566
4567 // H264 use WISHBONE(R2) interface
4568 //HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, VOP_R2_WISHBONE);
4569
4570 // Write trigger
4571 HAL_MVOP_SubLoadReg();
4572 }
4573
HAL_MVOP_SubEnableMVDInterface(MS_BOOL bEnable)4574 void HAL_MVOP_SubEnableMVDInterface(MS_BOOL bEnable)
4575 {
4576 MS_BOOL bMVOPMain2MVD = TRUE;
4577 bMVOPMain2MVD = (bEnable) ? FALSE : TRUE;
4578
4579 //This bit is only valid in main mvop bank.
4580 //Select which mvop interrupt that mvd f/w recieve: 1 for main; 0 for sub.
4581 HAL_WriteByteMask(VOP_INPUT_SWITCH1, bMVOPMain2MVD, VOP_MVD_EN);
4582
4583 //No need to "Write trigger" since HAL_MVOP_SubSetInputMode() will do it later.
4584 //HAL_MVOP_SubLoadReg();
4585 }
4586
4587 /******************************************************************************/
4588 /// Set MVOP for RM Hardwire Mode
4589 /******************************************************************************/
HAL_MVOP_SubSetRMHardwireMode(void)4590 void HAL_MVOP_SubSetRMHardwireMode(void)
4591 {
4592 HAL_MVOP_SubSetH264HardwireMode();
4593 }
4594
4595 /******************************************************************************/
4596 /// Set MVOP for JPEG Hardwire Mode
4597 /******************************************************************************/
HAL_MVOP_SubSetJpegHardwireMode(void)4598 void HAL_MVOP_SubSetJpegHardwireMode(void)
4599 {
4600 MS_U8 regval = 0x00;
4601
4602 //16*32 tile format
4603 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
4604
4605 // set mvop to 64bit interface
4606 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4607
4608 regval |= 0x80; // packmode
4609 regval |= 0x20; // Dram Rd Contd
4610 regval |= 0x10; // reg_img422
4611 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), regval);
4612 /* There is no hardwire:mvd2dc_img422/hvd2dc_img422 0x20[4] in sub mvop*/
4613 HAL_WriteByteMask(SUB_REG(VOP_INFO_FROM_CODEC_L), 0, VOP_INFO_FROM_CODEC_422_FMT);
4614 g_pHalMVOPCtx->bSubIs422 = 1;
4615 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 0, VOP_420_BW_SAVE);
4616 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
4617
4618 // Write trigger
4619 HAL_MVOP_SubLoadReg();
4620 }
4621 /******************************************************************************/
4622 /// Set MVOP for EVD Hardwire Mode
4623 /******************************************************************************/
HAL_MVOP_SubSetEVDHardwireMode(MS_U16 u16ECOVersion)4624 void HAL_MVOP_SubSetEVDHardwireMode(MS_U16 u16ECOVersion)
4625 {
4626 UNUSED(u16ECOVersion);
4627
4628 // Hardwire mode
4629 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), 0x00);
4630
4631 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4632
4633 //16*32 tile format
4634 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
4635
4636 // EVD use HVD interface
4637 //HAL_WriteByteMask(SUB_REG(VOP_INPUT_SWITCH1), BIT3, BIT2|BIT3);
4638
4639 // EVD mode enable
4640 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, EVD_ENABLE);
4641
4642 // set mvop to 128bit_i128 interface
4643 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4644
4645 // set evd flag for interlace mode setting
4646 g_pHalMVOPCtx->bSubIsH265 = 1;
4647
4648 // Enable mfdec setting from wb
4649 HAL_WriteRegBit(SUB_REG(VOP_REG_MFDEC_2_L), 1, VOP_MF_FROM_WB);
4650
4651 // 10 bits from wb
4652 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), 1, VOP_INFO_FROM_CODEC_10BIT);
4653
4654 HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), 0, VOP_LSB_REQ_MASK); //10 bits bw control by vdec fw
4655
4656 // Write trigger
4657 HAL_MVOP_SubLoadReg();
4658 }
4659
4660 /******************************************************************************/
4661 /// Set MVOP for VP9 Hardwire Mode
4662 /******************************************************************************/
HAL_MVOP_SubSetVP9HardwireMode(void)4663 void HAL_MVOP_SubSetVP9HardwireMode(void)
4664 {
4665 // Hardwire mode
4666 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), 0x00);
4667
4668 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4669
4670 //16*32 tile format
4671 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
4672
4673 // Enable VP9 dram continue mode
4674 //HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 1, VOP_DRAM_RD_MODE);
4675
4676 // set mvop to 128bit_i128 interface
4677 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4678
4679 // Enable mfdec setting from wb
4680 HAL_WriteRegBit(SUB_REG(VOP_REG_MFDEC_2_L), 1, VOP_MF_FROM_WB);
4681
4682 // EVD mode enable
4683 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, EVD_ENABLE);
4684
4685 // 10 bits from wb
4686 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), 1, VOP_INFO_FROM_CODEC_10BIT);
4687
4688 HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), 0, VOP_LSB_REQ_MASK); //10 bits bw control by vdec fw
4689
4690 // Write trigger
4691 HAL_MVOP_LoadReg();
4692
4693 }
4694
4695
4696 ///Enable 3D L/R dual buffer mode
HAL_MVOP_SubEnable3DLR(MS_BOOL bEnable)4697 MS_BOOL HAL_MVOP_SubEnable3DLR(MS_BOOL bEnable)
4698 {
4699 if (g_pHalMVOPCtx == NULL)
4700 {
4701 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4702 return FALSE;
4703 }
4704 HAL_WriteRegBit(SUB_REG(VOP_MULTI_WIN_CFG0), bEnable, VOP_LR_BUF_MODE);
4705 g_pHalMVOPCtx->bSub3DLRMode = bEnable;
4706 if(bEnable)
4707 {
4708 //only for monaco: do not wait for data ready.
4709 HAL_WriteByteMask(SUB_REG(VOP_NOT_WAIT_READ_DATA), 2, VOP_NOT_WAIT_RDLAT);
4710 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
4711 }
4712 else
4713 {
4714 HAL_WriteByteMask(SUB_REG(VOP_NOT_WAIT_READ_DATA), 0, VOP_NOT_WAIT_RDLAT);
4715 }
4716 return TRUE;
4717 }
4718
4719 ///Get if 3D L/R mode is enabled
HAL_MVOP_SubGet3DLRMode(void)4720 MS_BOOL HAL_MVOP_SubGet3DLRMode(void)
4721 {
4722 if (g_pHalMVOPCtx == NULL)
4723 {
4724 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4725 return FALSE;
4726 }
4727 return g_pHalMVOPCtx->bSub3DLRMode;
4728 }
4729
HAL_MVOP_SubGetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters * pMvopTimingInfo)4730 MS_BOOL HAL_MVOP_SubGetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters *pMvopTimingInfo)
4731 {
4732 if(NULL == pMvopTimingInfo)
4733 {
4734 MVOP_PRINTF("HAL_MVOP_SubGetTimingInfoFromRegisters():pMvopTimingInfo is NULL\n");
4735 return FALSE;
4736 }
4737 if(HAL_MVOP_SubGetEnableState() == FALSE)
4738 {
4739 MVOP_PRINTF("MVOP is not enabled!\n");
4740 pMvopTimingInfo->bEnabled = FALSE;
4741 return FALSE;
4742 }
4743 pMvopTimingInfo->bEnabled = TRUE;
4744 pMvopTimingInfo->u16H_TotalCount = (HAL_ReadByte(SUB_REG(VOP_FRAME_HCOUNT + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_FRAME_HCOUNT)));
4745 pMvopTimingInfo->u16V_TotalCount = (HAL_ReadByte(SUB_REG(VOP_FRAME_VCOUNT + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_FRAME_VCOUNT)));
4746 pMvopTimingInfo->u16VBlank0_Start = (HAL_ReadByte(SUB_REG(VOP_VB0_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_VB0_STR)));
4747 pMvopTimingInfo->u16VBlank0_End = (HAL_ReadByte(SUB_REG(VOP_VB0_END + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_VB0_END)));
4748 pMvopTimingInfo->u16VBlank1_Start = (HAL_ReadByte(SUB_REG(VOP_VB1_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_VB1_STR)));
4749 pMvopTimingInfo->u16VBlank1_End = (HAL_ReadByte(SUB_REG(VOP_VB1_END + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_VB1_END)));
4750 pMvopTimingInfo->u16TopField_Start = (HAL_ReadByte(SUB_REG(VOP_TF_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_TF_STR)));
4751 pMvopTimingInfo->u16BottomField_Start = (HAL_ReadByte(SUB_REG(VOP_BF_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_BF_STR)));
4752 pMvopTimingInfo->u16HActive_Start = (HAL_ReadByte(SUB_REG(VOP_HACT_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_HACT_STR)));
4753 pMvopTimingInfo->u16TopField_VS = (HAL_ReadByte(SUB_REG(VOP_TF_VS + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_TF_VS)));
4754 pMvopTimingInfo->u16BottomField_VS = (HAL_ReadByte(SUB_REG(VOP_BF_VS + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_BF_VS)));
4755 pMvopTimingInfo->bInterlace = (HAL_ReadRegBit(SUB_REG(VOP_CTRL0), BIT7) == BIT7);
4756 return TRUE;
4757 }
4758
HAL_MVOP_SubSetYUVBaseAdd(MS_PHY u32YOffset,MS_PHY u32UVOffset,MS_BOOL bProgressive,MS_BOOL b422pack)4759 void HAL_MVOP_SubSetYUVBaseAdd(MS_PHY u32YOffset, MS_PHY u32UVOffset, MS_BOOL bProgressive, MS_BOOL b422pack)
4760 {
4761 MS_PHY u64tmp = 0;
4762
4763 if (g_pHalMVOPCtx == NULL)
4764 {
4765 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4766 return;
4767 }
4768 // Y offset
4769 u64tmp = u32YOffset >> 3;
4770 if ( !bProgressive )
4771 { //Refine Y offset for interlace repeat bottom field
4772 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eSubRepeatField)
4773 {
4774 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eSubRepeatField);
4775 u64tmp += 2;
4776 }
4777 else
4778 {
4779 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eSubRepeatField);
4780 }
4781 }
4782 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L), u64tmp & 0xff);
4783 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L+1), (u64tmp >> 8) & 0xff);
4784 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L+2), (u64tmp >> 16) & 0xff);
4785 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
4786
4787 if (!bProgressive )
4788 { //Y offset of bottom field if interlace
4789 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L), u64tmp & 0xff);
4790 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L+1), (u64tmp >> 8) & 0xff);
4791 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L+2), (u64tmp >> 16) & 0xff);
4792 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
4793 }
4794
4795 if (b422pack)
4796 {
4797 if (HAL_ReadRegBit(SUB_REG(VOP_MIU_IF), VOP_MIU_128B_I64) != VOP_MIU_128B_I64) //128-bit
4798 {
4799 u32UVOffset = u32YOffset + 16; //add 16 for 128bit; add 8 for 64bit
4800 }
4801 else //64-bit
4802 {
4803 u32UVOffset = u32YOffset + 8; //add 16 for 128bit; add 8 for 64bit
4804 }
4805 }
4806 // UV offset
4807 u64tmp = u32UVOffset >> 3;
4808 if( !bProgressive )
4809 { //Refine UV offset for interlace repeat bottom field
4810 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eSubRepeatField)
4811 {
4812 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eSubRepeatField);
4813 u64tmp += 2;
4814 }
4815 else
4816 {
4817 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eSubRepeatField);
4818 }
4819 }
4820 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L), u64tmp & 0xff);
4821 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
4822 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L+2), (u64tmp >> 16) & 0xff);
4823 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
4824
4825 if( !bProgressive )
4826 { //UV offset of bottom field if interlace
4827 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L), u64tmp & 0xff);
4828 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
4829 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L+2), (u64tmp >> 16) & 0xff);
4830 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
4831 }
4832
4833 return;
4834 }
4835
HAL_MVOP_SubGetYBaseAdd(void)4836 MS_PHY HAL_MVOP_SubGetYBaseAdd(void)
4837 {
4838 MS_PHY u64YOffset;
4839 u64YOffset = HAL_ReadByte(SUB_REG(VOP_JPG_YSTR0_L))&0xff;
4840 u64YOffset |=((HAL_ReadByte(SUB_REG(VOP_JPG_YSTR0_L+1))<<8)&0xff00);
4841 u64YOffset |=((HAL_ReadByte(SUB_REG(VOP_JPG_YSTR0_L+2))<<16)&0xff0000);
4842 u64YOffset |= ((HAL_ReadByte(SUB_REG(VOP_JPG_YSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
4843 return u64YOffset;
4844 }
4845
HAL_MVOP_SubGetUVBaseAdd(void)4846 MS_PHY HAL_MVOP_SubGetUVBaseAdd(void)
4847 {
4848 MS_PHY u64UVOffset;
4849 u64UVOffset = HAL_ReadByte(SUB_REG(VOP_JPG_UVSTR0_L))&0xff;
4850 u64UVOffset |=((HAL_ReadByte(SUB_REG(VOP_JPG_UVSTR0_L+1))<<8)&0xff00);
4851 u64UVOffset |=((HAL_ReadByte(SUB_REG(VOP_JPG_UVSTR0_L+2))<<16)&0xff0000);
4852 u64UVOffset |= ((HAL_ReadByte(SUB_REG(VOP_JPG_UVSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
4853 return u64UVOffset;
4854 }
4855
4856 /******************************************************************************/
4857 /// Set MVOP Saving BW Mode
4858 /// @ Napoli this command should be set after MDrv_MVOP_SubSetOutputCfg
4859 /******************************************************************************/
HAL_MVOP_SubSet420BWSaveMode(MS_BOOL bEnable)4860 MS_BOOL HAL_MVOP_SubSet420BWSaveMode(MS_BOOL bEnable)
4861 {
4862 MS_BOOL bValue = FALSE;
4863
4864 //hw limtation: 3DLA/3DSBS/422/p mode in, i mode out/i mode in, p mode out(only need to check in MCU mode)
4865 bValue = (g_pHalMVOPCtx->bSub3DLRAltSBSOutput || g_pHalMVOPCtx->bSub3DLRAltOutput /*|| g_pHalMVOPCtx->bSub3DLRMode*/ || g_pHalMVOPCtx->bSubIs422 );
4866
4867 if(bValue)
4868 {
4869 MVOP_DBG(MVOP_PRINTF("%s Hit the limitation of saving bw, disable BW Saving mode\n", __FUNCTION__);)
4870 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 0, VOP_420_BW_SAVE);
4871 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
4872 HAL_MVOP_SubLoadReg();
4873 return FALSE;
4874 }
4875 else
4876 {
4877 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), bEnable, VOP_420_BW_SAVE);
4878 if( g_pHalMVOPCtx->bSub3DLRMode == FALSE)
4879 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), bEnable, VOP_420_BW_SAVE_EX);
4880 else
4881 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
4882
4883 HAL_MVOP_SubLoadReg();
4884 return TRUE;
4885 }
4886 }
4887
HAL_MVOP_SubSetEVDYUVBaseAdd(MVOP_EVDBaseAddInput * stEVDBaseAddInfo)4888 MS_BOOL HAL_MVOP_SubSetEVDYUVBaseAdd(MVOP_EVDBaseAddInput *stEVDBaseAddInfo)
4889 {
4890 //----------------------------------------------------
4891 // Set MSB YUV Address
4892 //----------------------------------------------------
4893
4894 MS_PHY u64tmp = 0;
4895
4896 if (g_pHalMVOPCtx == NULL)
4897 {
4898 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4899 return FALSE;
4900 }
4901 // Y offset
4902 u64tmp = stEVDBaseAddInfo->u32MSBYOffset >> 3;
4903 if ( !stEVDBaseAddInfo->bProgressive)
4904 { //Refine Y offset for interlace repeat bottom field
4905 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
4906 {
4907 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
4908 u64tmp += 2;
4909 }
4910 else
4911 {
4912 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
4913 }
4914 }
4915 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L), u64tmp & 0xff);
4916 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L+1), (u64tmp >> 8) & 0xff);
4917 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_H), (u64tmp >> 16) & 0xff);
4918 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
4919
4920 if (!stEVDBaseAddInfo->bProgressive )
4921 { //Y offset of bottom field if interlace
4922 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L), u64tmp & 0xff);
4923 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L+1), (u64tmp >> 8) & 0xff);
4924 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_H), (u64tmp >> 16) & 0xff);
4925 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
4926 }
4927
4928 if (stEVDBaseAddInfo->b422Pack)
4929 {
4930 stEVDBaseAddInfo->u32MSBUVOffset = stEVDBaseAddInfo->u32MSBYOffset + 16; //add 16 for 128bit; add 8 for 64bit
4931 }
4932 // UV offset
4933 u64tmp = stEVDBaseAddInfo->u32MSBUVOffset >> 3;
4934 if( !stEVDBaseAddInfo->bProgressive )
4935 { //Refine UV offset for interlace repeat bottom field
4936 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
4937 {
4938 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
4939 u64tmp += 2;
4940 }
4941 else
4942 {
4943 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
4944 }
4945 }
4946 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L), u64tmp & 0xff);
4947 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
4948 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_H), (u64tmp >> 16) & 0xff);
4949 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
4950
4951 if( !stEVDBaseAddInfo->bProgressive )
4952 { //UV offset of bottom field if interlace
4953 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L), u64tmp & 0xff);
4954 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
4955 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_H), (u64tmp >> 16) & 0xff);
4956 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
4957 }
4958
4959 //----------------------------------------------------
4960 // Set MSB YUV Address
4961 //----------------------------------------------------
4962 if(stEVDBaseAddInfo->bEnLSB)
4963 {
4964 //Enable LSB
4965 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 1, VOP_EVD_10B_Y_EN);
4966 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 1, VOP_EVD_10B_UV_EN);
4967 HAL_WriteRegBit(SUB_REG(VOP_REG_MASK), 0, VOP_LSB_REQ_MASK);
4968
4969 // Y offset
4970 u64tmp = stEVDBaseAddInfo->u32LSBYOffset >> 3;
4971 if ( !stEVDBaseAddInfo->bProgressive)
4972 { //Refine Y offset for interlace repeat bottom field
4973 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
4974 {
4975 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
4976 u64tmp += 2;
4977 }
4978 else
4979 {
4980 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
4981 }
4982 }
4983 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR0_L), u64tmp & 0xff);
4984 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR0_L+1), (u64tmp >> 8) & 0xff);
4985 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR0_L), (u64tmp >> 16) & 0xff);
4986 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR0_L+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
4987
4988 if (!stEVDBaseAddInfo->bProgressive )
4989 { //Y offset of bottom field if interlace
4990 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR1_L), u64tmp & 0xff);
4991 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR1_L+1), (u64tmp >> 8) & 0xff);
4992 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR1_H), (u64tmp >> 16) & 0xff);
4993 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
4994 }
4995
4996 if (stEVDBaseAddInfo->b422Pack)
4997 {
4998 stEVDBaseAddInfo->u32LSBUVOffset = stEVDBaseAddInfo->u32LSBYOffset + 16; //add 16 for 128bit; add 8 for 64bit
4999 }
5000 // UV offset
5001 u64tmp = stEVDBaseAddInfo->u32LSBUVOffset >> 3;
5002 if( !stEVDBaseAddInfo->bProgressive )
5003 { //Refine UV offset for interlace repeat bottom field
5004 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
5005 {
5006 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5007 u64tmp += 2;
5008 }
5009 else
5010 {
5011 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5012 }
5013 }
5014 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR0_L), u64tmp & 0xff);
5015 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
5016 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR0_H), (u64tmp >> 16) & 0xff);
5017 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5018
5019 if( !stEVDBaseAddInfo->bProgressive )
5020 { //UV offset of bottom field if interlace
5021 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR1_L), u64tmp & 0xff);
5022 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
5023 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR1_H), (u64tmp >> 16) & 0xff);
5024 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5025 }
5026 }
5027
5028 return TRUE;
5029 }
5030
HAL_MVOP_SubCheckSTCCW(void)5031 MS_BOOL HAL_MVOP_SubCheckSTCCW(void)
5032 {
5033 MS_U16 u16STC_CW_L = 0;
5034 MS_U16 u16STC_CW_H = 0;
5035 MS_BOOL u16STC_CW_SEL = 0;
5036 MS_BOOL u16TSP_CLK_EN = 0;
5037
5038 u16STC_CW_L = HAL_Read2Byte(REG_STC1_CW_L)&0xffff;
5039 u16STC_CW_H = HAL_Read2Byte(REG_STC1_CW_H)&0xffff;
5040
5041 u16STC_CW_SEL = (HAL_ReadRegBit(REG_STC_CW_SLE_H, BIT1) == BIT1);
5042 u16TSP_CLK_EN = !(HAL_ReadRegBit(REG_TSP_CLK, BIT0) == BIT0);
5043
5044 if((((u16STC_CW_L || u16STC_CW_H) == 0) && (u16STC_CW_SEL == 0)) || ((u16STC_CW_SEL == 1) && (u16TSP_CLK_EN == 0)))
5045 return FALSE;
5046 else
5047 return TRUE;
5048 }
5049
HAL_MVOP_SubSetVSyncMode(MS_U8 u8Mode)5050 void HAL_MVOP_SubSetVSyncMode(MS_U8 u8Mode)
5051 {
5052 if (g_pHalMVOPCtx == NULL)
5053 {
5054 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5055 return;
5056 }
5057 if (1==u8Mode)
5058 {
5059 g_pHalMVOPCtx->bSubNewVSyncMode = TRUE;
5060 }
5061 else
5062 {
5063 g_pHalMVOPCtx->bSubNewVSyncMode = FALSE;
5064 }
5065 }
5066
HAL_MVOP_SubSet3DLRAltOutput_VHalfScaling(MS_BOOL bEnable)5067 MS_BOOL HAL_MVOP_SubSet3DLRAltOutput_VHalfScaling(MS_BOOL bEnable)
5068 {
5069 MS_BOOL bEnDualBuff = bEnable ? ENABLE : DISABLE; //enable dual buffer
5070 MS_BOOL bEnSWDualBuff = bEnable ? DISABLE : ENABLE; //buffer controlled by HK instead of FW
5071 MS_BOOL bEnMirrMaskBase = bEnable ? DISABLE : ENABLE; //do not mask LSB
5072 MS_BOOL bEnHwFldBase = bEnable ? DISABLE : ENABLE; //hardware calculate field jump base address
5073 if (g_pHalMVOPCtx == NULL)
5074 {
5075 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5076 return FALSE;
5077 }
5078 //Set 0x27[2] = 1 (enable SW dual buffer mode)
5079 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), bEnDualBuff, VOP_BUF_DUAL);
5080
5081 //Set 0x38[8] = 0 (use SW dual buffer mode)
5082 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), bEnSWDualBuff, VOP_INFO_FROM_CODEC_DUAL_BUFF);
5083
5084 //Set 0x3b[7] = 0 (use MVD/HVD firmware send base)
5085 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnMirrMaskBase, VOP_MASK_BASE_LSB);
5086
5087 //Set 0x3b[5] = 0 (hardware calculate field jump base address)
5088 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnHwFldBase, VOP_HW_FLD_BASE);
5089 g_pHalMVOPCtx->bSub3DLRAltOutput = bEnable;
5090 return TRUE;
5091 }
5092
HAL_MVOP_SubSet3DLRAltOutput(MS_BOOL bEnable)5093 MS_BOOL HAL_MVOP_SubSet3DLRAltOutput(MS_BOOL bEnable)
5094 {
5095 //Set 0x3C[2] = 1 (enable 3D L/R dual buffer line alternative output)
5096 //it works when 0x3C[0] = 1
5097 HAL_WriteRegBit(SUB_REG(VOP_MULTI_WIN_CFG0), bEnable, VOP_LR_LA_OUT);
5098 // bw saving not support: LA/SBS
5099 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 0, VOP_420_BW_SAVE);
5100 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
5101 HAL_MVOP_LoadReg();
5102
5103 g_pHalMVOPCtx->bSub3DLRAltOutput = bEnable;
5104 return TRUE;
5105 }
5106
HAL_MVOP_SubSet3DLRAltSBSOutput(MS_BOOL bEnable)5107 MS_BOOL HAL_MVOP_SubSet3DLRAltSBSOutput(MS_BOOL bEnable)
5108 {
5109 //it works when 0x3C[0] = 1 and 0x3C[2] = 1
5110 //Set 0x3C[3] = 1 (3D L/R line alternative read, side-by-side output)
5111 HAL_WriteRegBit(SUB_REG(VOP_MULTI_WIN_CFG0), bEnable, VOP_LR_LA2SBS_OUT);
5112 g_pHalMVOPCtx->bSub3DLRAltSBSOutput = bEnable;
5113 return TRUE;
5114 }
5115
HAL_MVOP_SubGet3DLRAltOutput(void)5116 MS_BOOL HAL_MVOP_SubGet3DLRAltOutput(void)
5117 {
5118 if (g_pHalMVOPCtx == NULL)
5119 {
5120 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5121 return FALSE;
5122 }
5123 return g_pHalMVOPCtx->bSub3DLRAltOutput;
5124 }
5125
HAL_MVOP_SubGet3DLRAltSBSOutput(void)5126 MS_BOOL HAL_MVOP_SubGet3DLRAltSBSOutput(void)
5127 {
5128 return g_pHalMVOPCtx->bSub3DLRAltSBSOutput;
5129 }
5130
HAL_MVOP_SubGetOutput3DType(void)5131 EN_MVOP_Output_3D_TYPE HAL_MVOP_SubGetOutput3DType(void)
5132 {
5133 EN_MVOP_Output_3D_TYPE en3DType = E_MVOP_OUTPUT_3D_NONE;
5134 if(g_pHalMVOPCtx->bSub3DLRMode)
5135 {
5136 if(g_pHalMVOPCtx->bSub3DLRAltSBSOutput)
5137 {
5138 en3DType = E_MVOP_OUTPUT_3D_SBS;
5139 }
5140 else
5141 {
5142 en3DType = E_MVOP_OUTPUT_3D_TB;
5143 }
5144 }
5145 else if(g_pHalMVOPCtx->bSub3DLRAltOutput)
5146 {
5147 en3DType = E_MVOP_OUTPUT_3D_LA;
5148 }
5149 return en3DType;
5150 }
5151 #endif
5152
5153
5154 #define MVOP_INT_UF BIT0
5155 #define MVOP_INT_OF BIT1
5156 #define MVOP_INT_VSYNC BIT2
5157 #define MVOP_INT_HSYNC BIT3
5158 #define MVOP_INT_RDY BIT4
5159 #define MVOP_INT_FLD BIT5
5160 #define MVOP_INT_ALL (BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
5161
5162 const MS_U16 u16MvopRegBase[2] = { MVOP_REG_BASE, MVOP_SUB_REG_BASE};
5163 #define MAP_REG(_id, _reg) ((_reg) - MVOP_REG_BASE + u16MvopRegBase[(_id)])
5164
HAL_MVOP_IntEnableMask(MVOP_DevID eID,MS_U8 eIntType)5165 MS_BOOL HAL_MVOP_IntEnableMask(MVOP_DevID eID, MS_U8 eIntType)
5166 {
5167 MS_BOOL bRet = TRUE;
5168 MS_U16 u16Reg = MAP_REG( eID, VOP_INT_MASK);
5169 MS_U8 u8Mask = 0;
5170
5171 u8Mask = HAL_ReadByte(u16Reg);
5172
5173 if (E_MVOP_INT_NONE != eIntType)
5174 {
5175 u8Mask = (E_MVOP_INT_VSYNC == (eIntType&E_MVOP_INT_VSYNC)) ?
5176 (u8Mask & ~MVOP_INT_VSYNC) : (u8Mask);
5177 u8Mask = (E_MVOP_INT_HSYNC == (eIntType&E_MVOP_INT_HSYNC)) ?
5178 (u8Mask & ~MVOP_INT_HSYNC) : (u8Mask);
5179 u8Mask = (E_MVOP_INT_FDCHNG == (eIntType&E_MVOP_INT_FDCHNG)) ?
5180 (u8Mask & ~MVOP_INT_FLD) : (u8Mask);
5181 u8Mask = (E_MVOP_INT_RDY == (eIntType&E_MVOP_INT_RDY)) ?
5182 (u8Mask & ~MVOP_INT_RDY) : (u8Mask);
5183 u8Mask = (E_MVOP_INT_BUFF_UF == (eIntType&E_MVOP_INT_BUFF_UF)) ?
5184 (u8Mask & ~MVOP_INT_UF) : (u8Mask);
5185 u8Mask = (E_MVOP_INT_BUFF_OF == (eIntType&E_MVOP_INT_BUFF_OF)) ?
5186 (u8Mask & ~MVOP_INT_OF) : (u8Mask);
5187 }
5188 else //mask all
5189 {
5190 u8Mask |= MVOP_INT_ALL;
5191 }
5192
5193 //MVOP_PRINTF("u8Mask %x ", u8Mask);
5194 HAL_WriteByteMask(u16Reg, u8Mask, MVOP_INT_ALL);
5195 //u8Mask = HAL_ReadByte(u16Reg);
5196 //MVOP_PRINTF("==> %x \n", u8Mask);
5197 return bRet;
5198 }
5199
HAL_MVOP_IntGetStatus(MVOP_DevID eID)5200 MS_U8 HAL_MVOP_IntGetStatus(MVOP_DevID eID)
5201 {
5202 MS_U8 u8IntVal = 0;
5203 MS_U8 u8IntType = E_MVOP_INT_NONE;
5204 MS_U16 u16Reg = MAP_REG(eID, (VOP_INT_MASK+1));
5205
5206 u8IntVal = HAL_ReadByte(u16Reg) & MVOP_INT_ALL;
5207 //MVOP_PRINTF("u8IntVal %x\n", u8IntVal);
5208 if ((u8IntVal & MVOP_INT_VSYNC) == MVOP_INT_VSYNC)
5209 {
5210 u8IntType |= E_MVOP_INT_VSYNC;
5211 }
5212 if ((u8IntVal & MVOP_INT_HSYNC) == MVOP_INT_HSYNC)
5213 {
5214 u8IntType |= E_MVOP_INT_HSYNC;
5215 }
5216 if ((u8IntVal & MVOP_INT_FLD) == MVOP_INT_FLD)
5217 {
5218 u8IntType |= E_MVOP_INT_FDCHNG;
5219 }
5220 if ((u8IntVal & MVOP_INT_RDY) == MVOP_INT_RDY)
5221 {
5222 u8IntType |= E_MVOP_INT_RDY;
5223 }
5224 if ((u8IntVal & MVOP_INT_UF) == MVOP_INT_UF)
5225 {
5226 u8IntType |= E_MVOP_INT_BUFF_UF;
5227 }
5228 if ((u8IntVal & MVOP_INT_OF) == MVOP_INT_OF)
5229 {
5230 u8IntType |= E_MVOP_INT_BUFF_OF;
5231 }
5232 return u8IntType;
5233 }
5234