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Searched refs:REG_PWM_BASE (Results 1 – 25 of 45) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/pwm/hal/kano/pwm/
H A DregPWM.h110 #define REG_PWM_BASE 0x3200 macro
112 #define REG_PWM_GRP0_CLK_GATE_EN (REG_PWM_BASE + 0x01*2) //bit0
113 #define REG_PWM_GRP1_CLK_GATE_EN (REG_PWM_BASE + 0x01*2) //bit1
114 #define REG_PWM_GRP2_CLK_GATE_EN (REG_PWM_BASE + 0x01*2) //bit2
116 #define REG_PWM0_PERIOD (REG_PWM_BASE + 0x02*2) //bit0~15
117 #define REG_PWM1_PERIOD (REG_PWM_BASE + 0x05*2) //bit0~15
118 #define REG_PWM2_PERIOD (REG_PWM_BASE + 0x08*2) //bit0~15
119 #define REG_PWM3_PERIOD (REG_PWM_BASE + 0x0B*2) //bit0~15
120 #define REG_PWM4_PERIOD (REG_PWM_BASE + 0x0E*2) //bit0~15
121 #define REG_PWM5_PERIOD (REG_PWM_BASE + 0x11*2) //bit0~15
[all …]
/utopia/UTPA2-700.0.x/modules/pwm/hal/k6/pwm/
H A DregPWM.h110 #define REG_PWM_BASE 0x3200 macro
112 #define REG_PWM_GRP0_CLK_GATE_EN (REG_PWM_BASE + 0x01*2) //bit0
113 #define REG_PWM_GRP1_CLK_GATE_EN (REG_PWM_BASE + 0x01*2) //bit1
114 #define REG_PWM_GRP2_CLK_GATE_EN (REG_PWM_BASE + 0x01*2) //bit2
116 #define REG_PWM0_PERIOD (REG_PWM_BASE + 0x02*2) //bit0~15
117 #define REG_PWM1_PERIOD (REG_PWM_BASE + 0x05*2) //bit0~15
118 #define REG_PWM2_PERIOD (REG_PWM_BASE + 0x08*2) //bit0~15
119 #define REG_PWM3_PERIOD (REG_PWM_BASE + 0x0B*2) //bit0~15
120 #define REG_PWM4_PERIOD (REG_PWM_BASE + 0x0E*2) //bit0~15
121 #define REG_PWM5_PERIOD (REG_PWM_BASE + 0x11*2) //bit0~15
[all …]
/utopia/UTPA2-700.0.x/modules/pwm/hal/k6lite/pwm/
H A DregPWM.h110 #define REG_PWM_BASE 0x3200 macro
112 #define REG_PWM_GRP0_CLK_GATE_EN (REG_PWM_BASE + 0x01*2) //bit0
113 #define REG_PWM_GRP1_CLK_GATE_EN (REG_PWM_BASE + 0x01*2) //bit1
114 #define REG_PWM_GRP2_CLK_GATE_EN (REG_PWM_BASE + 0x01*2) //bit2
116 #define REG_PWM0_PERIOD (REG_PWM_BASE + 0x02*2) //bit0~15
117 #define REG_PWM1_PERIOD (REG_PWM_BASE + 0x05*2) //bit0~15
118 #define REG_PWM2_PERIOD (REG_PWM_BASE + 0x08*2) //bit0~15
119 #define REG_PWM3_PERIOD (REG_PWM_BASE + 0x0B*2) //bit0~15
120 #define REG_PWM4_PERIOD (REG_PWM_BASE + 0x0E*2) //bit0~15
121 #define REG_PWM5_PERIOD (REG_PWM_BASE + 0x11*2) //bit0~15
[all …]
/utopia/UTPA2-700.0.x/modules/pwm/hal/curry/pwm/
H A DregPWM.h110 #define REG_PWM_BASE 0x3200 macro
112 #define REG_PWM_GRP0_CLK_GATE_EN (REG_PWM_BASE + 0x01*2) //bit0
113 #define REG_PWM_GRP1_CLK_GATE_EN (REG_PWM_BASE + 0x01*2) //bit1
114 #define REG_PWM_GRP2_CLK_GATE_EN (REG_PWM_BASE + 0x01*2) //bit2
116 #define REG_PWM0_PERIOD (REG_PWM_BASE + 0x02*2) //bit0~15
117 #define REG_PWM1_PERIOD (REG_PWM_BASE + 0x05*2) //bit0~15
118 #define REG_PWM2_PERIOD (REG_PWM_BASE + 0x08*2) //bit0~15
119 #define REG_PWM3_PERIOD (REG_PWM_BASE + 0x0B*2) //bit0~15
120 #define REG_PWM4_PERIOD (REG_PWM_BASE + 0x0E*2) //bit0~15
121 #define REG_PWM5_PERIOD (REG_PWM_BASE + 0x11*2) //bit0~15
[all …]
/utopia/UTPA2-700.0.x/modules/pwm/hal/mustang/pwm/
H A DhalPWM.c113 #define HAL_PWM_ReadByte(addr) READ_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
114 #define HAL_PWM_Read2Byte(addr) READ_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<…
116 #define HAL_PWM_WriteByte(addr, val) WRITE_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<…
117 #define HAL_PWM_Write2Byte(addr, val) WRITE_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)…
118 #define HAL_PWM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_MapBase + REG_PWM_BASE) + ((…
H A DregPWM.h109 #define REG_PWM_BASE (0x6400) macro
/utopia/UTPA2-700.0.x/modules/pwm/hal/maldives/pwm/
H A DhalPWM.c113 #define HAL_PWM_ReadByte(addr) READ_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
114 #define HAL_PWM_Read2Byte(addr) READ_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<…
116 #define HAL_PWM_WriteByte(addr, val) WRITE_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<…
117 #define HAL_PWM_Write2Byte(addr, val) WRITE_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)…
118 #define HAL_PWM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_MapBase + REG_PWM_BASE) + ((…
H A DregPWM.h105 #define REG_PWM_BASE (0x6400) macro
/utopia/UTPA2-700.0.x/modules/pwm/hal/macan/pwm/
H A DhalPWM.c127 #define HAL_PWM_ReadByte(addr) READ_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
128 #define HAL_PWM_Read2Byte(addr) READ_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
130 #define HAL_PWM_WriteByte(addr, val) WRITE_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2),…
131 #define HAL_PWM_Write2Byte(addr, val) WRITE_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2…
132 #define HAL_PWM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_MapBase + REG_PWM_BASE) + ((add…
H A DregPWM.h117 #define REG_PWM_BASE (0x7E800) macro
/utopia/UTPA2-700.0.x/modules/pwm/hal/M7621/pwm/
H A DhalPWM.c127 #define HAL_PWM_ReadByte(addr) READ_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
128 #define HAL_PWM_Read2Byte(addr) READ_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
130 #define HAL_PWM_WriteByte(addr, val) WRITE_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2),…
131 #define HAL_PWM_Write2Byte(addr, val) WRITE_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2…
132 #define HAL_PWM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_MapBase + REG_PWM_BASE) + ((add…
H A DregPWM.h117 #define REG_PWM_BASE (0x7E800) macro
/utopia/UTPA2-700.0.x/modules/pwm/hal/maserati/pwm/
H A DhalPWM.c127 #define HAL_PWM_ReadByte(addr) READ_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
128 #define HAL_PWM_Read2Byte(addr) READ_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
130 #define HAL_PWM_WriteByte(addr, val) WRITE_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2),…
131 #define HAL_PWM_Write2Byte(addr, val) WRITE_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2…
132 #define HAL_PWM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_MapBase + REG_PWM_BASE) + ((add…
/utopia/UTPA2-700.0.x/modules/pwm/hal/M7821/pwm/
H A DhalPWM.c127 #define HAL_PWM_ReadByte(addr) READ_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
128 #define HAL_PWM_Read2Byte(addr) READ_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
130 #define HAL_PWM_WriteByte(addr, val) WRITE_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2),…
131 #define HAL_PWM_Write2Byte(addr, val) WRITE_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2…
132 #define HAL_PWM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_MapBase + REG_PWM_BASE) + ((add…
H A DregPWM.h117 #define REG_PWM_BASE (0x7E800) macro
/utopia/UTPA2-700.0.x/modules/pwm/hal/messi/pwm/
H A DhalPWM.c128 #define HAL_PWM_ReadByte(addr) READ_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
129 #define HAL_PWM_Read2Byte(addr) READ_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
131 #define HAL_PWM_WriteByte(addr, val) WRITE_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2),…
132 #define HAL_PWM_Write2Byte(addr, val) WRITE_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2…
133 #define HAL_PWM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_MapBase + REG_PWM_BASE) + ((add…
H A DregPWM.h117 #define REG_PWM_BASE (0x7E800) macro
/utopia/UTPA2-700.0.x/modules/pwm/hal/mooney/pwm/
H A DhalPWM.c127 #define HAL_PWM_ReadByte(addr) READ_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
128 #define HAL_PWM_Read2Byte(addr) READ_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
130 #define HAL_PWM_WriteByte(addr, val) WRITE_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2),…
131 #define HAL_PWM_Write2Byte(addr, val) WRITE_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2…
132 #define HAL_PWM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_MapBase + REG_PWM_BASE) + ((add…
H A DregPWM.h117 #define REG_PWM_BASE (0x7E800) macro
/utopia/UTPA2-700.0.x/modules/pwm/hal/mainz/pwm/
H A DhalPWM.c128 #define HAL_PWM_ReadByte(addr) READ_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
129 #define HAL_PWM_Read2Byte(addr) READ_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
131 #define HAL_PWM_WriteByte(addr, val) WRITE_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2),…
132 #define HAL_PWM_Write2Byte(addr, val) WRITE_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2…
133 #define HAL_PWM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_MapBase + REG_PWM_BASE) + ((add…
H A DregPWM.h117 #define REG_PWM_BASE (0x7E800) macro
/utopia/UTPA2-700.0.x/modules/pwm/hal/maxim/pwm/
H A DhalPWM.c127 #define HAL_PWM_ReadByte(addr) READ_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
128 #define HAL_PWM_Read2Byte(addr) READ_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
130 #define HAL_PWM_WriteByte(addr, val) WRITE_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2),…
131 #define HAL_PWM_Write2Byte(addr, val) WRITE_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2…
132 #define HAL_PWM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_MapBase + REG_PWM_BASE) + ((add…
H A DregPWM.h117 #define REG_PWM_BASE (0x7E800) macro
/utopia/UTPA2-700.0.x/modules/pwm/hal/manhattan/pwm/
H A DhalPWM.c127 #define HAL_PWM_ReadByte(addr) READ_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
128 #define HAL_PWM_Read2Byte(addr) READ_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
130 #define HAL_PWM_WriteByte(addr, val) WRITE_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2),…
131 #define HAL_PWM_Write2Byte(addr, val) WRITE_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2…
132 #define HAL_PWM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_MapBase + REG_PWM_BASE) + ((add…
H A DregPWM.h117 #define REG_PWM_BASE (0x7E800) macro

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