xref: /utopia/UTPA2-700.0.x/modules/pwm/hal/manhattan/pwm/halPWM.c (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
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77*53ee8cc1Swenshuai.xi //<MStar Software>
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92*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
93*53ee8cc1Swenshuai.xi #define _HAL_PWM_C
94*53ee8cc1Swenshuai.xi 
95*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
96*53ee8cc1Swenshuai.xi /// @file mhal_PWM.c
97*53ee8cc1Swenshuai.xi /// @author MStar Semiconductor Inc.
98*53ee8cc1Swenshuai.xi /// @brief Pulse Width Modulation driver
99*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
100*53ee8cc1Swenshuai.xi 
101*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
102*53ee8cc1Swenshuai.xi // Header Files
103*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
104*53ee8cc1Swenshuai.xi #include "MsCommon.h"
105*53ee8cc1Swenshuai.xi #include "MsTypes.h"
106*53ee8cc1Swenshuai.xi #include "drvPWM.h"/* this is not good idea, just for temp. */
107*53ee8cc1Swenshuai.xi #include "halPWM.h"
108*53ee8cc1Swenshuai.xi #include "regPWM.h"
109*53ee8cc1Swenshuai.xi 
110*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
111*53ee8cc1Swenshuai.xi // Global variable
112*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
113*53ee8cc1Swenshuai.xi 
114*53ee8cc1Swenshuai.xi static MS_VIRT _gMIO_MapBase = 0;
115*53ee8cc1Swenshuai.xi static MS_VIRT _gMIO_PM_MapBase = 0;
116*53ee8cc1Swenshuai.xi static MS_U16 _gPWM_Status  = 0;
117*53ee8cc1Swenshuai.xi 
118*53ee8cc1Swenshuai.xi //static MS_BOOL _gPWM_DBen   = 0;
119*53ee8cc1Swenshuai.xi static MS_BOOL _gPWM_VDBen  = 0;
120*53ee8cc1Swenshuai.xi 
121*53ee8cc1Swenshuai.xi static void _HAL_PWM_VDBen_SW(PWM_ChNum index, MS_BOOL bSwitch);
122*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
123*53ee8cc1Swenshuai.xi // Define & data type
124*53ee8cc1Swenshuai.xi ///////////////////////////////////////////////////////////////////////////////
125*53ee8cc1Swenshuai.xi #define WRITE_WORD_MASK(_reg, _val, _mask)  { (*((volatile MS_U16*)(_reg))) = ((*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask)); }
126*53ee8cc1Swenshuai.xi 
127*53ee8cc1Swenshuai.xi #define HAL_PWM_ReadByte(addr)		     READ_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
128*53ee8cc1Swenshuai.xi #define HAL_PWM_Read2Byte(addr)              READ_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
129*53ee8cc1Swenshuai.xi 
130*53ee8cc1Swenshuai.xi #define HAL_PWM_WriteByte(addr, val) 	     WRITE_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2), (val))
131*53ee8cc1Swenshuai.xi #define HAL_PWM_Write2Byte(addr, val)        WRITE_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2), (val))
132*53ee8cc1Swenshuai.xi #define HAL_PWM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2), (val), (mask))
133*53ee8cc1Swenshuai.xi 
134*53ee8cc1Swenshuai.xi #define HAL_TOP_ReadByte(addr)		     READ_BYTE((_gMIO_MapBase + REG_TOP_BASE) + ((addr)<<2))
135*53ee8cc1Swenshuai.xi #define HAL_TOP_Read2Byte(addr)              READ_WORD((_gMIO_MapBase + REG_TOP_BASE) + ((addr)<<2))
136*53ee8cc1Swenshuai.xi #define HAL_TOP_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_MapBase + REG_TOP_BASE) + ((addr)<<2), (val), (mask))
137*53ee8cc1Swenshuai.xi 
138*53ee8cc1Swenshuai.xi #define HAL_PM_WriteByte(addr, val) 	     WRITE_BYTE((_gMIO_PM_MapBase + REG_PM_BASE) + ((addr)<<2), (val))
139*53ee8cc1Swenshuai.xi #define HAL_PM_Write2Byte(addr, val)        WRITE_WORD((_gMIO_PM_MapBase + REG_PM_BASE) + ((addr)<<2), (val))
140*53ee8cc1Swenshuai.xi #define HAL_PM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_PM_MapBase + REG_PM_BASE) + ((addr)<<2), (val), (mask))
141*53ee8cc1Swenshuai.xi 
142*53ee8cc1Swenshuai.xi #define HAL_SUBBANK0    //HAL_PWM_WriteByte(0,0)
143*53ee8cc1Swenshuai.xi #define HAL_SUBBANK1    //HAL_PWM_WriteByte(0,1) /* PWM sub-bank */
144*53ee8cc1Swenshuai.xi 
145*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
146*53ee8cc1Swenshuai.xi // Global Function
147*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_Write4Byte(MS_U32 u32RegAddr,MS_U32 u32Val)148*53ee8cc1Swenshuai.xi MS_BOOL HAL_PWM_Write4Byte(MS_U32 u32RegAddr, MS_U32 u32Val)
149*53ee8cc1Swenshuai.xi {
150*53ee8cc1Swenshuai.xi     HAL_PWM_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF);
151*53ee8cc1Swenshuai.xi     HAL_PWM_Write2Byte(u32RegAddr+2, u32Val >> 16);
152*53ee8cc1Swenshuai.xi     return TRUE;
153*53ee8cc1Swenshuai.xi }
154*53ee8cc1Swenshuai.xi 
HAL_PWM_WriteNumberByte(MS_U32 u32RegAddr,MS_U32 u32SetValue,MS_U8 u8BitNum)155*53ee8cc1Swenshuai.xi static MS_BOOL HAL_PWM_WriteNumberByte(MS_U32 u32RegAddr, MS_U32 u32SetValue, MS_U8 u8BitNum)
156*53ee8cc1Swenshuai.xi {
157*53ee8cc1Swenshuai.xi     MS_U32 u32Mask=0x0;
158*53ee8cc1Swenshuai.xi     MS_U32 u32Value=0x0;
159*53ee8cc1Swenshuai.xi     MS_U8 i;
160*53ee8cc1Swenshuai.xi 
161*53ee8cc1Swenshuai.xi     for(i = 0; i<u8BitNum; i++)
162*53ee8cc1Swenshuai.xi         u32Mask |= (1<<i);
163*53ee8cc1Swenshuai.xi     if (u8BitNum == 0)
164*53ee8cc1Swenshuai.xi     {
165*53ee8cc1Swenshuai.xi         return TRUE;
166*53ee8cc1Swenshuai.xi     }
167*53ee8cc1Swenshuai.xi     else if (u8BitNum <= 8)
168*53ee8cc1Swenshuai.xi     {
169*53ee8cc1Swenshuai.xi         u32Value = u32SetValue & u32Mask;
170*53ee8cc1Swenshuai.xi         HAL_PWM_WriteByte(u32RegAddr, (MS_U8) u32Value) ;
171*53ee8cc1Swenshuai.xi     }
172*53ee8cc1Swenshuai.xi     else if (u8BitNum <= 16)
173*53ee8cc1Swenshuai.xi     {
174*53ee8cc1Swenshuai.xi         u32Value = u32SetValue & u32Mask;
175*53ee8cc1Swenshuai.xi         HAL_PWM_Write2Byte(u32RegAddr, (MS_U16) u32Value) ;
176*53ee8cc1Swenshuai.xi     }
177*53ee8cc1Swenshuai.xi     else if (u8BitNum <= 32)
178*53ee8cc1Swenshuai.xi     {
179*53ee8cc1Swenshuai.xi         u32Value = u32SetValue & u32Mask;
180*53ee8cc1Swenshuai.xi         HAL_PWM_Write4Byte(u32RegAddr, (MS_U32) u32Value) ;
181*53ee8cc1Swenshuai.xi     }
182*53ee8cc1Swenshuai.xi     else
183*53ee8cc1Swenshuai.xi     {
184*53ee8cc1Swenshuai.xi         return FALSE;
185*53ee8cc1Swenshuai.xi     }
186*53ee8cc1Swenshuai.xi     return TRUE;
187*53ee8cc1Swenshuai.xi }
188*53ee8cc1Swenshuai.xi 
_HAL_PWM_VDBen_SW(PWM_ChNum index,MS_BOOL bSwitch)189*53ee8cc1Swenshuai.xi static void _HAL_PWM_VDBen_SW(PWM_ChNum index, MS_BOOL bSwitch)
190*53ee8cc1Swenshuai.xi {
191*53ee8cc1Swenshuai.xi 	if(_gPWM_VDBen)
192*53ee8cc1Swenshuai.xi 	{
193*53ee8cc1Swenshuai.xi 		//printf("%s(0x%08X, %x)", __FUNCTION__, (int)index, bSwitch);
194*53ee8cc1Swenshuai.xi 		switch(index)
195*53ee8cc1Swenshuai.xi     	        {
196*53ee8cc1Swenshuai.xi         	case E_PWM_CH0:
197*53ee8cc1Swenshuai.xi             	HAL_PWM_WriteRegBit(REG_PWM0_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14));
198*53ee8cc1Swenshuai.xi             	break;
199*53ee8cc1Swenshuai.xi         	case E_PWM_CH1:
200*53ee8cc1Swenshuai.xi 				HAL_PWM_WriteRegBit(REG_PWM1_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14));
201*53ee8cc1Swenshuai.xi             	break;
202*53ee8cc1Swenshuai.xi         	case E_PWM_CH2:
203*53ee8cc1Swenshuai.xi 				HAL_PWM_WriteRegBit(REG_PWM2_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14));
204*53ee8cc1Swenshuai.xi             	break;
205*53ee8cc1Swenshuai.xi         	case E_PWM_CH3:
206*53ee8cc1Swenshuai.xi 				HAL_PWM_WriteRegBit(REG_PWM3_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14));
207*53ee8cc1Swenshuai.xi             	break;
208*53ee8cc1Swenshuai.xi         	case E_PWM_CH4:
209*53ee8cc1Swenshuai.xi 				HAL_PWM_WriteRegBit(REG_PWM4_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14));
210*53ee8cc1Swenshuai.xi             	break;
211*53ee8cc1Swenshuai.xi         	case E_PWM_CH5:
212*53ee8cc1Swenshuai.xi         	case E_PWM_CH6:
213*53ee8cc1Swenshuai.xi         	case E_PWM_CH7:
214*53ee8cc1Swenshuai.xi         	case E_PWM_CH8:
215*53ee8cc1Swenshuai.xi         	case E_PWM_CH9:
216*53ee8cc1Swenshuai.xi 				printf("[Utopia] The PWM%d is not support\n", (int)index);
217*53ee8cc1Swenshuai.xi             	UNUSED(bSwitch);
218*53ee8cc1Swenshuai.xi             	break;
219*53ee8cc1Swenshuai.xi 			default:
220*53ee8cc1Swenshuai.xi 				break;
221*53ee8cc1Swenshuai.xi 		}
222*53ee8cc1Swenshuai.xi 	}
223*53ee8cc1Swenshuai.xi }
224*53ee8cc1Swenshuai.xi 
225*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
226*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name: HAL_PWM_SetIOMapBase
227*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description: Set IO Map base
228*53ee8cc1Swenshuai.xi /// @param <IN>          \b None :
229*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
230*53ee8cc1Swenshuai.xi /// @param <RET>        \b None :
231*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
232*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_SetIOMapBase(MS_VIRT virtBase,MS_VIRT virtBase1)233*53ee8cc1Swenshuai.xi void HAL_PWM_SetIOMapBase(MS_VIRT virtBase,MS_VIRT virtBase1)
234*53ee8cc1Swenshuai.xi {
235*53ee8cc1Swenshuai.xi     _gMIO_MapBase = virtBase;
236*53ee8cc1Swenshuai.xi     _gMIO_PM_MapBase = virtBase1;
237*53ee8cc1Swenshuai.xi }
238*53ee8cc1Swenshuai.xi 
239*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
240*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name: HAL_PWM_SetChipTopIOMapBase
241*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description: Set chip top IO Map base
242*53ee8cc1Swenshuai.xi /// @param <IN>          \b None :
243*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
244*53ee8cc1Swenshuai.xi /// @param <RET>        \b None :
245*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
246*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_SetChipTopIOMapBase(MS_VIRT virtBase)247*53ee8cc1Swenshuai.xi void HAL_PWM_SetChipTopIOMapBase(MS_VIRT virtBase)
248*53ee8cc1Swenshuai.xi {
249*53ee8cc1Swenshuai.xi 
250*53ee8cc1Swenshuai.xi }
251*53ee8cc1Swenshuai.xi 
252*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
253*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name: HAL_PWM_GetIOMapBase
254*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description: Get IO Map base
255*53ee8cc1Swenshuai.xi /// @param <IN>          \b None :
256*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
257*53ee8cc1Swenshuai.xi /// @param <RET>        \b None :
258*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
259*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_GetIOMapBase(void)260*53ee8cc1Swenshuai.xi MS_VIRT HAL_PWM_GetIOMapBase(void)
261*53ee8cc1Swenshuai.xi {
262*53ee8cc1Swenshuai.xi     return _gMIO_MapBase;
263*53ee8cc1Swenshuai.xi }
264*53ee8cc1Swenshuai.xi 
265*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
266*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name: HAL_PWM_Init
267*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description: Initial PWM
268*53ee8cc1Swenshuai.xi /// @param <IN>          \b None :
269*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
270*53ee8cc1Swenshuai.xi /// @param <RET>        \b MS_BOOL :
271*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
272*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_Init(void)273*53ee8cc1Swenshuai.xi MS_BOOL HAL_PWM_Init(void)
274*53ee8cc1Swenshuai.xi {
275*53ee8cc1Swenshuai.xi     MS_BOOL ret = FALSE;
276*53ee8cc1Swenshuai.xi #if 0
277*53ee8cc1Swenshuai.xi     HAL_PWM_WriteRegBit(REG_ALL_PAD_IN, BIT7, 0);
278*53ee8cc1Swenshuai.xi     HAL_PWM_WriteRegBit(REG_PWM_IS_GPIO, BIT0, 0);
279*53ee8cc1Swenshuai.xi     HAL_PWM_WriteRegBit(REG_PWM_IS_GPIO, BIT1, 0);
280*53ee8cc1Swenshuai.xi     HAL_PWM_WriteRegBit(REG_PWM_IS_GPIO, BIT2, 0);
281*53ee8cc1Swenshuai.xi     HAL_PWM_WriteRegBit(REG_PWM_IS_GPIO, BIT3, 0);
282*53ee8cc1Swenshuai.xi #endif
283*53ee8cc1Swenshuai.xi 	_gPWM_Status = HAL_TOP_Read2Byte(REG_PWM_MODE);
284*53ee8cc1Swenshuai.xi 
285*53ee8cc1Swenshuai.xi 	if(_gPWM_Status&PAD_PWM0_OUT)
286*53ee8cc1Swenshuai.xi 	{
287*53ee8cc1Swenshuai.xi 		printf("Init PWM0\n");
288*53ee8cc1Swenshuai.xi 	}
289*53ee8cc1Swenshuai.xi 	if(_gPWM_Status&PAD_PWM1_OUT)
290*53ee8cc1Swenshuai.xi 	{
291*53ee8cc1Swenshuai.xi 		printf("Init PWM1\n");
292*53ee8cc1Swenshuai.xi 	}
293*53ee8cc1Swenshuai.xi 	if(_gPWM_Status&PAD_PWM2_OUT)
294*53ee8cc1Swenshuai.xi 	{
295*53ee8cc1Swenshuai.xi 		printf("Init PWM2\n");
296*53ee8cc1Swenshuai.xi 	}
297*53ee8cc1Swenshuai.xi 	if(_gPWM_Status&PAD_PWM3_OUT)
298*53ee8cc1Swenshuai.xi 	{
299*53ee8cc1Swenshuai.xi 		printf("Init PWM3\n");
300*53ee8cc1Swenshuai.xi 	}
301*53ee8cc1Swenshuai.xi 	if(_gPWM_Status&PAD_PWM4_OUT)
302*53ee8cc1Swenshuai.xi 	{
303*53ee8cc1Swenshuai.xi 		printf("Init PWM4\n");
304*53ee8cc1Swenshuai.xi 	}
305*53ee8cc1Swenshuai.xi     ret = TRUE;
306*53ee8cc1Swenshuai.xi     return ret;
307*53ee8cc1Swenshuai.xi }
308*53ee8cc1Swenshuai.xi 
309*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
310*53ee8cc1Swenshuai.xi /// @brief \b Function  \b Name: HAL_PWM_Oen
311*53ee8cc1Swenshuai.xi /// @brief \b Function  \b Description: Switch PWM PAD as Output or Input
312*53ee8cc1Swenshuai.xi /// @param <IN>         \b MS_U16 : index
313*53ee8cc1Swenshuai.xi /// @param <IN>         \b MS_BOOL : letch, 1 for Input; 0 for Output
314*53ee8cc1Swenshuai.xi /// @param <OUT>      \b None :
315*53ee8cc1Swenshuai.xi /// @param <RET>       \b MS_BOOL :
316*53ee8cc1Swenshuai.xi /// @param <GLOBAL>  \b None :
317*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_Oen(PWM_ChNum index,MS_BOOL letch)318*53ee8cc1Swenshuai.xi MS_BOOL HAL_PWM_Oen(PWM_ChNum index, MS_BOOL letch)
319*53ee8cc1Swenshuai.xi {
320*53ee8cc1Swenshuai.xi 
321*53ee8cc1Swenshuai.xi     //Use the PWM oen in ChipTop Reg first, if it provides for.
322*53ee8cc1Swenshuai.xi 
323*53ee8cc1Swenshuai.xi     switch(index)
324*53ee8cc1Swenshuai.xi     {
325*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
326*53ee8cc1Swenshuai.xi             HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(0:0,letch), BMASK(0:0));
327*53ee8cc1Swenshuai.xi             break;
328*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
329*53ee8cc1Swenshuai.xi 			HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(1:1,letch), BMASK(1:1));
330*53ee8cc1Swenshuai.xi             break;
331*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
332*53ee8cc1Swenshuai.xi 			HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(2:2,letch), BMASK(2:2));
333*53ee8cc1Swenshuai.xi             break;
334*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
335*53ee8cc1Swenshuai.xi 			HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(3:3,letch), BMASK(3:3));
336*53ee8cc1Swenshuai.xi             break;
337*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
338*53ee8cc1Swenshuai.xi 			HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(4:4,letch), BMASK(4:4));
339*53ee8cc1Swenshuai.xi             break;
340*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
341*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
342*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
343*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
344*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
345*53ee8cc1Swenshuai.xi 			printf("[Utopia] The PWM%d is not support\n", (int)index);
346*53ee8cc1Swenshuai.xi             UNUSED(letch);
347*53ee8cc1Swenshuai.xi             break;
348*53ee8cc1Swenshuai.xi 		default:
349*53ee8cc1Swenshuai.xi 			break;
350*53ee8cc1Swenshuai.xi     }
351*53ee8cc1Swenshuai.xi 
352*53ee8cc1Swenshuai.xi     return TRUE;
353*53ee8cc1Swenshuai.xi }
354*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
355*53ee8cc1Swenshuai.xi /// @brief \b Function  \b Name: HAL_PWM_GetOen
356*53ee8cc1Swenshuai.xi /// @brief \b Function  \b Description: Switch PWM PAD as Output or Input
357*53ee8cc1Swenshuai.xi /// @param <IN>         \b MS_U16 : index
358*53ee8cc1Swenshuai.xi /// @param <OUT>      \b None :
359*53ee8cc1Swenshuai.xi /// @param <RET>       \b MS_BOOL : letch, 1 for Input; 0 for Output
360*53ee8cc1Swenshuai.xi /// @param <GLOBAL>  \b None :
361*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_GetOen(PWM_ChNum index)362*53ee8cc1Swenshuai.xi MS_BOOL HAL_PWM_GetOen(PWM_ChNum index)
363*53ee8cc1Swenshuai.xi {
364*53ee8cc1Swenshuai.xi     MS_BOOL letch = 0;
365*53ee8cc1Swenshuai.xi     //Use the PWM oen in ChipTop Reg first, if it provides for.
366*53ee8cc1Swenshuai.xi     switch(index)
367*53ee8cc1Swenshuai.xi     {
368*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
369*53ee8cc1Swenshuai.xi             letch = (HAL_PWM_Read2Byte(REG_PWM_OEN) & BMASK(0:0)) >> 0;
370*53ee8cc1Swenshuai.xi             break;
371*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
372*53ee8cc1Swenshuai.xi             letch = (HAL_PWM_Read2Byte(REG_PWM_OEN) & BMASK(1:1)) >> 1;
373*53ee8cc1Swenshuai.xi             break;
374*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
375*53ee8cc1Swenshuai.xi             letch = (HAL_PWM_Read2Byte(REG_PWM_OEN) & BMASK(2:2)) >> 2;
376*53ee8cc1Swenshuai.xi             break;
377*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
378*53ee8cc1Swenshuai.xi             letch = (HAL_PWM_Read2Byte(REG_PWM_OEN) & BMASK(3:3)) >> 3;
379*53ee8cc1Swenshuai.xi             break;
380*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
381*53ee8cc1Swenshuai.xi             letch = (HAL_PWM_Read2Byte(REG_PWM_OEN) & BMASK(4:4)) >> 4;
382*53ee8cc1Swenshuai.xi             break;
383*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
384*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
385*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
386*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
387*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
388*53ee8cc1Swenshuai.xi 			printf("[Utopia] The PWM%d is not support\n", (int)index);
389*53ee8cc1Swenshuai.xi             break;
390*53ee8cc1Swenshuai.xi 		default:
391*53ee8cc1Swenshuai.xi 			break;
392*53ee8cc1Swenshuai.xi     }
393*53ee8cc1Swenshuai.xi     return letch;
394*53ee8cc1Swenshuai.xi }
395*53ee8cc1Swenshuai.xi 
396*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
397*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_UnitDiv
398*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description : Set the Unit_Div of the pwm
399*53ee8cc1Swenshuai.xi /// @param <IN>          \b MS_U16 : the Unit_Div value
400*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
401*53ee8cc1Swenshuai.xi /// @param <RET>        \b MS_BOOL : 1 for doen; 0 for not done
402*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
403*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_UnitDiv(MS_U16 u16DivPWM)404*53ee8cc1Swenshuai.xi MS_BOOL HAL_PWM_UnitDiv(MS_U16 u16DivPWM)
405*53ee8cc1Swenshuai.xi {
406*53ee8cc1Swenshuai.xi     MS_BOOL ret = FALSE;
407*53ee8cc1Swenshuai.xi     /* the PWM clock unit divider is NO USE in T3 */
408*53ee8cc1Swenshuai.xi     UNUSED(u16DivPWM);
409*53ee8cc1Swenshuai.xi     printf("[Utopia] T8 is not support\n");
410*53ee8cc1Swenshuai.xi     return ret;
411*53ee8cc1Swenshuai.xi }
412*53ee8cc1Swenshuai.xi 
413*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
414*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_Period
415*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description : Set the period of the specific pwm
416*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the PWM CH
417*53ee8cc1Swenshuai.xi /// @param <IN>          \b MS_U32 : the 18-bit Period value
418*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
419*53ee8cc1Swenshuai.xi /// @param <RET>        \b None :
420*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
421*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_Period(PWM_ChNum index,MS_U32 u32PeriodPWM)422*53ee8cc1Swenshuai.xi void HAL_PWM_Period(PWM_ChNum index, MS_U32 u32PeriodPWM)
423*53ee8cc1Swenshuai.xi {
424*53ee8cc1Swenshuai.xi     MS_U16  Period_L, Period_H;
425*53ee8cc1Swenshuai.xi     Period_L = (MS_U16)u32PeriodPWM;
426*53ee8cc1Swenshuai.xi     Period_H = (MS_U16)(u32PeriodPWM >> 16);
427*53ee8cc1Swenshuai.xi 
428*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
429*53ee8cc1Swenshuai.xi     _HAL_PWM_VDBen_SW(index,0);
430*53ee8cc1Swenshuai.xi     /* the Period capability is restricted to ONLY 18-bit */
431*53ee8cc1Swenshuai.xi     switch(index)
432*53ee8cc1Swenshuai.xi     {
433*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
434*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM0_PERIOD, Period_L);
435*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM0_PERIOD_EXT,BITS(1:0,Period_H),BMASK(1:0));
436*53ee8cc1Swenshuai.xi             break;
437*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
438*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM1_PERIOD, Period_L);
439*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM1_PERIOD_EXT,BITS(3:2,Period_H),BMASK(3:2));
440*53ee8cc1Swenshuai.xi             break;
441*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
442*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM2_PERIOD, Period_L);
443*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM2_PERIOD_EXT,BITS(5:4,Period_H),BMASK(5:4));
444*53ee8cc1Swenshuai.xi             break;
445*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
446*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM3_PERIOD, Period_L);
447*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM3_PERIOD_EXT,BITS(7:6,Period_H),BMASK(7:6));
448*53ee8cc1Swenshuai.xi             break;
449*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
450*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM4_PERIOD, Period_L);
451*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM4_PERIOD_EXT,BITS(9:8,Period_H),BMASK(9:8));
452*53ee8cc1Swenshuai.xi             break;
453*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
454*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
455*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
456*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
457*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
458*53ee8cc1Swenshuai.xi 	    printf("[Utopia] The PWM%d is not support\n", (int)index);
459*53ee8cc1Swenshuai.xi             UNUSED(Period_L);
460*53ee8cc1Swenshuai.xi             UNUSED(Period_H);
461*53ee8cc1Swenshuai.xi             break;
462*53ee8cc1Swenshuai.xi 		default:
463*53ee8cc1Swenshuai.xi 			break;
464*53ee8cc1Swenshuai.xi     }
465*53ee8cc1Swenshuai.xi     _HAL_PWM_VDBen_SW(index,1);
466*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
467*53ee8cc1Swenshuai.xi }
468*53ee8cc1Swenshuai.xi 
HAL_PWM_GetPeriod(PWM_ChNum index)469*53ee8cc1Swenshuai.xi MS_U32 HAL_PWM_GetPeriod(PWM_ChNum index)
470*53ee8cc1Swenshuai.xi {
471*53ee8cc1Swenshuai.xi     MS_U16  Period_L=0, Period_H=0;
472*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
473*53ee8cc1Swenshuai.xi     _HAL_PWM_VDBen_SW(index,0);
474*53ee8cc1Swenshuai.xi     switch(index)
475*53ee8cc1Swenshuai.xi     {
476*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
477*53ee8cc1Swenshuai.xi             Period_L = HAL_PWM_Read2Byte(REG_PWM0_PERIOD);
478*53ee8cc1Swenshuai.xi             Period_H = HAL_PWM_ReadByte(REG_PWM0_PERIOD_EXT) & BMASK(1:0);
479*53ee8cc1Swenshuai.xi             break;
480*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
481*53ee8cc1Swenshuai.xi             Period_L = HAL_PWM_Read2Byte(REG_PWM1_PERIOD);
482*53ee8cc1Swenshuai.xi             Period_H = (HAL_PWM_ReadByte(REG_PWM1_PERIOD_EXT) & BMASK(3:2)) >> 2;
483*53ee8cc1Swenshuai.xi             break;
484*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
485*53ee8cc1Swenshuai.xi             Period_L = HAL_PWM_Read2Byte(REG_PWM2_PERIOD);
486*53ee8cc1Swenshuai.xi             Period_H = (HAL_PWM_ReadByte(REG_PWM2_PERIOD_EXT) & BMASK(5:4)) >> 4;
487*53ee8cc1Swenshuai.xi             break;
488*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
489*53ee8cc1Swenshuai.xi             Period_L = HAL_PWM_Read2Byte(REG_PWM3_PERIOD);
490*53ee8cc1Swenshuai.xi             Period_H = (HAL_PWM_ReadByte(REG_PWM3_PERIOD_EXT) & BMASK(7:6)) >> 6;
491*53ee8cc1Swenshuai.xi             break;
492*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
493*53ee8cc1Swenshuai.xi             Period_L = HAL_PWM_Read2Byte(REG_PWM4_PERIOD);
494*53ee8cc1Swenshuai.xi             Period_H = (HAL_PWM_Read2Byte(REG_PWM4_PERIOD_EXT) & BMASK(9:8)) >> 8;
495*53ee8cc1Swenshuai.xi             break;
496*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
497*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
498*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
499*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
500*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
501*53ee8cc1Swenshuai.xi         printf("[Utopia] The PWM%d is not support\n", (int)index);
502*53ee8cc1Swenshuai.xi             UNUSED(Period_L);
503*53ee8cc1Swenshuai.xi             UNUSED(Period_H);
504*53ee8cc1Swenshuai.xi             break;
505*53ee8cc1Swenshuai.xi         default:
506*53ee8cc1Swenshuai.xi             break;
507*53ee8cc1Swenshuai.xi     }
508*53ee8cc1Swenshuai.xi     _HAL_PWM_VDBen_SW(index,1);
509*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
510*53ee8cc1Swenshuai.xi     return ((MS_U32)Period_H << 16 | Period_L);
511*53ee8cc1Swenshuai.xi }
512*53ee8cc1Swenshuai.xi 
513*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
514*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_DutyCycle
515*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description : Set the Duty of the specific pwm
516*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the PWM CH
517*53ee8cc1Swenshuai.xi /// @param <IN>          \b MS_U32 : the 18-bit Duty value
518*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
519*53ee8cc1Swenshuai.xi /// @param <RET>        \b None :
520*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
521*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_DutyCycle(PWM_ChNum index,MS_U32 u32DutyPWM)522*53ee8cc1Swenshuai.xi void HAL_PWM_DutyCycle(PWM_ChNum index, MS_U32 u32DutyPWM)
523*53ee8cc1Swenshuai.xi {
524*53ee8cc1Swenshuai.xi     MS_U16  Duty_L, Duty_H;
525*53ee8cc1Swenshuai.xi 
526*53ee8cc1Swenshuai.xi     Duty_L = (MS_U16)u32DutyPWM;
527*53ee8cc1Swenshuai.xi     Duty_H = (MS_U8)(u32DutyPWM >> 16);
528*53ee8cc1Swenshuai.xi 
529*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
530*53ee8cc1Swenshuai.xi     _HAL_PWM_VDBen_SW(index,0);
531*53ee8cc1Swenshuai.xi     /* the Duty capability is restricted to ONLY 10-bit */
532*53ee8cc1Swenshuai.xi     switch(index)
533*53ee8cc1Swenshuai.xi     {
534*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
535*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM0_DUTY, Duty_L);
536*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM0_DUTY_EXT,BITS(1:0,Duty_H),BMASK(1:0));
537*53ee8cc1Swenshuai.xi             break;
538*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
539*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM1_DUTY, Duty_L);
540*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM1_DUTY_EXT,BITS(3:2,Duty_H),BMASK(3:2));
541*53ee8cc1Swenshuai.xi             break;
542*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
543*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM2_DUTY, Duty_L);
544*53ee8cc1Swenshuai.xi 	    HAL_PWM_WriteRegBit(REG_PWM2_DUTY_EXT,BITS(5:4,Duty_H),BMASK(5:4));
545*53ee8cc1Swenshuai.xi             break;
546*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
547*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM3_DUTY, Duty_L);
548*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM3_DUTY_EXT,BITS(7:6,Duty_H),BMASK(7:6));
549*53ee8cc1Swenshuai.xi             break;
550*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
551*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM4_DUTY, Duty_L);
552*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM4_DUTY_EXT,BITS(9:8,Duty_H),BMASK(9:8));
553*53ee8cc1Swenshuai.xi             break;
554*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
555*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
556*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
557*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
558*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
559*53ee8cc1Swenshuai.xi 			printf("[Utopia] The PWM%d is not support\n", (int)index);
560*53ee8cc1Swenshuai.xi             UNUSED(Duty_L);
561*53ee8cc1Swenshuai.xi             UNUSED(Duty_H);
562*53ee8cc1Swenshuai.xi             break;
563*53ee8cc1Swenshuai.xi 		default:
564*53ee8cc1Swenshuai.xi 			break;
565*53ee8cc1Swenshuai.xi     }
566*53ee8cc1Swenshuai.xi     _HAL_PWM_VDBen_SW(index,1);
567*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
568*53ee8cc1Swenshuai.xi }
569*53ee8cc1Swenshuai.xi 
HAL_PWM_GetDutyCycle(PWM_ChNum index)570*53ee8cc1Swenshuai.xi MS_U32 HAL_PWM_GetDutyCycle(PWM_ChNum index)
571*53ee8cc1Swenshuai.xi {
572*53ee8cc1Swenshuai.xi     MS_U16  Duty_L=0, Duty_H=0;
573*53ee8cc1Swenshuai.xi 
574*53ee8cc1Swenshuai.xi     //Duty_L = (MS_U16)u32DutyPWM;
575*53ee8cc1Swenshuai.xi     //Duty_H = (MS_U8)(u32DutyPWM >> 16);
576*53ee8cc1Swenshuai.xi 
577*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
578*53ee8cc1Swenshuai.xi     _HAL_PWM_VDBen_SW(index,0);
579*53ee8cc1Swenshuai.xi     /* the Duty capability is restricted to ONLY 10-bit */
580*53ee8cc1Swenshuai.xi     switch(index)
581*53ee8cc1Swenshuai.xi     {
582*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
583*53ee8cc1Swenshuai.xi             Duty_L = HAL_PWM_Read2Byte(REG_PWM0_DUTY);
584*53ee8cc1Swenshuai.xi             Duty_H = HAL_PWM_ReadByte(REG_PWM0_DUTY_EXT) & BMASK(1:0);
585*53ee8cc1Swenshuai.xi             break;
586*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
587*53ee8cc1Swenshuai.xi             Duty_L = HAL_PWM_Read2Byte(REG_PWM1_DUTY);
588*53ee8cc1Swenshuai.xi             Duty_H = (HAL_PWM_ReadByte(REG_PWM1_DUTY_EXT) & BMASK(3:2)) >> 2;
589*53ee8cc1Swenshuai.xi             break;
590*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
591*53ee8cc1Swenshuai.xi             Duty_L = HAL_PWM_Read2Byte(REG_PWM2_DUTY);
592*53ee8cc1Swenshuai.xi             Duty_H = (HAL_PWM_ReadByte(REG_PWM2_DUTY_EXT) & BMASK(5:4)) >> 4;
593*53ee8cc1Swenshuai.xi             break;
594*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
595*53ee8cc1Swenshuai.xi             Duty_L = HAL_PWM_Read2Byte(REG_PWM3_DUTY);
596*53ee8cc1Swenshuai.xi             Duty_H = (HAL_PWM_ReadByte(REG_PWM3_DUTY_EXT) & BMASK(7:6)) >> 6;
597*53ee8cc1Swenshuai.xi             break;
598*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
599*53ee8cc1Swenshuai.xi             Duty_L = HAL_PWM_Read2Byte(REG_PWM4_DUTY);
600*53ee8cc1Swenshuai.xi             Duty_H = (HAL_PWM_Read2Byte(REG_PWM4_DUTY_EXT) & BMASK(9:8)) >> 8;
601*53ee8cc1Swenshuai.xi             break;
602*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
603*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
604*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
605*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
606*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
607*53ee8cc1Swenshuai.xi             printf("[Utopia] The PWM%d is not support\n", (int)index);
608*53ee8cc1Swenshuai.xi             UNUSED(Duty_L);
609*53ee8cc1Swenshuai.xi             UNUSED(Duty_H);
610*53ee8cc1Swenshuai.xi             break;
611*53ee8cc1Swenshuai.xi         default:
612*53ee8cc1Swenshuai.xi             break;
613*53ee8cc1Swenshuai.xi     }
614*53ee8cc1Swenshuai.xi     _HAL_PWM_VDBen_SW(index,1);
615*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
616*53ee8cc1Swenshuai.xi     return ((MS_U32)Duty_H << 16 | Duty_L);
617*53ee8cc1Swenshuai.xi }
618*53ee8cc1Swenshuai.xi 
619*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
620*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_Div
621*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description : Set the Div of the specific pwm
622*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the PWM CH
623*53ee8cc1Swenshuai.xi /// @param <IN>          \b MS_U16 : the 16-bit Div value
624*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
625*53ee8cc1Swenshuai.xi /// @param <RET>        \b None :
626*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
627*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_Div(PWM_ChNum index,MS_U16 u16DivPWM)628*53ee8cc1Swenshuai.xi void HAL_PWM_Div(PWM_ChNum index, MS_U16 u16DivPWM)
629*53ee8cc1Swenshuai.xi {
630*53ee8cc1Swenshuai.xi 	MS_U8 u8DivPWM[2] = {0};
631*53ee8cc1Swenshuai.xi 
632*53ee8cc1Swenshuai.xi 	u8DivPWM[0] = (MS_U8)(u16DivPWM&0xFF);
633*53ee8cc1Swenshuai.xi 	u8DivPWM[1] = (MS_U8)(u16DivPWM >> 8);
634*53ee8cc1Swenshuai.xi 
635*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
636*53ee8cc1Swenshuai.xi     /* the Div capability is restricted to ONLY 16-bit */
637*53ee8cc1Swenshuai.xi     switch(index)
638*53ee8cc1Swenshuai.xi     {
639*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
640*53ee8cc1Swenshuai.xi             HAL_PWM_WriteByte(REG_PWM0_DIV,     u8DivPWM[0]);
641*53ee8cc1Swenshuai.xi             HAL_PWM_WriteByte(REG_PWM0_DIV_EXT, u8DivPWM[1]);
642*53ee8cc1Swenshuai.xi             break;
643*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
644*53ee8cc1Swenshuai.xi             HAL_PWM_WriteByte(REG_PWM1_DIV,     u8DivPWM[0]);
645*53ee8cc1Swenshuai.xi             //HAL_PWM_WriteByte(REG_PWM1_DIV_EXT+1, u8DivPWM[1]);
646*53ee8cc1Swenshuai.xi 			HAL_PWM_WriteRegBit(REG_PWM1_DIV_EXT,u16DivPWM,BMASK(15:8));
647*53ee8cc1Swenshuai.xi             break;
648*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
649*53ee8cc1Swenshuai.xi             HAL_PWM_WriteByte(REG_PWM2_DIV,     u8DivPWM[0]);
650*53ee8cc1Swenshuai.xi             HAL_PWM_WriteByte(REG_PWM2_DIV_EXT, u8DivPWM[1]);
651*53ee8cc1Swenshuai.xi             break;
652*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
653*53ee8cc1Swenshuai.xi             HAL_PWM_WriteByte(REG_PWM3_DIV,     u8DivPWM[0]);
654*53ee8cc1Swenshuai.xi             //HAL_PWM_WriteByte(REG_PWM3_DIV_EXT+1, u8DivPWM[1]);
655*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM3_DIV_EXT,u16DivPWM,BMASK(15:8));
656*53ee8cc1Swenshuai.xi             break;
657*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
658*53ee8cc1Swenshuai.xi             HAL_PWM_WriteByte(REG_PWM4_DIV, 	u8DivPWM[0]);
659*53ee8cc1Swenshuai.xi             HAL_PWM_WriteByte(REG_PWM4_DIV_EXT, u8DivPWM[1]);
660*53ee8cc1Swenshuai.xi             break;
661*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
662*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
663*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
664*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
665*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
666*53ee8cc1Swenshuai.xi 	    printf("[Utopia] The PWM%d is not support\n", (int)index);
667*53ee8cc1Swenshuai.xi             UNUSED(u16DivPWM);
668*53ee8cc1Swenshuai.xi             break;
669*53ee8cc1Swenshuai.xi 		default:
670*53ee8cc1Swenshuai.xi 			break;
671*53ee8cc1Swenshuai.xi     }
672*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
673*53ee8cc1Swenshuai.xi }
674*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
675*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_GetDiv
676*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description :Get the Div of the specific pwm
677*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the PWM CH
678*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
679*53ee8cc1Swenshuai.xi /// @param <RET>        \b MS_U16 : the 16-bit Div value
680*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
681*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_GetDiv(PWM_ChNum index)682*53ee8cc1Swenshuai.xi MS_U16 HAL_PWM_GetDiv(PWM_ChNum index)
683*53ee8cc1Swenshuai.xi {
684*53ee8cc1Swenshuai.xi 	MS_U8 u8DivPWM[2] = {0};
685*53ee8cc1Swenshuai.xi 
686*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
687*53ee8cc1Swenshuai.xi     /* the Div capability is restricted to ONLY 16-bit */
688*53ee8cc1Swenshuai.xi     switch(index)
689*53ee8cc1Swenshuai.xi     {
690*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
691*53ee8cc1Swenshuai.xi             u8DivPWM[0] = HAL_PWM_ReadByte(REG_PWM0_DIV);
692*53ee8cc1Swenshuai.xi             u8DivPWM[1] = HAL_PWM_ReadByte(REG_PWM0_DIV_EXT);
693*53ee8cc1Swenshuai.xi             break;
694*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
695*53ee8cc1Swenshuai.xi             u8DivPWM[0] = HAL_PWM_ReadByte(REG_PWM1_DIV);
696*53ee8cc1Swenshuai.xi             u8DivPWM[1] = ((HAL_PWM_Read2Byte(REG_PWM1_DIV_EXT) & BMASK(15:8)) >> 8)&0xFF;
697*53ee8cc1Swenshuai.xi             break;
698*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
699*53ee8cc1Swenshuai.xi             u8DivPWM[0] = HAL_PWM_ReadByte(REG_PWM2_DIV);
700*53ee8cc1Swenshuai.xi             u8DivPWM[1] = HAL_PWM_ReadByte(REG_PWM2_DIV_EXT);
701*53ee8cc1Swenshuai.xi             break;
702*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
703*53ee8cc1Swenshuai.xi             u8DivPWM[0] = HAL_PWM_ReadByte(REG_PWM3_DIV);
704*53ee8cc1Swenshuai.xi             u8DivPWM[1] = ((HAL_PWM_Read2Byte(REG_PWM3_DIV_EXT) & BMASK(15:8)) >> 8)&0xFF;
705*53ee8cc1Swenshuai.xi             break;
706*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
707*53ee8cc1Swenshuai.xi             u8DivPWM[0] = HAL_PWM_ReadByte(REG_PWM4_DIV);
708*53ee8cc1Swenshuai.xi             u8DivPWM[1] = HAL_PWM_ReadByte(REG_PWM4_DIV_EXT);
709*53ee8cc1Swenshuai.xi             break;
710*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
711*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
712*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
713*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
714*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
715*53ee8cc1Swenshuai.xi 	        printf("[Utopia] The PWM%d is not support\n", (int)index);
716*53ee8cc1Swenshuai.xi             break;
717*53ee8cc1Swenshuai.xi 		default:
718*53ee8cc1Swenshuai.xi 			break;
719*53ee8cc1Swenshuai.xi     }
720*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
721*53ee8cc1Swenshuai.xi 
722*53ee8cc1Swenshuai.xi     return ((u8DivPWM[1]<<8) | u8DivPWM[0]);
723*53ee8cc1Swenshuai.xi }
724*53ee8cc1Swenshuai.xi 
725*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
726*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_Polarity
727*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description : Set the Polarity of the specific pwm
728*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the PWM CH
729*53ee8cc1Swenshuai.xi /// @param <IN>          \b MS_BOOL : 1 for enable; 0 for disable
730*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
731*53ee8cc1Swenshuai.xi /// @param <RET>        \b None :
732*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
733*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_Polarity(PWM_ChNum index,MS_BOOL bPolPWM)734*53ee8cc1Swenshuai.xi void HAL_PWM_Polarity(PWM_ChNum index, MS_BOOL bPolPWM)
735*53ee8cc1Swenshuai.xi {
736*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
737*53ee8cc1Swenshuai.xi     switch(index)
738*53ee8cc1Swenshuai.xi     {
739*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
740*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM0_PORARITY,BITS(8:8,bPolPWM),BMASK(8:8));
741*53ee8cc1Swenshuai.xi             break;
742*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
743*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM1_PORARITY,BITS(8:8,bPolPWM),BMASK(8:8));
744*53ee8cc1Swenshuai.xi             break;
745*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
746*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM2_PORARITY,BITS(8:8,bPolPWM),BMASK(8:8));
747*53ee8cc1Swenshuai.xi             break;
748*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
749*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM3_PORARITY,BITS(8:8,bPolPWM),BMASK(8:8));
750*53ee8cc1Swenshuai.xi             break;
751*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
752*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM4_PORARITY,BITS(8:8,bPolPWM),BMASK(8:8));
753*53ee8cc1Swenshuai.xi             break;
754*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
755*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
756*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
757*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
758*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
759*53ee8cc1Swenshuai.xi 	    printf("[Utopia] The PWM%d is not support\n", (int)index);
760*53ee8cc1Swenshuai.xi             UNUSED(bPolPWM);
761*53ee8cc1Swenshuai.xi             break;
762*53ee8cc1Swenshuai.xi 		default:
763*53ee8cc1Swenshuai.xi 			break;
764*53ee8cc1Swenshuai.xi     }
765*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
766*53ee8cc1Swenshuai.xi }
767*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
768*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_GetPolarity
769*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description : Get the Polarity of the specific pwm
770*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the PWM CH
771*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
772*53ee8cc1Swenshuai.xi /// @param <RET>        \b MS_BOOL : 1 for enable; 0 for disable
773*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
774*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_GetPolarity(PWM_ChNum index)775*53ee8cc1Swenshuai.xi MS_BOOL HAL_PWM_GetPolarity(PWM_ChNum index)
776*53ee8cc1Swenshuai.xi {
777*53ee8cc1Swenshuai.xi     MS_BOOL bPolarity = FALSE;
778*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
779*53ee8cc1Swenshuai.xi     switch(index)
780*53ee8cc1Swenshuai.xi     {
781*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
782*53ee8cc1Swenshuai.xi             bPolarity = (HAL_PWM_Read2Byte(REG_PWM0_PORARITY) & BMASK(8:8)) >> 8;
783*53ee8cc1Swenshuai.xi             break;
784*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
785*53ee8cc1Swenshuai.xi             bPolarity = (HAL_PWM_Read2Byte(REG_PWM1_PORARITY) & BMASK(8:8)) >> 8;
786*53ee8cc1Swenshuai.xi             break;
787*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
788*53ee8cc1Swenshuai.xi             bPolarity = (HAL_PWM_Read2Byte(REG_PWM2_PORARITY) & BMASK(8:8)) >> 8;
789*53ee8cc1Swenshuai.xi             break;
790*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
791*53ee8cc1Swenshuai.xi             bPolarity = (HAL_PWM_Read2Byte(REG_PWM3_PORARITY) & BMASK(8:8)) >> 8;
792*53ee8cc1Swenshuai.xi             break;
793*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
794*53ee8cc1Swenshuai.xi             bPolarity = (HAL_PWM_Read2Byte(REG_PWM4_PORARITY) & BMASK(8:8)) >> 8;
795*53ee8cc1Swenshuai.xi             break;
796*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
797*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
798*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
799*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
800*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
801*53ee8cc1Swenshuai.xi 	        printf("[Utopia] The PWM%d is not support\n", (int)index);
802*53ee8cc1Swenshuai.xi             break;
803*53ee8cc1Swenshuai.xi 		default:
804*53ee8cc1Swenshuai.xi 			break;
805*53ee8cc1Swenshuai.xi     }
806*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
807*53ee8cc1Swenshuai.xi 
808*53ee8cc1Swenshuai.xi     return bPolarity;
809*53ee8cc1Swenshuai.xi }
810*53ee8cc1Swenshuai.xi 
811*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
812*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_VDBen
813*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description : Set the Vsync Double buffer of the specific pwm
814*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the PWM CH
815*53ee8cc1Swenshuai.xi /// @param <IN>          \b MS_BOOL : 1 for enable; 0 for disable
816*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
817*53ee8cc1Swenshuai.xi /// @param <RET>        \b None :
818*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
819*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_VDBen(PWM_ChNum index,MS_BOOL bVdbenPWM)820*53ee8cc1Swenshuai.xi void HAL_PWM_VDBen(PWM_ChNum index, MS_BOOL bVdbenPWM)
821*53ee8cc1Swenshuai.xi {
822*53ee8cc1Swenshuai.xi     _gPWM_VDBen = bVdbenPWM;
823*53ee8cc1Swenshuai.xi 
824*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
825*53ee8cc1Swenshuai.xi 
826*53ee8cc1Swenshuai.xi     switch(index)
827*53ee8cc1Swenshuai.xi     {
828*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
829*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM0_VDBEN,BITS(9:9,bVdbenPWM),BMASK(9:9));
830*53ee8cc1Swenshuai.xi             break;
831*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
832*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM1_VDBEN,BITS(9:9,bVdbenPWM),BMASK(9:9));
833*53ee8cc1Swenshuai.xi             break;
834*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
835*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM2_VDBEN,BITS(9:9,bVdbenPWM),BMASK(9:9));
836*53ee8cc1Swenshuai.xi             break;
837*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
838*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM3_VDBEN,BITS(9:9,bVdbenPWM),BMASK(9:9));
839*53ee8cc1Swenshuai.xi             break;
840*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
841*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM4_VDBEN,BITS(9:9,bVdbenPWM),BMASK(9:9));
842*53ee8cc1Swenshuai.xi             break;
843*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
844*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
845*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
846*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
847*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
848*53ee8cc1Swenshuai.xi 	    printf("[Utopia] The PWM%d is not support\n", (int)index);
849*53ee8cc1Swenshuai.xi             UNUSED(bVdbenPWM);
850*53ee8cc1Swenshuai.xi             break;
851*53ee8cc1Swenshuai.xi 		default:
852*53ee8cc1Swenshuai.xi 			break;
853*53ee8cc1Swenshuai.xi     }
854*53ee8cc1Swenshuai.xi 
855*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
856*53ee8cc1Swenshuai.xi }
857*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
858*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_GetVDBen
859*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description :Get the Vsync Double buffer of the specific pwm
860*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the PWM CH
861*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
862*53ee8cc1Swenshuai.xi /// @param <RET>        \b MS_BOOL : 1 for enable; 0 for disable
863*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
864*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_GetVDBen(PWM_ChNum index)865*53ee8cc1Swenshuai.xi MS_BOOL HAL_PWM_GetVDBen(PWM_ChNum index)
866*53ee8cc1Swenshuai.xi {
867*53ee8cc1Swenshuai.xi     MS_BOOL bVdbenPWM = FALSE;
868*53ee8cc1Swenshuai.xi 
869*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
870*53ee8cc1Swenshuai.xi 
871*53ee8cc1Swenshuai.xi     switch(index)
872*53ee8cc1Swenshuai.xi     {
873*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
874*53ee8cc1Swenshuai.xi             bVdbenPWM = (HAL_PWM_Read2Byte(REG_PWM0_VDBEN) & BMASK(9:9)) >> 9;
875*53ee8cc1Swenshuai.xi             break;
876*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
877*53ee8cc1Swenshuai.xi             bVdbenPWM = (HAL_PWM_Read2Byte(REG_PWM1_VDBEN) & BMASK(9:9)) >> 9;
878*53ee8cc1Swenshuai.xi             break;
879*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
880*53ee8cc1Swenshuai.xi             bVdbenPWM = (HAL_PWM_Read2Byte(REG_PWM2_VDBEN) & BMASK(9:9)) >> 9;
881*53ee8cc1Swenshuai.xi             break;
882*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
883*53ee8cc1Swenshuai.xi             bVdbenPWM = (HAL_PWM_Read2Byte(REG_PWM3_VDBEN) & BMASK(9:9)) >> 9;
884*53ee8cc1Swenshuai.xi             break;
885*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
886*53ee8cc1Swenshuai.xi             bVdbenPWM = (HAL_PWM_Read2Byte(REG_PWM4_VDBEN) & BMASK(9:9)) >> 9;
887*53ee8cc1Swenshuai.xi             break;
888*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
889*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
890*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
891*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
892*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
893*53ee8cc1Swenshuai.xi 	        printf("[Utopia] The PWM%d is not support\n", (int)index);
894*53ee8cc1Swenshuai.xi             break;
895*53ee8cc1Swenshuai.xi 		default:
896*53ee8cc1Swenshuai.xi 			break;
897*53ee8cc1Swenshuai.xi     }
898*53ee8cc1Swenshuai.xi 
899*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
900*53ee8cc1Swenshuai.xi     return bVdbenPWM;
901*53ee8cc1Swenshuai.xi }
902*53ee8cc1Swenshuai.xi 
903*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
904*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_Vrest
905*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description : Set the Hsync reset of the specific pwm
906*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the PWM CH
907*53ee8cc1Swenshuai.xi /// @param <IN>          \b MS_BOOL : 1 for enable; 0 for disable
908*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
909*53ee8cc1Swenshuai.xi /// @param <RET>        \b None :
910*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
911*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_Vrest(PWM_ChNum index,MS_BOOL bRstPWM)912*53ee8cc1Swenshuai.xi void HAL_PWM_Vrest(PWM_ChNum index, MS_BOOL bRstPWM)
913*53ee8cc1Swenshuai.xi {
914*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
915*53ee8cc1Swenshuai.xi 
916*53ee8cc1Swenshuai.xi     switch(index)
917*53ee8cc1Swenshuai.xi     {
918*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
919*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM0_RESET_EN,BITS(10:10,bRstPWM),BMASK(10:10));
920*53ee8cc1Swenshuai.xi             break;
921*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
922*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM1_RESET_EN,BITS(10:10,bRstPWM),BMASK(10:10));
923*53ee8cc1Swenshuai.xi             break;
924*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
925*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM2_RESET_EN,BITS(10:10,bRstPWM),BMASK(10:10));
926*53ee8cc1Swenshuai.xi             break;
927*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
928*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM3_RESET_EN,BITS(10:10,bRstPWM),BMASK(10:10));
929*53ee8cc1Swenshuai.xi             break;
930*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
931*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM4_RESET_EN,BITS(10:10,bRstPWM),BMASK(10:10));
932*53ee8cc1Swenshuai.xi             break;
933*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
934*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
935*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
936*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
937*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
938*53ee8cc1Swenshuai.xi 	    printf("[Utopia] The PWM%d is not support\n", (int)index);
939*53ee8cc1Swenshuai.xi             UNUSED(bRstPWM);
940*53ee8cc1Swenshuai.xi             break;
941*53ee8cc1Swenshuai.xi 		default:
942*53ee8cc1Swenshuai.xi 			break;
943*53ee8cc1Swenshuai.xi     }
944*53ee8cc1Swenshuai.xi 
945*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
946*53ee8cc1Swenshuai.xi }
947*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
948*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_GetVrest
949*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description :Get the Hsync reset of the specific pwm
950*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the PWM CH
951*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
952*53ee8cc1Swenshuai.xi /// @param <RET>        \b MS_BOOL : 1 for enable; 0 for disable
953*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
954*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_GetVrest(PWM_ChNum index)955*53ee8cc1Swenshuai.xi MS_BOOL HAL_PWM_GetVrest(PWM_ChNum index)
956*53ee8cc1Swenshuai.xi {
957*53ee8cc1Swenshuai.xi     MS_BOOL bRstPWM = 0;
958*53ee8cc1Swenshuai.xi 
959*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
960*53ee8cc1Swenshuai.xi 
961*53ee8cc1Swenshuai.xi     switch(index)
962*53ee8cc1Swenshuai.xi     {
963*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
964*53ee8cc1Swenshuai.xi             bRstPWM = (HAL_PWM_Read2Byte(REG_PWM0_RESET_EN) & BMASK(10:10)) >> 10;
965*53ee8cc1Swenshuai.xi             break;
966*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
967*53ee8cc1Swenshuai.xi             bRstPWM = (HAL_PWM_Read2Byte(REG_PWM1_RESET_EN) & BMASK(10:10)) >> 10;
968*53ee8cc1Swenshuai.xi             break;
969*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
970*53ee8cc1Swenshuai.xi             bRstPWM = (HAL_PWM_Read2Byte(REG_PWM2_RESET_EN) & BMASK(10:10)) >> 10;
971*53ee8cc1Swenshuai.xi             break;
972*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
973*53ee8cc1Swenshuai.xi             bRstPWM = (HAL_PWM_Read2Byte(REG_PWM3_RESET_EN) & BMASK(10:10)) >> 10;
974*53ee8cc1Swenshuai.xi             break;
975*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
976*53ee8cc1Swenshuai.xi             bRstPWM = (HAL_PWM_Read2Byte(REG_PWM4_RESET_EN) & BMASK(10:10)) >> 10;
977*53ee8cc1Swenshuai.xi             break;
978*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
979*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
980*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
981*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
982*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
983*53ee8cc1Swenshuai.xi 	        printf("[Utopia] The PWM%d is not support\n", (int)index);
984*53ee8cc1Swenshuai.xi             break;
985*53ee8cc1Swenshuai.xi 		default:
986*53ee8cc1Swenshuai.xi 			break;
987*53ee8cc1Swenshuai.xi     }
988*53ee8cc1Swenshuai.xi 
989*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
990*53ee8cc1Swenshuai.xi     return bRstPWM;
991*53ee8cc1Swenshuai.xi }
992*53ee8cc1Swenshuai.xi 
993*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
994*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_DBen
995*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description : Set the Double buffer of the specific pwm
996*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the PWM CH
997*53ee8cc1Swenshuai.xi /// @param <IN>          \b MS_BOOL : 1 for enable; 0 for disable
998*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
999*53ee8cc1Swenshuai.xi /// @param <RET>        \b None :
1000*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
1001*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_DBen(PWM_ChNum index,MS_BOOL bdbenPWM)1002*53ee8cc1Swenshuai.xi void HAL_PWM_DBen(PWM_ChNum index, MS_BOOL bdbenPWM)
1003*53ee8cc1Swenshuai.xi {
1004*53ee8cc1Swenshuai.xi 	//_gPWM_DBen = bdbenPWM;
1005*53ee8cc1Swenshuai.xi 
1006*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
1007*53ee8cc1Swenshuai.xi 
1008*53ee8cc1Swenshuai.xi     switch(index)
1009*53ee8cc1Swenshuai.xi     {
1010*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
1011*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM0_DBEN,BITS(11:11,bdbenPWM),BMASK(11:11));
1012*53ee8cc1Swenshuai.xi             break;
1013*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
1014*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM1_DBEN,BITS(11:11,bdbenPWM),BMASK(11:11));
1015*53ee8cc1Swenshuai.xi             break;
1016*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
1017*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM2_DBEN,BITS(11:11,bdbenPWM),BMASK(11:11));
1018*53ee8cc1Swenshuai.xi             break;
1019*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
1020*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM3_DBEN,BITS(11:11,bdbenPWM),BMASK(11:11));
1021*53ee8cc1Swenshuai.xi             break;
1022*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
1023*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM4_DBEN,BITS(11:11,bdbenPWM),BMASK(11:11));
1024*53ee8cc1Swenshuai.xi             break;
1025*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
1026*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
1027*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
1028*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
1029*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
1030*53ee8cc1Swenshuai.xi 	    printf("[Utopia] The PWM%d is not support\n", (int)index);
1031*53ee8cc1Swenshuai.xi             UNUSED(bdbenPWM);
1032*53ee8cc1Swenshuai.xi             break;
1033*53ee8cc1Swenshuai.xi 		default:
1034*53ee8cc1Swenshuai.xi 			break;
1035*53ee8cc1Swenshuai.xi     }
1036*53ee8cc1Swenshuai.xi 
1037*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
1038*53ee8cc1Swenshuai.xi }
1039*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
1040*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_GetDBen
1041*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description : Get the Double buffer of the specific pwm
1042*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the PWM CH
1043*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
1044*53ee8cc1Swenshuai.xi /// @param <RET>        \b None :
1045*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
1046*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_GetDBen(PWM_ChNum index)1047*53ee8cc1Swenshuai.xi MS_BOOL HAL_PWM_GetDBen(PWM_ChNum index)
1048*53ee8cc1Swenshuai.xi {
1049*53ee8cc1Swenshuai.xi     MS_BOOL bdbenPWM = FALSE;
1050*53ee8cc1Swenshuai.xi 
1051*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
1052*53ee8cc1Swenshuai.xi 
1053*53ee8cc1Swenshuai.xi     switch(index)
1054*53ee8cc1Swenshuai.xi     {
1055*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
1056*53ee8cc1Swenshuai.xi             bdbenPWM = (HAL_PWM_Read2Byte(REG_PWM0_DBEN) & BMASK(11:11)) >> 11;
1057*53ee8cc1Swenshuai.xi             break;
1058*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
1059*53ee8cc1Swenshuai.xi             bdbenPWM = (HAL_PWM_Read2Byte(REG_PWM1_DBEN) & BMASK(11:11)) >> 11;
1060*53ee8cc1Swenshuai.xi             break;
1061*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
1062*53ee8cc1Swenshuai.xi             bdbenPWM = (HAL_PWM_Read2Byte(REG_PWM2_DBEN) & BMASK(11:11)) >> 11;
1063*53ee8cc1Swenshuai.xi             break;
1064*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
1065*53ee8cc1Swenshuai.xi             bdbenPWM = (HAL_PWM_Read2Byte(REG_PWM3_DBEN) & BMASK(11:11)) >> 11;
1066*53ee8cc1Swenshuai.xi             break;
1067*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
1068*53ee8cc1Swenshuai.xi             bdbenPWM = (HAL_PWM_Read2Byte(REG_PWM4_DBEN) & BMASK(11:11)) >> 11;
1069*53ee8cc1Swenshuai.xi             break;
1070*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
1071*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
1072*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
1073*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
1074*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
1075*53ee8cc1Swenshuai.xi             printf("[Utopia] The PWM%d is not support\n", (int)index);
1076*53ee8cc1Swenshuai.xi             break;
1077*53ee8cc1Swenshuai.xi 		default:
1078*53ee8cc1Swenshuai.xi 			break;
1079*53ee8cc1Swenshuai.xi     }
1080*53ee8cc1Swenshuai.xi 
1081*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
1082*53ee8cc1Swenshuai.xi 
1083*53ee8cc1Swenshuai.xi     return bdbenPWM;
1084*53ee8cc1Swenshuai.xi }
1085*53ee8cc1Swenshuai.xi 
HAL_PWM_IMPULSE_EN(PWM_ChNum index,MS_BOOL bdbenPWM)1086*53ee8cc1Swenshuai.xi void HAL_PWM_IMPULSE_EN(PWM_ChNum index, MS_BOOL bdbenPWM)
1087*53ee8cc1Swenshuai.xi {
1088*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
1089*53ee8cc1Swenshuai.xi 
1090*53ee8cc1Swenshuai.xi     switch(index)
1091*53ee8cc1Swenshuai.xi     {
1092*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
1093*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM0_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1094*53ee8cc1Swenshuai.xi             break;
1095*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
1096*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM1_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1097*53ee8cc1Swenshuai.xi             break;
1098*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
1099*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM2_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1100*53ee8cc1Swenshuai.xi             break;
1101*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
1102*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM3_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1103*53ee8cc1Swenshuai.xi             break;
1104*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
1105*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM4_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1106*53ee8cc1Swenshuai.xi             break;
1107*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
1108*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM5_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1109*53ee8cc1Swenshuai.xi             break;
1110*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
1111*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM6_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1112*53ee8cc1Swenshuai.xi             break;
1113*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
1114*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM7_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1115*53ee8cc1Swenshuai.xi             break;
1116*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
1117*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM8_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1118*53ee8cc1Swenshuai.xi             break;
1119*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
1120*53ee8cc1Swenshuai.xi             UNUSED(bdbenPWM);
1121*53ee8cc1Swenshuai.xi             break;
1122*53ee8cc1Swenshuai.xi 		default:
1123*53ee8cc1Swenshuai.xi 			break;
1124*53ee8cc1Swenshuai.xi     }
1125*53ee8cc1Swenshuai.xi 
1126*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
1127*53ee8cc1Swenshuai.xi }
1128*53ee8cc1Swenshuai.xi 
1129*53ee8cc1Swenshuai.xi 
HAL_PWM_ODDEVEN_SYNC(PWM_ChNum index,MS_BOOL bdbenPWM)1130*53ee8cc1Swenshuai.xi void HAL_PWM_ODDEVEN_SYNC(PWM_ChNum index, MS_BOOL bdbenPWM)
1131*53ee8cc1Swenshuai.xi {
1132*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
1133*53ee8cc1Swenshuai.xi 
1134*53ee8cc1Swenshuai.xi     switch(index)
1135*53ee8cc1Swenshuai.xi     {
1136*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
1137*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM0_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1138*53ee8cc1Swenshuai.xi             break;
1139*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
1140*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM1_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1141*53ee8cc1Swenshuai.xi             break;
1142*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
1143*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM2_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1144*53ee8cc1Swenshuai.xi             break;
1145*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
1146*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM3_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1147*53ee8cc1Swenshuai.xi             break;
1148*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
1149*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM4_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1150*53ee8cc1Swenshuai.xi             break;
1151*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
1152*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM5_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1153*53ee8cc1Swenshuai.xi             break;
1154*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
1155*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM6_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1156*53ee8cc1Swenshuai.xi             break;
1157*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
1158*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM7_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1159*53ee8cc1Swenshuai.xi             break;
1160*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
1161*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_PWM8_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1162*53ee8cc1Swenshuai.xi             break;
1163*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
1164*53ee8cc1Swenshuai.xi             UNUSED(bdbenPWM);
1165*53ee8cc1Swenshuai.xi             break;
1166*53ee8cc1Swenshuai.xi 		default:
1167*53ee8cc1Swenshuai.xi 			break;
1168*53ee8cc1Swenshuai.xi     }
1169*53ee8cc1Swenshuai.xi 
1170*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
1171*53ee8cc1Swenshuai.xi }
1172*53ee8cc1Swenshuai.xi 
1173*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
1174*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_RstMux
1175*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description : Set the Rst Mux of the specific pwm
1176*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the PWM CH
1177*53ee8cc1Swenshuai.xi /// @param <IN>          \b MS_BOOL : 1 for Hsync; 0 for Vsync
1178*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
1179*53ee8cc1Swenshuai.xi /// @param <RET>        \b None :
1180*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
1181*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_RstMux(PWM_ChNum index,MS_BOOL bMuxPWM)1182*53ee8cc1Swenshuai.xi void HAL_PWM_RstMux(PWM_ChNum index, MS_BOOL bMuxPWM)
1183*53ee8cc1Swenshuai.xi {
1184*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
1185*53ee8cc1Swenshuai.xi 
1186*53ee8cc1Swenshuai.xi     switch(index)
1187*53ee8cc1Swenshuai.xi     {
1188*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
1189*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_RST_MUX0,BITS(15:15,bMuxPWM),BMASK(15:15));
1190*53ee8cc1Swenshuai.xi             break;
1191*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
1192*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_RST_MUX1,BITS(7:7,bMuxPWM),BMASK(7:7));
1193*53ee8cc1Swenshuai.xi             break;
1194*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
1195*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_RST_MUX2,BITS(15:15,bMuxPWM),BMASK(15:15));
1196*53ee8cc1Swenshuai.xi             break;
1197*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
1198*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_RST_MUX3,BITS(7:7,bMuxPWM),BMASK(7:7));
1199*53ee8cc1Swenshuai.xi             break;
1200*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
1201*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_RST_MUX4,BITS(15:15,bMuxPWM),BMASK(15:15));
1202*53ee8cc1Swenshuai.xi             break;
1203*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
1204*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
1205*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
1206*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
1207*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
1208*53ee8cc1Swenshuai.xi 	    printf("[Utopia] The PWM%d is not support\n", (int)index);
1209*53ee8cc1Swenshuai.xi             UNUSED(bMuxPWM);
1210*53ee8cc1Swenshuai.xi             break;
1211*53ee8cc1Swenshuai.xi 		default:
1212*53ee8cc1Swenshuai.xi 			break;
1213*53ee8cc1Swenshuai.xi     }
1214*53ee8cc1Swenshuai.xi 
1215*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
1216*53ee8cc1Swenshuai.xi }
1217*53ee8cc1Swenshuai.xi 
1218*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
1219*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_RstCnt
1220*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description : Set the Rst_Cnt of the specific pwm
1221*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the PWM CH
1222*53ee8cc1Swenshuai.xi /// @param <IN>          \b MS_U8 : u8RstCntPWM
1223*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
1224*53ee8cc1Swenshuai.xi /// @param <RET>        \b None :
1225*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
1226*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_RstCnt(PWM_ChNum index,MS_U8 u8RstCntPWM)1227*53ee8cc1Swenshuai.xi void HAL_PWM_RstCnt(PWM_ChNum index, MS_U8 u8RstCntPWM)
1228*53ee8cc1Swenshuai.xi {
1229*53ee8cc1Swenshuai.xi 	if( u8RstCntPWM & 0x10 )
1230*53ee8cc1Swenshuai.xi 	{
1231*53ee8cc1Swenshuai.xi 		printf("PWM%d Reset Count is too large\n", index);
1232*53ee8cc1Swenshuai.xi 	}
1233*53ee8cc1Swenshuai.xi 
1234*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
1235*53ee8cc1Swenshuai.xi     /* the Hsync reset counter capability is restricted to ONLY 4-bit */
1236*53ee8cc1Swenshuai.xi     switch(index)
1237*53ee8cc1Swenshuai.xi     {
1238*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
1239*53ee8cc1Swenshuai.xi 	    HAL_PWM_WriteRegBit(REG_HS_RST_CNT0,BITS(11:8,u8RstCntPWM),BMASK(11:8));
1240*53ee8cc1Swenshuai.xi             break;
1241*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
1242*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_HS_RST_CNT1,BITS(3:0,u8RstCntPWM),BMASK(3:0));
1243*53ee8cc1Swenshuai.xi             break;
1244*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
1245*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_HS_RST_CNT2,BITS(11:8,u8RstCntPWM),BMASK(11:8));
1246*53ee8cc1Swenshuai.xi             break;
1247*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
1248*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_HS_RST_CNT3,BITS(3:0,u8RstCntPWM),BMASK(3:0));
1249*53ee8cc1Swenshuai.xi             break;
1250*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
1251*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_HS_RST_CNT4,BITS(11:8,u8RstCntPWM),BMASK(11:8));
1252*53ee8cc1Swenshuai.xi             break;
1253*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
1254*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
1255*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
1256*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
1257*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
1258*53ee8cc1Swenshuai.xi 	    printf("[Utopia] The PWM%d is not support\n", (int)index);
1259*53ee8cc1Swenshuai.xi             UNUSED(u8RstCntPWM);
1260*53ee8cc1Swenshuai.xi             break;
1261*53ee8cc1Swenshuai.xi 		default:
1262*53ee8cc1Swenshuai.xi 			break;
1263*53ee8cc1Swenshuai.xi     }
1264*53ee8cc1Swenshuai.xi 
1265*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
1266*53ee8cc1Swenshuai.xi }
1267*53ee8cc1Swenshuai.xi 
1268*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
1269*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_BypassUnit
1270*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description : Set the Bypass Unit of the specific pwm
1271*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the PWM CH
1272*53ee8cc1Swenshuai.xi /// @param <IN>          \b MS_BOOL : 1 for enable; 0 for disable
1273*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
1274*53ee8cc1Swenshuai.xi /// @param <RET>        \b None :
1275*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
1276*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_BypassUnit(PWM_ChNum index,MS_BOOL bBypassPWM)1277*53ee8cc1Swenshuai.xi void HAL_PWM_BypassUnit(PWM_ChNum index, MS_BOOL bBypassPWM)
1278*53ee8cc1Swenshuai.xi {
1279*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
1280*53ee8cc1Swenshuai.xi 
1281*53ee8cc1Swenshuai.xi     //T2 ONLY
1282*53ee8cc1Swenshuai.xi 
1283*53ee8cc1Swenshuai.xi     switch(index)
1284*53ee8cc1Swenshuai.xi     {
1285*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
1286*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
1287*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
1288*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
1289*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
1290*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
1291*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
1292*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
1293*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
1294*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
1295*53ee8cc1Swenshuai.xi 			printf("[Utopia] The PWM%d is not support\n", (int)index);
1296*53ee8cc1Swenshuai.xi             UNUSED(bBypassPWM);
1297*53ee8cc1Swenshuai.xi             break;
1298*53ee8cc1Swenshuai.xi 		default:
1299*53ee8cc1Swenshuai.xi 			break;
1300*53ee8cc1Swenshuai.xi     }
1301*53ee8cc1Swenshuai.xi 
1302*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
1303*53ee8cc1Swenshuai.xi }
1304*53ee8cc1Swenshuai.xi 
1305*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
1306*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM01_CntMode
1307*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description :  Counter mode for PWM0 and PWM1
1308*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the Counter mode
1309*53ee8cc1Swenshuai.xi /// @param <IN>          \b None :
1310*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
1311*53ee8cc1Swenshuai.xi /// @param <RET>        \b PWM_Result :
1312*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
1313*53ee8cc1Swenshuai.xi /// @note                                                       \n
1314*53ee8cc1Swenshuai.xi ///     11: PWM1 donate internal divider to PWM0   \n
1315*53ee8cc1Swenshuai.xi ///     10: PWM0 donate internal divider to PWM1   \n
1316*53ee8cc1Swenshuai.xi ///     0x: Normal mode                                      \n
1317*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM01_CntMode(PWM_CntMode CntMode)1318*53ee8cc1Swenshuai.xi MS_BOOL HAL_PWM01_CntMode(PWM_CntMode CntMode)
1319*53ee8cc1Swenshuai.xi {
1320*53ee8cc1Swenshuai.xi     MS_BOOL ret = FALSE;
1321*53ee8cc1Swenshuai.xi     //T2 ONLY
1322*53ee8cc1Swenshuai.xi     UNUSED(CntMode);
1323*53ee8cc1Swenshuai.xi     return ret;
1324*53ee8cc1Swenshuai.xi }
1325*53ee8cc1Swenshuai.xi 
1326*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
1327*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM23_CntMode
1328*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description :  Counter mode for PWM2 and PWM3
1329*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the Counter mode
1330*53ee8cc1Swenshuai.xi /// @param <IN>          \b None :
1331*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
1332*53ee8cc1Swenshuai.xi /// @param <RET>        \b PWM_Result :
1333*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
1334*53ee8cc1Swenshuai.xi /// @note                                                       \n
1335*53ee8cc1Swenshuai.xi ///     11: PWM3 donate internal divider to PWM2   \n
1336*53ee8cc1Swenshuai.xi ///     10: PWM2 donate internal divider to PWM3   \n
1337*53ee8cc1Swenshuai.xi ///     0x: Normal mode                                      \n
1338*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM23_CntMode(PWM_CntMode CntMode)1339*53ee8cc1Swenshuai.xi MS_BOOL HAL_PWM23_CntMode(PWM_CntMode CntMode)
1340*53ee8cc1Swenshuai.xi {
1341*53ee8cc1Swenshuai.xi     MS_BOOL ret = FALSE;
1342*53ee8cc1Swenshuai.xi     //T2 ONLY
1343*53ee8cc1Swenshuai.xi     UNUSED(CntMode);
1344*53ee8cc1Swenshuai.xi     return ret;
1345*53ee8cc1Swenshuai.xi }
1346*53ee8cc1Swenshuai.xi 
1347*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
1348*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM67_CntMode
1349*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description :  Counter mode for PWM6 and PWM7
1350*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the Counter mode
1351*53ee8cc1Swenshuai.xi /// @param <IN>          \b None :
1352*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
1353*53ee8cc1Swenshuai.xi /// @param <RET>        \b PWM_Result :
1354*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
1355*53ee8cc1Swenshuai.xi /// @note                                                       \n
1356*53ee8cc1Swenshuai.xi ///     11: PWM7 donate internal divider to PWM6   \n
1357*53ee8cc1Swenshuai.xi ///     10: PWM6 donate internal divider to PWM7   \n
1358*53ee8cc1Swenshuai.xi ///     0x: Normal mode                                      \n
1359*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM67_CntMode(PWM_CntMode CntMode)1360*53ee8cc1Swenshuai.xi MS_BOOL HAL_PWM67_CntMode(PWM_CntMode CntMode)
1361*53ee8cc1Swenshuai.xi {
1362*53ee8cc1Swenshuai.xi     MS_BOOL ret = FALSE;
1363*53ee8cc1Swenshuai.xi     //T2 ONLY
1364*53ee8cc1Swenshuai.xi     UNUSED(CntMode);
1365*53ee8cc1Swenshuai.xi     return ret;
1366*53ee8cc1Swenshuai.xi }
1367*53ee8cc1Swenshuai.xi 
1368*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
1369*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_Shift
1370*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description : Set the Shift of the specific pwm
1371*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the PWM CH
1372*53ee8cc1Swenshuai.xi /// @param <IN>          \b MS_U16 : the 18-bit shift value
1373*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
1374*53ee8cc1Swenshuai.xi /// @param <RET>        \b None :
1375*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
1376*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_Shift(PWM_ChNum index,MS_U32 u32ShiftPWM)1377*53ee8cc1Swenshuai.xi MS_BOOL HAL_PWM_Shift(PWM_ChNum index, MS_U32 u32ShiftPWM)
1378*53ee8cc1Swenshuai.xi {
1379*53ee8cc1Swenshuai.xi     MS_U16 Shift_L, Shift_H;
1380*53ee8cc1Swenshuai.xi 
1381*53ee8cc1Swenshuai.xi     Shift_L = (MS_U16)(u32ShiftPWM & 0xFFFF);
1382*53ee8cc1Swenshuai.xi     Shift_H = (MS_U16)(u32ShiftPWM >> 16);
1383*53ee8cc1Swenshuai.xi 
1384*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
1385*53ee8cc1Swenshuai.xi 
1386*53ee8cc1Swenshuai.xi     switch(index)
1387*53ee8cc1Swenshuai.xi     {
1388*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
1389*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM0_SHIFT_L, Shift_L);
1390*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM0_SHIFT_H, Shift_H);
1391*53ee8cc1Swenshuai.xi             break;
1392*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
1393*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM1_SHIFT_L, Shift_L);
1394*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM1_SHIFT_H, Shift_H);
1395*53ee8cc1Swenshuai.xi             break;
1396*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
1397*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM2_SHIFT_L, Shift_L);
1398*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM2_SHIFT_H, Shift_H);
1399*53ee8cc1Swenshuai.xi             break;
1400*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
1401*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM3_SHIFT_L, Shift_L);
1402*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM3_SHIFT_H, Shift_H);
1403*53ee8cc1Swenshuai.xi             break;
1404*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
1405*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM4_SHIFT_L, Shift_L);
1406*53ee8cc1Swenshuai.xi             HAL_PWM_Write2Byte(REG_PWM4_SHIFT_H, Shift_H);
1407*53ee8cc1Swenshuai.xi             break;
1408*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
1409*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
1410*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
1411*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
1412*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
1413*53ee8cc1Swenshuai.xi 			printf("[Utopia] The PWM%d is not support\n", (int)index);
1414*53ee8cc1Swenshuai.xi             UNUSED(Shift_L);UNUSED(Shift_H);
1415*53ee8cc1Swenshuai.xi             break;
1416*53ee8cc1Swenshuai.xi 		default:
1417*53ee8cc1Swenshuai.xi 			break;
1418*53ee8cc1Swenshuai.xi     }
1419*53ee8cc1Swenshuai.xi 
1420*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
1421*53ee8cc1Swenshuai.xi 
1422*53ee8cc1Swenshuai.xi     return TRUE;
1423*53ee8cc1Swenshuai.xi }
1424*53ee8cc1Swenshuai.xi 
1425*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
1426*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_GetShift
1427*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description : Set the Shift of the specific pwm
1428*53ee8cc1Swenshuai.xi /// @param <IN>          \b PWM_ChNum : Enum of the PWM CH
1429*53ee8cc1Swenshuai.xi /// @param <IN>          \b MS_U16 : the 18-bit shift value
1430*53ee8cc1Swenshuai.xi /// @param <OUT>       \b None :
1431*53ee8cc1Swenshuai.xi /// @param <RET>        \b MS_U16 : the 18-bit shift value
1432*53ee8cc1Swenshuai.xi /// @param <GLOBAL>   \b None :
1433*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_GetShift(PWM_ChNum index)1434*53ee8cc1Swenshuai.xi MS_U32 HAL_PWM_GetShift(PWM_ChNum index)
1435*53ee8cc1Swenshuai.xi {
1436*53ee8cc1Swenshuai.xi     MS_U16 Shift_L = 0, Shift_H = 0;
1437*53ee8cc1Swenshuai.xi 
1438*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
1439*53ee8cc1Swenshuai.xi 
1440*53ee8cc1Swenshuai.xi     switch(index)
1441*53ee8cc1Swenshuai.xi     {
1442*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
1443*53ee8cc1Swenshuai.xi             Shift_L = HAL_PWM_Read2Byte(REG_PWM0_SHIFT_L);
1444*53ee8cc1Swenshuai.xi             Shift_H = HAL_PWM_Read2Byte(REG_PWM0_SHIFT_H);
1445*53ee8cc1Swenshuai.xi             break;
1446*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
1447*53ee8cc1Swenshuai.xi             Shift_L = HAL_PWM_Read2Byte(REG_PWM1_SHIFT_L);
1448*53ee8cc1Swenshuai.xi             Shift_H = HAL_PWM_Read2Byte(REG_PWM1_SHIFT_H);
1449*53ee8cc1Swenshuai.xi             break;
1450*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
1451*53ee8cc1Swenshuai.xi             Shift_L = HAL_PWM_Read2Byte(REG_PWM2_SHIFT_L);
1452*53ee8cc1Swenshuai.xi             Shift_H = HAL_PWM_Read2Byte(REG_PWM2_SHIFT_H);
1453*53ee8cc1Swenshuai.xi             break;
1454*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
1455*53ee8cc1Swenshuai.xi             Shift_L = HAL_PWM_Read2Byte(REG_PWM3_SHIFT_L);
1456*53ee8cc1Swenshuai.xi             Shift_H = HAL_PWM_Read2Byte(REG_PWM3_SHIFT_H);
1457*53ee8cc1Swenshuai.xi             break;
1458*53ee8cc1Swenshuai.xi         case E_PWM_CH4:
1459*53ee8cc1Swenshuai.xi             Shift_L = HAL_PWM_Read2Byte(REG_PWM4_SHIFT_L);
1460*53ee8cc1Swenshuai.xi             Shift_H = HAL_PWM_Read2Byte(REG_PWM4_SHIFT_H);
1461*53ee8cc1Swenshuai.xi             break;
1462*53ee8cc1Swenshuai.xi         case E_PWM_CH5:
1463*53ee8cc1Swenshuai.xi         case E_PWM_CH6:
1464*53ee8cc1Swenshuai.xi         case E_PWM_CH7:
1465*53ee8cc1Swenshuai.xi         case E_PWM_CH8:
1466*53ee8cc1Swenshuai.xi         case E_PWM_CH9:
1467*53ee8cc1Swenshuai.xi 			printf("[Utopia] The PWM%d is not support\n", (int)index);
1468*53ee8cc1Swenshuai.xi             break;
1469*53ee8cc1Swenshuai.xi 		default:
1470*53ee8cc1Swenshuai.xi 			break;
1471*53ee8cc1Swenshuai.xi     }
1472*53ee8cc1Swenshuai.xi 
1473*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
1474*53ee8cc1Swenshuai.xi 
1475*53ee8cc1Swenshuai.xi     return ((Shift_H<<16) | Shift_L);
1476*53ee8cc1Swenshuai.xi }
1477*53ee8cc1Swenshuai.xi 
HAL_PWM_Nvsync(PWM_ChNum index,MS_BOOL bNvsPWM)1478*53ee8cc1Swenshuai.xi void HAL_PWM_Nvsync(PWM_ChNum index, MS_BOOL bNvsPWM)
1479*53ee8cc1Swenshuai.xi     {
1480*53ee8cc1Swenshuai.xi 
1481*53ee8cc1Swenshuai.xi         HAL_SUBBANK1;
1482*53ee8cc1Swenshuai.xi 
1483*53ee8cc1Swenshuai.xi         switch(index)
1484*53ee8cc1Swenshuai.xi         {
1485*53ee8cc1Swenshuai.xi             case E_PWM_CH0:
1486*53ee8cc1Swenshuai.xi                 HAL_PWM_WriteRegBit(REG_PWM0_NVS,BITS(0:0,bNvsPWM),BMASK(0:0));
1487*53ee8cc1Swenshuai.xi                 break;
1488*53ee8cc1Swenshuai.xi             case E_PWM_CH1:
1489*53ee8cc1Swenshuai.xi                 HAL_PWM_WriteRegBit(REG_PWM1_NVS,BITS(1:1,bNvsPWM),BMASK(1:1));
1490*53ee8cc1Swenshuai.xi                 break;
1491*53ee8cc1Swenshuai.xi             case E_PWM_CH2:
1492*53ee8cc1Swenshuai.xi                 HAL_PWM_WriteRegBit(REG_PWM2_NVS,BITS(2:2,bNvsPWM),BMASK(2:2));
1493*53ee8cc1Swenshuai.xi                 break;
1494*53ee8cc1Swenshuai.xi             case E_PWM_CH3:
1495*53ee8cc1Swenshuai.xi                 HAL_PWM_WriteRegBit(REG_PWM3_NVS,BITS(3:3,bNvsPWM),BMASK(3:3));
1496*53ee8cc1Swenshuai.xi                 break;
1497*53ee8cc1Swenshuai.xi             case E_PWM_CH4:
1498*53ee8cc1Swenshuai.xi                 HAL_PWM_WriteRegBit(REG_PWM4_NVS,BITS(4:4,bNvsPWM),BMASK(4:4));
1499*53ee8cc1Swenshuai.xi                 break;
1500*53ee8cc1Swenshuai.xi             case E_PWM_CH5:
1501*53ee8cc1Swenshuai.xi             case E_PWM_CH6:
1502*53ee8cc1Swenshuai.xi             case E_PWM_CH7:
1503*53ee8cc1Swenshuai.xi             case E_PWM_CH8:
1504*53ee8cc1Swenshuai.xi             case E_PWM_CH9:
1505*53ee8cc1Swenshuai.xi             printf("[Utopia] The PWM%d is not support\n", (int)index);
1506*53ee8cc1Swenshuai.xi                 UNUSED(bNvsPWM);
1507*53ee8cc1Swenshuai.xi                 break;
1508*53ee8cc1Swenshuai.xi             default:
1509*53ee8cc1Swenshuai.xi                 break;
1510*53ee8cc1Swenshuai.xi         }
1511*53ee8cc1Swenshuai.xi 
1512*53ee8cc1Swenshuai.xi         HAL_SUBBANK0;
1513*53ee8cc1Swenshuai.xi     }
1514*53ee8cc1Swenshuai.xi 
HAL_PWM_Align(PWM_ChNum index,MS_BOOL bAliPWM)1515*53ee8cc1Swenshuai.xi void HAL_PWM_Align(PWM_ChNum index, MS_BOOL bAliPWM)
1516*53ee8cc1Swenshuai.xi     {
1517*53ee8cc1Swenshuai.xi 
1518*53ee8cc1Swenshuai.xi         HAL_SUBBANK1;
1519*53ee8cc1Swenshuai.xi 
1520*53ee8cc1Swenshuai.xi         switch(index)
1521*53ee8cc1Swenshuai.xi         {
1522*53ee8cc1Swenshuai.xi             case E_PWM_CH0:
1523*53ee8cc1Swenshuai.xi                 HAL_PWM_WriteRegBit(REG_PWM0_Align,BITS(0:0,bAliPWM),BMASK(0:0));
1524*53ee8cc1Swenshuai.xi                 break;
1525*53ee8cc1Swenshuai.xi             case E_PWM_CH1:
1526*53ee8cc1Swenshuai.xi                 HAL_PWM_WriteRegBit(REG_PWM1_Align,BITS(1:1,bAliPWM),BMASK(1:1));
1527*53ee8cc1Swenshuai.xi                 break;
1528*53ee8cc1Swenshuai.xi             case E_PWM_CH2:
1529*53ee8cc1Swenshuai.xi                 HAL_PWM_WriteRegBit(REG_PWM2_Align,BITS(2:2,bAliPWM),BMASK(2:2));
1530*53ee8cc1Swenshuai.xi                 break;
1531*53ee8cc1Swenshuai.xi             case E_PWM_CH3:
1532*53ee8cc1Swenshuai.xi                 HAL_PWM_WriteRegBit(REG_PWM3_Align,BITS(3:3,bAliPWM),BMASK(3:3));
1533*53ee8cc1Swenshuai.xi                 break;
1534*53ee8cc1Swenshuai.xi             case E_PWM_CH4:
1535*53ee8cc1Swenshuai.xi                 HAL_PWM_WriteRegBit(REG_PWM4_Align,BITS(4:4,bAliPWM),BMASK(4:4));
1536*53ee8cc1Swenshuai.xi                 break;
1537*53ee8cc1Swenshuai.xi             case E_PWM_CH5:
1538*53ee8cc1Swenshuai.xi             case E_PWM_CH6:
1539*53ee8cc1Swenshuai.xi             case E_PWM_CH7:
1540*53ee8cc1Swenshuai.xi             case E_PWM_CH8:
1541*53ee8cc1Swenshuai.xi             case E_PWM_CH9:
1542*53ee8cc1Swenshuai.xi             printf("[Utopia] The PWM%d is not support\n", (int)index);
1543*53ee8cc1Swenshuai.xi                 UNUSED(bAliPWM);
1544*53ee8cc1Swenshuai.xi                 break;
1545*53ee8cc1Swenshuai.xi             default:
1546*53ee8cc1Swenshuai.xi                 break;
1547*53ee8cc1Swenshuai.xi         }
1548*53ee8cc1Swenshuai.xi 
1549*53ee8cc1Swenshuai.xi         HAL_SUBBANK0;
1550*53ee8cc1Swenshuai.xi     }
1551*53ee8cc1Swenshuai.xi 
1552*53ee8cc1Swenshuai.xi PWM_3D_RegisterOffset g_ArrayPWM3D_RegisterOffset[PWM_Num][MAX_3DPWM_NUM] =
1553*53ee8cc1Swenshuai.xi {
1554*53ee8cc1Swenshuai.xi     { //PWM0
1555*53ee8cc1Swenshuai.xi         {//PWM0_Waveform_0
1556*53ee8cc1Swenshuai.xi             {0,  0}, //PWM0_Waveform_0_Shift  ==> use: HAL_PWM_Shift()
1557*53ee8cc1Swenshuai.xi             {0,  0}, //PWM0_Waveform_0_duty  ==> use: HAL_PWM_DutyCycle()
1558*53ee8cc1Swenshuai.xi         },
1559*53ee8cc1Swenshuai.xi         {//PWM0_Waveform_1
1560*53ee8cc1Swenshuai.xi             {REG_PWM0_HIT_CNT_ST,    16}, //PWM0_Waveform_1_Shift
1561*53ee8cc1Swenshuai.xi             {REG_PWM0_HIT_CNT_END,   16}, //PWM0_Waveform_1_duty
1562*53ee8cc1Swenshuai.xi         },
1563*53ee8cc1Swenshuai.xi         {//PWM0_Waveform_2
1564*53ee8cc1Swenshuai.xi             {REG_PWM0_HIT_CNT_ST2,    16}, //PWM0_Waveform_2_Shift
1565*53ee8cc1Swenshuai.xi             {REG_PWM0_HIT_CNT_END2,   16}, //PWM0_Waveform_2_duty
1566*53ee8cc1Swenshuai.xi         },
1567*53ee8cc1Swenshuai.xi         {//PWM0_Waveform_3
1568*53ee8cc1Swenshuai.xi             {REG_PWM0_SHIFT4,    16}, //PWM0_Waveform_3_Shift
1569*53ee8cc1Swenshuai.xi             {REG_PWM0_DUTY4,   16}, //PWM0_Waveform_3_duty
1570*53ee8cc1Swenshuai.xi         },
1571*53ee8cc1Swenshuai.xi     },
1572*53ee8cc1Swenshuai.xi 
1573*53ee8cc1Swenshuai.xi     { //PWM1
1574*53ee8cc1Swenshuai.xi         {//PWM1_Waveform_0
1575*53ee8cc1Swenshuai.xi             {0,  0}, //PWM1_Waveform_0_Shift  ==> use: HAL_PWM_Shift()
1576*53ee8cc1Swenshuai.xi             {0,  0}, //PWM1_Waveform_0_duty  ==> use: HAL_PWM_DutyCycle()
1577*53ee8cc1Swenshuai.xi         },
1578*53ee8cc1Swenshuai.xi         {//PWM1_Waveform_1
1579*53ee8cc1Swenshuai.xi             {REG_PWM1_HIT_CNT_ST,    16}, //PWM1_Waveform_1_Shift
1580*53ee8cc1Swenshuai.xi             {REG_PWM1_HIT_CNT_END,   16}, //PWM1_Waveform_1_duty
1581*53ee8cc1Swenshuai.xi         },
1582*53ee8cc1Swenshuai.xi         {//PWM1_Waveform_2
1583*53ee8cc1Swenshuai.xi             {REG_PWM1_HIT_CNT_ST2,    16}, //PWM1_Waveform_2_Shift
1584*53ee8cc1Swenshuai.xi             {REG_PWM1_HIT_CNT_END2,   16}, //PWM1_Waveform_2_duty
1585*53ee8cc1Swenshuai.xi         },
1586*53ee8cc1Swenshuai.xi         {//PWM1_Waveform_3
1587*53ee8cc1Swenshuai.xi             {REG_PWM1_SHIFT4,    16}, //PWM1_Waveform_3_Shift
1588*53ee8cc1Swenshuai.xi             {REG_PWM1_DUTY4,   16}, //PWM1_Waveform_3_duty
1589*53ee8cc1Swenshuai.xi         },
1590*53ee8cc1Swenshuai.xi     },
1591*53ee8cc1Swenshuai.xi };
1592*53ee8cc1Swenshuai.xi 
HAL_PWM_IsSupport3D(PWM_ChNum index)1593*53ee8cc1Swenshuai.xi MS_BOOL HAL_PWM_IsSupport3D(PWM_ChNum index)
1594*53ee8cc1Swenshuai.xi {
1595*53ee8cc1Swenshuai.xi     //Only PWM0 & PWM1 Support 3D Function
1596*53ee8cc1Swenshuai.xi     switch (index)
1597*53ee8cc1Swenshuai.xi     {
1598*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
1599*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
1600*53ee8cc1Swenshuai.xi             return TRUE;
1601*53ee8cc1Swenshuai.xi 
1602*53ee8cc1Swenshuai.xi         default:
1603*53ee8cc1Swenshuai.xi             return FALSE;
1604*53ee8cc1Swenshuai.xi     }
1605*53ee8cc1Swenshuai.xi }
1606*53ee8cc1Swenshuai.xi 
HAL_PWM_SetMultiDiff(MS_BOOL bEnable)1607*53ee8cc1Swenshuai.xi void HAL_PWM_SetMultiDiff(MS_BOOL bEnable)
1608*53ee8cc1Swenshuai.xi {
1609*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
1610*53ee8cc1Swenshuai.xi     HAL_PWM_WriteRegBit(REG_PWM_MULTI_DIFF, PWM_MULTI_DIEF_EN, bEnable);
1611*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
1612*53ee8cc1Swenshuai.xi }
1613*53ee8cc1Swenshuai.xi 
HAL_PWM_Set3D_DiffWaveform(PWM_ChNum index,MS_U8 u8WaveformIndex,MS_U32 u32Shift,MS_U32 u32Duty)1614*53ee8cc1Swenshuai.xi MS_BOOL HAL_PWM_Set3D_DiffWaveform(PWM_ChNum index, MS_U8 u8WaveformIndex, MS_U32 u32Shift, MS_U32 u32Duty)
1615*53ee8cc1Swenshuai.xi {
1616*53ee8cc1Swenshuai.xi     MS_BOOL bReturn = TRUE;
1617*53ee8cc1Swenshuai.xi     PWM_3D_RegisterOffset *pReigsterOffset = (PWM_3D_RegisterOffset *)&g_ArrayPWM3D_RegisterOffset[index][u8WaveformIndex];
1618*53ee8cc1Swenshuai.xi 
1619*53ee8cc1Swenshuai.xi     if (u8WaveformIndex == 0)
1620*53ee8cc1Swenshuai.xi     {
1621*53ee8cc1Swenshuai.xi         bReturn &= HAL_PWM_Shift(index, u32Shift);
1622*53ee8cc1Swenshuai.xi         HAL_PWM_DutyCycle(index, u32Duty);
1623*53ee8cc1Swenshuai.xi     }
1624*53ee8cc1Swenshuai.xi     else
1625*53ee8cc1Swenshuai.xi     {
1626*53ee8cc1Swenshuai.xi         HAL_SUBBANK1;
1627*53ee8cc1Swenshuai.xi         bReturn &= HAL_PWM_WriteNumberByte(pReigsterOffset->regShift.u32RegOffset, u32Shift, pReigsterOffset->regShift.u8NumBit);
1628*53ee8cc1Swenshuai.xi         bReturn &= HAL_PWM_WriteNumberByte(pReigsterOffset->regDuty.u32RegOffset, u32Duty, pReigsterOffset->regDuty.u8NumBit);
1629*53ee8cc1Swenshuai.xi         HAL_SUBBANK0
1630*53ee8cc1Swenshuai.xi     }
1631*53ee8cc1Swenshuai.xi 
1632*53ee8cc1Swenshuai.xi     return bReturn;
1633*53ee8cc1Swenshuai.xi }
1634*53ee8cc1Swenshuai.xi 
1635*53ee8cc1Swenshuai.xi //---------------------------PM Base--------------------------------//
1636*53ee8cc1Swenshuai.xi 
HAL_PM_PWM_Enable(void)1637*53ee8cc1Swenshuai.xi void HAL_PM_PWM_Enable(void)
1638*53ee8cc1Swenshuai.xi {
1639*53ee8cc1Swenshuai.xi     HAL_PM_WriteRegBit(REG_PM_PWM0_IS_GPIO,BITS(5:5,0),BMASK(5:5));
1640*53ee8cc1Swenshuai.xi     HAL_PM_WriteRegBit(reg_pwm_as_chip_config,BITS(0:0,0),BMASK(0:0));//reg_pwm_pm_is_PWM
1641*53ee8cc1Swenshuai.xi }
1642*53ee8cc1Swenshuai.xi 
HAL_PM_PWM_Period(MS_U16 u16PeriodPWM)1643*53ee8cc1Swenshuai.xi void HAL_PM_PWM_Period(MS_U16 u16PeriodPWM)
1644*53ee8cc1Swenshuai.xi {
1645*53ee8cc1Swenshuai.xi     MS_U16  Period;
1646*53ee8cc1Swenshuai.xi     Period = u16PeriodPWM;
1647*53ee8cc1Swenshuai.xi     HAL_PM_Write2Byte(REG_PM_PWM0_PERIOD, Period);
1648*53ee8cc1Swenshuai.xi }
1649*53ee8cc1Swenshuai.xi 
HAL_PM_PWM_DutyCycle(MS_U16 u16DutyPWM)1650*53ee8cc1Swenshuai.xi void HAL_PM_PWM_DutyCycle(MS_U16 u16DutyPWM)
1651*53ee8cc1Swenshuai.xi {
1652*53ee8cc1Swenshuai.xi     MS_U16  Duty;
1653*53ee8cc1Swenshuai.xi     Duty =u16DutyPWM;
1654*53ee8cc1Swenshuai.xi     HAL_PM_Write2Byte(REG_PM_PWM0_DUTY, Duty);
1655*53ee8cc1Swenshuai.xi }
1656*53ee8cc1Swenshuai.xi 
HAL_PM_PWM_Div(MS_U8 u8DivPWM)1657*53ee8cc1Swenshuai.xi void HAL_PM_PWM_Div(MS_U8 u8DivPWM)
1658*53ee8cc1Swenshuai.xi {
1659*53ee8cc1Swenshuai.xi     MS_U8 Div;
1660*53ee8cc1Swenshuai.xi     Div = u8DivPWM;
1661*53ee8cc1Swenshuai.xi     HAL_PM_Write2Byte(REG_PM_PWM0_DIV, Div);
1662*53ee8cc1Swenshuai.xi }
1663*53ee8cc1Swenshuai.xi 
HAL_PM_PWM_Polarity(MS_BOOL bPolPWM)1664*53ee8cc1Swenshuai.xi void HAL_PM_PWM_Polarity(MS_BOOL bPolPWM)
1665*53ee8cc1Swenshuai.xi {
1666*53ee8cc1Swenshuai.xi     HAL_PM_WriteRegBit(REG_PM_PWM0_PORARITY,BITS(0:0,bPolPWM),BMASK(0:0));
1667*53ee8cc1Swenshuai.xi }
1668*53ee8cc1Swenshuai.xi 
HAL_PM_PWM_DBen(MS_BOOL bdbenPWM)1669*53ee8cc1Swenshuai.xi void HAL_PM_PWM_DBen(MS_BOOL bdbenPWM)
1670*53ee8cc1Swenshuai.xi {
1671*53ee8cc1Swenshuai.xi     HAL_PM_WriteRegBit(REG_PM_PWM0_DBEN,BITS(1:1,bdbenPWM),BMASK(1:1));
1672*53ee8cc1Swenshuai.xi }
1673*53ee8cc1Swenshuai.xi 
1674*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
1675*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Name : HAL_PWM_INV_3D_Flag
1676*53ee8cc1Swenshuai.xi /// @brief \b Function   \b Description : Set Inverse 3D flag
1677*53ee8cc1Swenshuai.xi /// @param <IN>          \b MS_BOOL : 1 for Enable; 0 for Disable
1678*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_INV_3D_Flag(MS_BOOL bInvPWM)1679*53ee8cc1Swenshuai.xi MS_BOOL HAL_PWM_INV_3D_Flag(MS_BOOL bInvPWM)
1680*53ee8cc1Swenshuai.xi {
1681*53ee8cc1Swenshuai.xi 	MS_BOOL ret = FALSE;
1682*53ee8cc1Swenshuai.xi     HAL_SUBBANK1;
1683*53ee8cc1Swenshuai.xi     HAL_PM_WriteRegBit(REG_INV_3D_FLAG,BITS(15:15,bInvPWM),BMASK(15:15));
1684*53ee8cc1Swenshuai.xi     ret = true;
1685*53ee8cc1Swenshuai.xi     HAL_SUBBANK0;
1686*53ee8cc1Swenshuai.xi     return ret;
1687*53ee8cc1Swenshuai.xi }
1688*53ee8cc1Swenshuai.xi 
HAL_PWM_LR_RST_RISING(PWM_ChNum index,MS_BOOL bMask)1689*53ee8cc1Swenshuai.xi static void HAL_PWM_LR_RST_RISING(PWM_ChNum index, MS_BOOL bMask)
1690*53ee8cc1Swenshuai.xi {
1691*53ee8cc1Swenshuai.xi     switch (index)
1692*53ee8cc1Swenshuai.xi     {
1693*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
1694*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_INV_3D_FLAG, BITS(0:0, bMask), BMASK(0:0));
1695*53ee8cc1Swenshuai.xi             break;
1696*53ee8cc1Swenshuai.xi 
1697*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
1698*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_INV_3D_FLAG, BITS(1:1, bMask), BMASK(1:1));
1699*53ee8cc1Swenshuai.xi             break;
1700*53ee8cc1Swenshuai.xi 
1701*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
1702*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_INV_3D_FLAG, BITS(2:2, bMask), BMASK(2:2));
1703*53ee8cc1Swenshuai.xi             break;
1704*53ee8cc1Swenshuai.xi 
1705*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
1706*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_INV_3D_FLAG, BITS(3:3, bMask), BMASK(3:3));
1707*53ee8cc1Swenshuai.xi             break;
1708*53ee8cc1Swenshuai.xi 
1709*53ee8cc1Swenshuai.xi         default:
1710*53ee8cc1Swenshuai.xi             break;
1711*53ee8cc1Swenshuai.xi     }
1712*53ee8cc1Swenshuai.xi }
1713*53ee8cc1Swenshuai.xi 
HAL_PWM_LR_RST_FALLING(PWM_ChNum index,MS_BOOL bMask)1714*53ee8cc1Swenshuai.xi static void HAL_PWM_LR_RST_FALLING(PWM_ChNum index, MS_BOOL bMask)
1715*53ee8cc1Swenshuai.xi {
1716*53ee8cc1Swenshuai.xi     switch (index)
1717*53ee8cc1Swenshuai.xi     {
1718*53ee8cc1Swenshuai.xi         case E_PWM_CH0:
1719*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_INV_3D_FLAG, BITS(8:8, bMask), BMASK(8:8));
1720*53ee8cc1Swenshuai.xi             break;
1721*53ee8cc1Swenshuai.xi 
1722*53ee8cc1Swenshuai.xi         case E_PWM_CH1:
1723*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_INV_3D_FLAG, BITS(9:9, bMask), BMASK(9:9));
1724*53ee8cc1Swenshuai.xi             break;
1725*53ee8cc1Swenshuai.xi 
1726*53ee8cc1Swenshuai.xi         case E_PWM_CH2:
1727*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_INV_3D_FLAG, BITS(10:10, bMask), BMASK(10:10));
1728*53ee8cc1Swenshuai.xi             break;
1729*53ee8cc1Swenshuai.xi 
1730*53ee8cc1Swenshuai.xi         case E_PWM_CH3:
1731*53ee8cc1Swenshuai.xi             HAL_PWM_WriteRegBit(REG_INV_3D_FLAG, BITS(11:11, bMask), BMASK(11:11));
1732*53ee8cc1Swenshuai.xi             break;
1733*53ee8cc1Swenshuai.xi 
1734*53ee8cc1Swenshuai.xi         default:
1735*53ee8cc1Swenshuai.xi             break;
1736*53ee8cc1Swenshuai.xi     }
1737*53ee8cc1Swenshuai.xi }
1738*53ee8cc1Swenshuai.xi 
HAL_PWM_LR_RST_SEL(PWM_ChNum index,N_LR_SYNC_SEL eLR_Sync)1739*53ee8cc1Swenshuai.xi void HAL_PWM_LR_RST_SEL(PWM_ChNum index, N_LR_SYNC_SEL eLR_Sync)
1740*53ee8cc1Swenshuai.xi {
1741*53ee8cc1Swenshuai.xi     switch (eLR_Sync)
1742*53ee8cc1Swenshuai.xi     {
1743*53ee8cc1Swenshuai.xi         case E_VSYNC:
1744*53ee8cc1Swenshuai.xi             HAL_PWM_LR_RST_RISING(index, FALSE);
1745*53ee8cc1Swenshuai.xi             HAL_PWM_LR_RST_FALLING(index, FALSE);
1746*53ee8cc1Swenshuai.xi             break;
1747*53ee8cc1Swenshuai.xi 
1748*53ee8cc1Swenshuai.xi         case E_LR_RISING:
1749*53ee8cc1Swenshuai.xi             HAL_PWM_LR_RST_RISING(index, TRUE);
1750*53ee8cc1Swenshuai.xi             HAL_PWM_LR_RST_FALLING(index, FALSE);
1751*53ee8cc1Swenshuai.xi             break;
1752*53ee8cc1Swenshuai.xi 
1753*53ee8cc1Swenshuai.xi         case E_LR_FALLING:
1754*53ee8cc1Swenshuai.xi             HAL_PWM_LR_RST_RISING(index, FALSE);
1755*53ee8cc1Swenshuai.xi             HAL_PWM_LR_RST_FALLING(index, TRUE);
1756*53ee8cc1Swenshuai.xi             break;
1757*53ee8cc1Swenshuai.xi 
1758*53ee8cc1Swenshuai.xi         case E_LR_RISING_FALLING:
1759*53ee8cc1Swenshuai.xi             HAL_PWM_LR_RST_RISING(index, TRUE);
1760*53ee8cc1Swenshuai.xi             HAL_PWM_LR_RST_FALLING(index, TRUE);
1761*53ee8cc1Swenshuai.xi             break;
1762*53ee8cc1Swenshuai.xi 
1763*53ee8cc1Swenshuai.xi         default:
1764*53ee8cc1Swenshuai.xi             break;
1765*53ee8cc1Swenshuai.xi     }
1766*53ee8cc1Swenshuai.xi }
1767