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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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92 ////////////////////////////////////////////////////////////////////////////////
93 #define _HAL_PWM_C
94
95 ////////////////////////////////////////////////////////////////////////////////
96 /// @file mhal_PWM.c
97 /// @author MStar Semiconductor Inc.
98 /// @brief Pulse Width Modulation driver
99 ////////////////////////////////////////////////////////////////////////////////
100
101 ////////////////////////////////////////////////////////////////////////////////
102 // Header Files
103 ////////////////////////////////////////////////////////////////////////////////
104 #include "MsCommon.h"
105 #include "MsTypes.h"
106 #include "drvPWM.h"/* this is not good idea, just for temp. */
107 #include "halPWM.h"
108 #include "regPWM.h"
109
110 ////////////////////////////////////////////////////////////////////////////////
111 // Global variable
112 ////////////////////////////////////////////////////////////////////////////////
113
114 static MS_VIRT _gMIO_MapBase = 0;
115 static MS_VIRT _gMIO_PM_MapBase = 0;
116 static MS_U16 _gPWM_Status = 0;
117
118 //static MS_BOOL _gPWM_DBen = 0;
119 static MS_BOOL _gPWM_VDBen = 0;
120
121 static void _HAL_PWM_VDBen_SW(PWM_ChNum index, MS_BOOL bSwitch);
122 ////////////////////////////////////////////////////////////////////////////////
123 // Define & data type
124 ///////////////////////////////////////////////////////////////////////////////
125 #define WRITE_WORD_MASK(_reg, _val, _mask) { (*((volatile MS_U16*)(_reg))) = ((*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask)); }
126
127 #define HAL_PWM_ReadByte(addr) READ_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
128 #define HAL_PWM_Read2Byte(addr) READ_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2))
129
130 #define HAL_PWM_WriteByte(addr, val) WRITE_BYTE((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2), (val))
131 #define HAL_PWM_Write2Byte(addr, val) WRITE_WORD((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2), (val))
132 #define HAL_PWM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_MapBase + REG_PWM_BASE) + ((addr)<<2), (val), (mask))
133
134 #define HAL_TOP_ReadByte(addr) READ_BYTE((_gMIO_MapBase + REG_TOP_BASE) + ((addr)<<2))
135 #define HAL_TOP_Read2Byte(addr) READ_WORD((_gMIO_MapBase + REG_TOP_BASE) + ((addr)<<2))
136 #define HAL_TOP_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_MapBase + REG_TOP_BASE) + ((addr)<<2), (val), (mask))
137
138 #define HAL_PM_WriteByte(addr, val) WRITE_BYTE((_gMIO_PM_MapBase + REG_PM_BASE) + ((addr)<<2), (val))
139 #define HAL_PM_Write2Byte(addr, val) WRITE_WORD((_gMIO_PM_MapBase + REG_PM_BASE) + ((addr)<<2), (val))
140 #define HAL_PM_WriteRegBit(addr, val, mask) WRITE_WORD_MASK((_gMIO_PM_MapBase + REG_PM_BASE) + ((addr)<<2), (val), (mask))
141
142 #define HAL_SUBBANK0 //HAL_PWM_WriteByte(0,0)
143 #define HAL_SUBBANK1 //HAL_PWM_WriteByte(0,1) /* PWM sub-bank */
144
145 ////////////////////////////////////////////////////////////////////////////////
146 // Global Function
147 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_Write4Byte(MS_U32 u32RegAddr,MS_U32 u32Val)148 MS_BOOL HAL_PWM_Write4Byte(MS_U32 u32RegAddr, MS_U32 u32Val)
149 {
150 HAL_PWM_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF);
151 HAL_PWM_Write2Byte(u32RegAddr+2, u32Val >> 16);
152 return TRUE;
153 }
154
HAL_PWM_WriteNumberByte(MS_U32 u32RegAddr,MS_U32 u32SetValue,MS_U8 u8BitNum)155 static MS_BOOL HAL_PWM_WriteNumberByte(MS_U32 u32RegAddr, MS_U32 u32SetValue, MS_U8 u8BitNum)
156 {
157 MS_U32 u32Mask=0x0;
158 MS_U32 u32Value=0x0;
159 MS_U8 i;
160
161 for(i = 0; i<u8BitNum; i++)
162 u32Mask |= (1<<i);
163 if (u8BitNum == 0)
164 {
165 return TRUE;
166 }
167 else if (u8BitNum <= 8)
168 {
169 u32Value = u32SetValue & u32Mask;
170 HAL_PWM_WriteByte(u32RegAddr, (MS_U8) u32Value) ;
171 }
172 else if (u8BitNum <= 16)
173 {
174 u32Value = u32SetValue & u32Mask;
175 HAL_PWM_Write2Byte(u32RegAddr, (MS_U16) u32Value) ;
176 }
177 else if (u8BitNum <= 32)
178 {
179 u32Value = u32SetValue & u32Mask;
180 HAL_PWM_Write4Byte(u32RegAddr, (MS_U32) u32Value) ;
181 }
182 else
183 {
184 return FALSE;
185 }
186 return TRUE;
187 }
188
_HAL_PWM_VDBen_SW(PWM_ChNum index,MS_BOOL bSwitch)189 static void _HAL_PWM_VDBen_SW(PWM_ChNum index, MS_BOOL bSwitch)
190 {
191 if(_gPWM_VDBen)
192 {
193 //printf("%s(0x%08X, %x)", __FUNCTION__, (int)index, bSwitch);
194 switch(index)
195 {
196 case E_PWM_CH0:
197 HAL_PWM_WriteRegBit(REG_PWM0_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14));
198 break;
199 case E_PWM_CH1:
200 HAL_PWM_WriteRegBit(REG_PWM1_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14));
201 break;
202 case E_PWM_CH2:
203 HAL_PWM_WriteRegBit(REG_PWM2_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14));
204 break;
205 case E_PWM_CH3:
206 HAL_PWM_WriteRegBit(REG_PWM3_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14));
207 break;
208 case E_PWM_CH4:
209 HAL_PWM_WriteRegBit(REG_PWM4_VDBEN_SW,BITS(14:14,bSwitch),BMASK(14:14));
210 break;
211 case E_PWM_CH5:
212 case E_PWM_CH6:
213 case E_PWM_CH7:
214 case E_PWM_CH8:
215 case E_PWM_CH9:
216 printf("[Utopia] The PWM%d is not support\n", (int)index);
217 UNUSED(bSwitch);
218 break;
219 default:
220 break;
221 }
222 }
223 }
224
225 ////////////////////////////////////////////////////////////////////////////////
226 /// @brief \b Function \b Name: HAL_PWM_SetIOMapBase
227 /// @brief \b Function \b Description: Set IO Map base
228 /// @param <IN> \b None :
229 /// @param <OUT> \b None :
230 /// @param <RET> \b None :
231 /// @param <GLOBAL> \b None :
232 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_SetIOMapBase(MS_VIRT virtBase,MS_VIRT virtBase1)233 void HAL_PWM_SetIOMapBase(MS_VIRT virtBase,MS_VIRT virtBase1)
234 {
235 _gMIO_MapBase = virtBase;
236 _gMIO_PM_MapBase = virtBase1;
237 }
238
239 ////////////////////////////////////////////////////////////////////////////////
240 /// @brief \b Function \b Name: HAL_PWM_SetChipTopIOMapBase
241 /// @brief \b Function \b Description: Set chip top IO Map base
242 /// @param <IN> \b None :
243 /// @param <OUT> \b None :
244 /// @param <RET> \b None :
245 /// @param <GLOBAL> \b None :
246 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_SetChipTopIOMapBase(MS_VIRT virtBase)247 void HAL_PWM_SetChipTopIOMapBase(MS_VIRT virtBase)
248 {
249
250 }
251
252 ////////////////////////////////////////////////////////////////////////////////
253 /// @brief \b Function \b Name: HAL_PWM_GetIOMapBase
254 /// @brief \b Function \b Description: Get IO Map base
255 /// @param <IN> \b None :
256 /// @param <OUT> \b None :
257 /// @param <RET> \b None :
258 /// @param <GLOBAL> \b None :
259 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_GetIOMapBase(void)260 MS_VIRT HAL_PWM_GetIOMapBase(void)
261 {
262 return _gMIO_MapBase;
263 }
264
265 ////////////////////////////////////////////////////////////////////////////////
266 /// @brief \b Function \b Name: HAL_PWM_Init
267 /// @brief \b Function \b Description: Initial PWM
268 /// @param <IN> \b None :
269 /// @param <OUT> \b None :
270 /// @param <RET> \b MS_BOOL :
271 /// @param <GLOBAL> \b None :
272 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_Init(void)273 MS_BOOL HAL_PWM_Init(void)
274 {
275 MS_BOOL ret = FALSE;
276 #if 0
277 HAL_PWM_WriteRegBit(REG_ALL_PAD_IN, BIT7, 0);
278 HAL_PWM_WriteRegBit(REG_PWM_IS_GPIO, BIT0, 0);
279 HAL_PWM_WriteRegBit(REG_PWM_IS_GPIO, BIT1, 0);
280 HAL_PWM_WriteRegBit(REG_PWM_IS_GPIO, BIT2, 0);
281 HAL_PWM_WriteRegBit(REG_PWM_IS_GPIO, BIT3, 0);
282 #endif
283 _gPWM_Status = HAL_TOP_Read2Byte(REG_PWM_MODE);
284
285 if(_gPWM_Status&PAD_PWM0_OUT)
286 {
287 printf("Init PWM0\n");
288 }
289 if(_gPWM_Status&PAD_PWM1_OUT)
290 {
291 printf("Init PWM1\n");
292 }
293 if(_gPWM_Status&PAD_PWM2_OUT)
294 {
295 printf("Init PWM2\n");
296 }
297 if(_gPWM_Status&PAD_PWM3_OUT)
298 {
299 printf("Init PWM3\n");
300 }
301 if(_gPWM_Status&PAD_PWM4_OUT)
302 {
303 printf("Init PWM4\n");
304 }
305 ret = TRUE;
306 return ret;
307 }
308
309 ////////////////////////////////////////////////////////////////////////////////
310 /// @brief \b Function \b Name: HAL_PWM_Oen
311 /// @brief \b Function \b Description: Switch PWM PAD as Output or Input
312 /// @param <IN> \b MS_U16 : index
313 /// @param <IN> \b MS_BOOL : letch, 1 for Input; 0 for Output
314 /// @param <OUT> \b None :
315 /// @param <RET> \b MS_BOOL :
316 /// @param <GLOBAL> \b None :
317 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_Oen(PWM_ChNum index,MS_BOOL letch)318 MS_BOOL HAL_PWM_Oen(PWM_ChNum index, MS_BOOL letch)
319 {
320
321 //Use the PWM oen in ChipTop Reg first, if it provides for.
322
323 switch(index)
324 {
325 case E_PWM_CH0:
326 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(0:0,letch), BMASK(0:0));
327 break;
328 case E_PWM_CH1:
329 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(1:1,letch), BMASK(1:1));
330 break;
331 case E_PWM_CH2:
332 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(2:2,letch), BMASK(2:2));
333 break;
334 case E_PWM_CH3:
335 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(3:3,letch), BMASK(3:3));
336 break;
337 case E_PWM_CH4:
338 HAL_TOP_WriteRegBit(REG_PWM_OEN,BITS(4:4,letch), BMASK(4:4));
339 break;
340 case E_PWM_CH5:
341 case E_PWM_CH6:
342 case E_PWM_CH7:
343 case E_PWM_CH8:
344 case E_PWM_CH9:
345 printf("[Utopia] The PWM%d is not support\n", (int)index);
346 UNUSED(letch);
347 break;
348 default:
349 break;
350 }
351
352 return TRUE;
353 }
354 ////////////////////////////////////////////////////////////////////////////////
355 /// @brief \b Function \b Name: HAL_PWM_GetOen
356 /// @brief \b Function \b Description: Switch PWM PAD as Output or Input
357 /// @param <IN> \b MS_U16 : index
358 /// @param <OUT> \b None :
359 /// @param <RET> \b MS_BOOL : letch, 1 for Input; 0 for Output
360 /// @param <GLOBAL> \b None :
361 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_GetOen(PWM_ChNum index)362 MS_BOOL HAL_PWM_GetOen(PWM_ChNum index)
363 {
364 MS_BOOL letch = 0;
365 //Use the PWM oen in ChipTop Reg first, if it provides for.
366 switch(index)
367 {
368 case E_PWM_CH0:
369 letch = (HAL_PWM_Read2Byte(REG_PWM_OEN) & BMASK(0:0)) >> 0;
370 break;
371 case E_PWM_CH1:
372 letch = (HAL_PWM_Read2Byte(REG_PWM_OEN) & BMASK(1:1)) >> 1;
373 break;
374 case E_PWM_CH2:
375 letch = (HAL_PWM_Read2Byte(REG_PWM_OEN) & BMASK(2:2)) >> 2;
376 break;
377 case E_PWM_CH3:
378 letch = (HAL_PWM_Read2Byte(REG_PWM_OEN) & BMASK(3:3)) >> 3;
379 break;
380 case E_PWM_CH4:
381 letch = (HAL_PWM_Read2Byte(REG_PWM_OEN) & BMASK(4:4)) >> 4;
382 break;
383 case E_PWM_CH5:
384 case E_PWM_CH6:
385 case E_PWM_CH7:
386 case E_PWM_CH8:
387 case E_PWM_CH9:
388 printf("[Utopia] The PWM%d is not support\n", (int)index);
389 break;
390 default:
391 break;
392 }
393 return letch;
394 }
395
396 ////////////////////////////////////////////////////////////////////////////////
397 /// @brief \b Function \b Name : HAL_PWM_UnitDiv
398 /// @brief \b Function \b Description : Set the Unit_Div of the pwm
399 /// @param <IN> \b MS_U16 : the Unit_Div value
400 /// @param <OUT> \b None :
401 /// @param <RET> \b MS_BOOL : 1 for doen; 0 for not done
402 /// @param <GLOBAL> \b None :
403 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_UnitDiv(MS_U16 u16DivPWM)404 MS_BOOL HAL_PWM_UnitDiv(MS_U16 u16DivPWM)
405 {
406 MS_BOOL ret = FALSE;
407 /* the PWM clock unit divider is NO USE in T3 */
408 UNUSED(u16DivPWM);
409 printf("[Utopia] T8 is not support\n");
410 return ret;
411 }
412
413 ////////////////////////////////////////////////////////////////////////////////
414 /// @brief \b Function \b Name : HAL_PWM_Period
415 /// @brief \b Function \b Description : Set the period of the specific pwm
416 /// @param <IN> \b PWM_ChNum : Enum of the PWM CH
417 /// @param <IN> \b MS_U32 : the 18-bit Period value
418 /// @param <OUT> \b None :
419 /// @param <RET> \b None :
420 /// @param <GLOBAL> \b None :
421 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_Period(PWM_ChNum index,MS_U32 u32PeriodPWM)422 void HAL_PWM_Period(PWM_ChNum index, MS_U32 u32PeriodPWM)
423 {
424 MS_U16 Period_L, Period_H;
425 Period_L = (MS_U16)u32PeriodPWM;
426 Period_H = (MS_U16)(u32PeriodPWM >> 16);
427
428 HAL_SUBBANK1;
429 _HAL_PWM_VDBen_SW(index,0);
430 /* the Period capability is restricted to ONLY 18-bit */
431 switch(index)
432 {
433 case E_PWM_CH0:
434 HAL_PWM_Write2Byte(REG_PWM0_PERIOD, Period_L);
435 HAL_PWM_WriteRegBit(REG_PWM0_PERIOD_EXT,BITS(1:0,Period_H),BMASK(1:0));
436 break;
437 case E_PWM_CH1:
438 HAL_PWM_Write2Byte(REG_PWM1_PERIOD, Period_L);
439 HAL_PWM_WriteRegBit(REG_PWM1_PERIOD_EXT,BITS(3:2,Period_H),BMASK(3:2));
440 break;
441 case E_PWM_CH2:
442 HAL_PWM_Write2Byte(REG_PWM2_PERIOD, Period_L);
443 HAL_PWM_WriteRegBit(REG_PWM2_PERIOD_EXT,BITS(5:4,Period_H),BMASK(5:4));
444 break;
445 case E_PWM_CH3:
446 HAL_PWM_Write2Byte(REG_PWM3_PERIOD, Period_L);
447 HAL_PWM_WriteRegBit(REG_PWM3_PERIOD_EXT,BITS(7:6,Period_H),BMASK(7:6));
448 break;
449 case E_PWM_CH4:
450 HAL_PWM_Write2Byte(REG_PWM4_PERIOD, Period_L);
451 HAL_PWM_WriteRegBit(REG_PWM4_PERIOD_EXT,BITS(9:8,Period_H),BMASK(9:8));
452 break;
453 case E_PWM_CH5:
454 case E_PWM_CH6:
455 case E_PWM_CH7:
456 case E_PWM_CH8:
457 case E_PWM_CH9:
458 printf("[Utopia] The PWM%d is not support\n", (int)index);
459 UNUSED(Period_L);
460 UNUSED(Period_H);
461 break;
462 default:
463 break;
464 }
465 _HAL_PWM_VDBen_SW(index,1);
466 HAL_SUBBANK0;
467 }
468
HAL_PWM_GetPeriod(PWM_ChNum index)469 MS_U32 HAL_PWM_GetPeriod(PWM_ChNum index)
470 {
471 MS_U16 Period_L=0, Period_H=0;
472 HAL_SUBBANK1;
473 _HAL_PWM_VDBen_SW(index,0);
474 switch(index)
475 {
476 case E_PWM_CH0:
477 Period_L = HAL_PWM_Read2Byte(REG_PWM0_PERIOD);
478 Period_H = HAL_PWM_ReadByte(REG_PWM0_PERIOD_EXT) & BMASK(1:0);
479 break;
480 case E_PWM_CH1:
481 Period_L = HAL_PWM_Read2Byte(REG_PWM1_PERIOD);
482 Period_H = (HAL_PWM_ReadByte(REG_PWM1_PERIOD_EXT) & BMASK(3:2)) >> 2;
483 break;
484 case E_PWM_CH2:
485 Period_L = HAL_PWM_Read2Byte(REG_PWM2_PERIOD);
486 Period_H = (HAL_PWM_ReadByte(REG_PWM2_PERIOD_EXT) & BMASK(5:4)) >> 4;
487 break;
488 case E_PWM_CH3:
489 Period_L = HAL_PWM_Read2Byte(REG_PWM3_PERIOD);
490 Period_H = (HAL_PWM_ReadByte(REG_PWM3_PERIOD_EXT) & BMASK(7:6)) >> 6;
491 break;
492 case E_PWM_CH4:
493 Period_L = HAL_PWM_Read2Byte(REG_PWM4_PERIOD);
494 Period_H = (HAL_PWM_Read2Byte(REG_PWM4_PERIOD_EXT) & BMASK(9:8)) >> 8;
495 break;
496 case E_PWM_CH5:
497 case E_PWM_CH6:
498 case E_PWM_CH7:
499 case E_PWM_CH8:
500 case E_PWM_CH9:
501 printf("[Utopia] The PWM%d is not support\n", (int)index);
502 UNUSED(Period_L);
503 UNUSED(Period_H);
504 break;
505 default:
506 break;
507 }
508 _HAL_PWM_VDBen_SW(index,1);
509 HAL_SUBBANK0;
510 return ((MS_U32)Period_H << 16 | Period_L);
511 }
512
513 ////////////////////////////////////////////////////////////////////////////////
514 /// @brief \b Function \b Name : HAL_PWM_DutyCycle
515 /// @brief \b Function \b Description : Set the Duty of the specific pwm
516 /// @param <IN> \b PWM_ChNum : Enum of the PWM CH
517 /// @param <IN> \b MS_U32 : the 18-bit Duty value
518 /// @param <OUT> \b None :
519 /// @param <RET> \b None :
520 /// @param <GLOBAL> \b None :
521 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_DutyCycle(PWM_ChNum index,MS_U32 u32DutyPWM)522 void HAL_PWM_DutyCycle(PWM_ChNum index, MS_U32 u32DutyPWM)
523 {
524 MS_U16 Duty_L, Duty_H;
525
526 Duty_L = (MS_U16)u32DutyPWM;
527 Duty_H = (MS_U8)(u32DutyPWM >> 16);
528
529 HAL_SUBBANK1;
530 _HAL_PWM_VDBen_SW(index,0);
531 /* the Duty capability is restricted to ONLY 10-bit */
532 switch(index)
533 {
534 case E_PWM_CH0:
535 HAL_PWM_Write2Byte(REG_PWM0_DUTY, Duty_L);
536 HAL_PWM_WriteRegBit(REG_PWM0_DUTY_EXT,BITS(1:0,Duty_H),BMASK(1:0));
537 break;
538 case E_PWM_CH1:
539 HAL_PWM_Write2Byte(REG_PWM1_DUTY, Duty_L);
540 HAL_PWM_WriteRegBit(REG_PWM1_DUTY_EXT,BITS(3:2,Duty_H),BMASK(3:2));
541 break;
542 case E_PWM_CH2:
543 HAL_PWM_Write2Byte(REG_PWM2_DUTY, Duty_L);
544 HAL_PWM_WriteRegBit(REG_PWM2_DUTY_EXT,BITS(5:4,Duty_H),BMASK(5:4));
545 break;
546 case E_PWM_CH3:
547 HAL_PWM_Write2Byte(REG_PWM3_DUTY, Duty_L);
548 HAL_PWM_WriteRegBit(REG_PWM3_DUTY_EXT,BITS(7:6,Duty_H),BMASK(7:6));
549 break;
550 case E_PWM_CH4:
551 HAL_PWM_Write2Byte(REG_PWM4_DUTY, Duty_L);
552 HAL_PWM_WriteRegBit(REG_PWM4_DUTY_EXT,BITS(9:8,Duty_H),BMASK(9:8));
553 break;
554 case E_PWM_CH5:
555 case E_PWM_CH6:
556 case E_PWM_CH7:
557 case E_PWM_CH8:
558 case E_PWM_CH9:
559 printf("[Utopia] The PWM%d is not support\n", (int)index);
560 UNUSED(Duty_L);
561 UNUSED(Duty_H);
562 break;
563 default:
564 break;
565 }
566 _HAL_PWM_VDBen_SW(index,1);
567 HAL_SUBBANK0;
568 }
569
HAL_PWM_GetDutyCycle(PWM_ChNum index)570 MS_U32 HAL_PWM_GetDutyCycle(PWM_ChNum index)
571 {
572 MS_U16 Duty_L=0, Duty_H=0;
573
574 //Duty_L = (MS_U16)u32DutyPWM;
575 //Duty_H = (MS_U8)(u32DutyPWM >> 16);
576
577 HAL_SUBBANK1;
578 _HAL_PWM_VDBen_SW(index,0);
579 /* the Duty capability is restricted to ONLY 10-bit */
580 switch(index)
581 {
582 case E_PWM_CH0:
583 Duty_L = HAL_PWM_Read2Byte(REG_PWM0_DUTY);
584 Duty_H = HAL_PWM_ReadByte(REG_PWM0_DUTY_EXT) & BMASK(1:0);
585 break;
586 case E_PWM_CH1:
587 Duty_L = HAL_PWM_Read2Byte(REG_PWM1_DUTY);
588 Duty_H = (HAL_PWM_ReadByte(REG_PWM1_DUTY_EXT) & BMASK(3:2)) >> 2;
589 break;
590 case E_PWM_CH2:
591 Duty_L = HAL_PWM_Read2Byte(REG_PWM2_DUTY);
592 Duty_H = (HAL_PWM_ReadByte(REG_PWM2_DUTY_EXT) & BMASK(5:4)) >> 4;
593 break;
594 case E_PWM_CH3:
595 Duty_L = HAL_PWM_Read2Byte(REG_PWM3_DUTY);
596 Duty_H = (HAL_PWM_ReadByte(REG_PWM3_DUTY_EXT) & BMASK(7:6)) >> 6;
597 break;
598 case E_PWM_CH4:
599 Duty_L = HAL_PWM_Read2Byte(REG_PWM4_DUTY);
600 Duty_H = (HAL_PWM_Read2Byte(REG_PWM4_DUTY_EXT) & BMASK(9:8)) >> 8;
601 break;
602 case E_PWM_CH5:
603 case E_PWM_CH6:
604 case E_PWM_CH7:
605 case E_PWM_CH8:
606 case E_PWM_CH9:
607 printf("[Utopia] The PWM%d is not support\n", (int)index);
608 UNUSED(Duty_L);
609 UNUSED(Duty_H);
610 break;
611 default:
612 break;
613 }
614 _HAL_PWM_VDBen_SW(index,1);
615 HAL_SUBBANK0;
616 return ((MS_U32)Duty_H << 16 | Duty_L);
617 }
618
619 ////////////////////////////////////////////////////////////////////////////////
620 /// @brief \b Function \b Name : HAL_PWM_Div
621 /// @brief \b Function \b Description : Set the Div of the specific pwm
622 /// @param <IN> \b PWM_ChNum : Enum of the PWM CH
623 /// @param <IN> \b MS_U16 : the 16-bit Div value
624 /// @param <OUT> \b None :
625 /// @param <RET> \b None :
626 /// @param <GLOBAL> \b None :
627 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_Div(PWM_ChNum index,MS_U16 u16DivPWM)628 void HAL_PWM_Div(PWM_ChNum index, MS_U16 u16DivPWM)
629 {
630 MS_U8 u8DivPWM[2] = {0};
631
632 u8DivPWM[0] = (MS_U8)(u16DivPWM&0xFF);
633 u8DivPWM[1] = (MS_U8)(u16DivPWM >> 8);
634
635 HAL_SUBBANK1;
636 /* the Div capability is restricted to ONLY 16-bit */
637 switch(index)
638 {
639 case E_PWM_CH0:
640 HAL_PWM_WriteByte(REG_PWM0_DIV, u8DivPWM[0]);
641 HAL_PWM_WriteByte(REG_PWM0_DIV_EXT, u8DivPWM[1]);
642 break;
643 case E_PWM_CH1:
644 HAL_PWM_WriteByte(REG_PWM1_DIV, u8DivPWM[0]);
645 //HAL_PWM_WriteByte(REG_PWM1_DIV_EXT+1, u8DivPWM[1]);
646 HAL_PWM_WriteRegBit(REG_PWM1_DIV_EXT,u16DivPWM,BMASK(15:8));
647 break;
648 case E_PWM_CH2:
649 HAL_PWM_WriteByte(REG_PWM2_DIV, u8DivPWM[0]);
650 HAL_PWM_WriteByte(REG_PWM2_DIV_EXT, u8DivPWM[1]);
651 break;
652 case E_PWM_CH3:
653 HAL_PWM_WriteByte(REG_PWM3_DIV, u8DivPWM[0]);
654 //HAL_PWM_WriteByte(REG_PWM3_DIV_EXT+1, u8DivPWM[1]);
655 HAL_PWM_WriteRegBit(REG_PWM3_DIV_EXT,u16DivPWM,BMASK(15:8));
656 break;
657 case E_PWM_CH4:
658 HAL_PWM_WriteByte(REG_PWM4_DIV, u8DivPWM[0]);
659 HAL_PWM_WriteByte(REG_PWM4_DIV_EXT, u8DivPWM[1]);
660 break;
661 case E_PWM_CH5:
662 case E_PWM_CH6:
663 case E_PWM_CH7:
664 case E_PWM_CH8:
665 case E_PWM_CH9:
666 printf("[Utopia] The PWM%d is not support\n", (int)index);
667 UNUSED(u16DivPWM);
668 break;
669 default:
670 break;
671 }
672 HAL_SUBBANK0;
673 }
674 ////////////////////////////////////////////////////////////////////////////////
675 /// @brief \b Function \b Name : HAL_PWM_GetDiv
676 /// @brief \b Function \b Description :Get the Div of the specific pwm
677 /// @param <IN> \b PWM_ChNum : Enum of the PWM CH
678 /// @param <OUT> \b None :
679 /// @param <RET> \b MS_U16 : the 16-bit Div value
680 /// @param <GLOBAL> \b None :
681 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_GetDiv(PWM_ChNum index)682 MS_U16 HAL_PWM_GetDiv(PWM_ChNum index)
683 {
684 MS_U8 u8DivPWM[2] = {0};
685
686 HAL_SUBBANK1;
687 /* the Div capability is restricted to ONLY 16-bit */
688 switch(index)
689 {
690 case E_PWM_CH0:
691 u8DivPWM[0] = HAL_PWM_ReadByte(REG_PWM0_DIV);
692 u8DivPWM[1] = HAL_PWM_ReadByte(REG_PWM0_DIV_EXT);
693 break;
694 case E_PWM_CH1:
695 u8DivPWM[0] = HAL_PWM_ReadByte(REG_PWM1_DIV);
696 u8DivPWM[1] = ((HAL_PWM_Read2Byte(REG_PWM1_DIV_EXT) & BMASK(15:8)) >> 8)&0xFF;
697 break;
698 case E_PWM_CH2:
699 u8DivPWM[0] = HAL_PWM_ReadByte(REG_PWM2_DIV);
700 u8DivPWM[1] = HAL_PWM_ReadByte(REG_PWM2_DIV_EXT);
701 break;
702 case E_PWM_CH3:
703 u8DivPWM[0] = HAL_PWM_ReadByte(REG_PWM3_DIV);
704 u8DivPWM[1] = ((HAL_PWM_Read2Byte(REG_PWM3_DIV_EXT) & BMASK(15:8)) >> 8)&0xFF;
705 break;
706 case E_PWM_CH4:
707 u8DivPWM[0] = HAL_PWM_ReadByte(REG_PWM4_DIV);
708 u8DivPWM[1] = HAL_PWM_ReadByte(REG_PWM4_DIV_EXT);
709 break;
710 case E_PWM_CH5:
711 case E_PWM_CH6:
712 case E_PWM_CH7:
713 case E_PWM_CH8:
714 case E_PWM_CH9:
715 printf("[Utopia] The PWM%d is not support\n", (int)index);
716 break;
717 default:
718 break;
719 }
720 HAL_SUBBANK0;
721
722 return ((u8DivPWM[1]<<8) | u8DivPWM[0]);
723 }
724
725 ////////////////////////////////////////////////////////////////////////////////
726 /// @brief \b Function \b Name : HAL_PWM_Polarity
727 /// @brief \b Function \b Description : Set the Polarity of the specific pwm
728 /// @param <IN> \b PWM_ChNum : Enum of the PWM CH
729 /// @param <IN> \b MS_BOOL : 1 for enable; 0 for disable
730 /// @param <OUT> \b None :
731 /// @param <RET> \b None :
732 /// @param <GLOBAL> \b None :
733 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_Polarity(PWM_ChNum index,MS_BOOL bPolPWM)734 void HAL_PWM_Polarity(PWM_ChNum index, MS_BOOL bPolPWM)
735 {
736 HAL_SUBBANK1;
737 switch(index)
738 {
739 case E_PWM_CH0:
740 HAL_PWM_WriteRegBit(REG_PWM0_PORARITY,BITS(8:8,bPolPWM),BMASK(8:8));
741 break;
742 case E_PWM_CH1:
743 HAL_PWM_WriteRegBit(REG_PWM1_PORARITY,BITS(8:8,bPolPWM),BMASK(8:8));
744 break;
745 case E_PWM_CH2:
746 HAL_PWM_WriteRegBit(REG_PWM2_PORARITY,BITS(8:8,bPolPWM),BMASK(8:8));
747 break;
748 case E_PWM_CH3:
749 HAL_PWM_WriteRegBit(REG_PWM3_PORARITY,BITS(8:8,bPolPWM),BMASK(8:8));
750 break;
751 case E_PWM_CH4:
752 HAL_PWM_WriteRegBit(REG_PWM4_PORARITY,BITS(8:8,bPolPWM),BMASK(8:8));
753 break;
754 case E_PWM_CH5:
755 case E_PWM_CH6:
756 case E_PWM_CH7:
757 case E_PWM_CH8:
758 case E_PWM_CH9:
759 printf("[Utopia] The PWM%d is not support\n", (int)index);
760 UNUSED(bPolPWM);
761 break;
762 default:
763 break;
764 }
765 HAL_SUBBANK0;
766 }
767 ////////////////////////////////////////////////////////////////////////////////
768 /// @brief \b Function \b Name : HAL_PWM_GetPolarity
769 /// @brief \b Function \b Description : Get the Polarity of the specific pwm
770 /// @param <IN> \b PWM_ChNum : Enum of the PWM CH
771 /// @param <OUT> \b None :
772 /// @param <RET> \b MS_BOOL : 1 for enable; 0 for disable
773 /// @param <GLOBAL> \b None :
774 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_GetPolarity(PWM_ChNum index)775 MS_BOOL HAL_PWM_GetPolarity(PWM_ChNum index)
776 {
777 MS_BOOL bPolarity = FALSE;
778 HAL_SUBBANK1;
779 switch(index)
780 {
781 case E_PWM_CH0:
782 bPolarity = (HAL_PWM_Read2Byte(REG_PWM0_PORARITY) & BMASK(8:8)) >> 8;
783 break;
784 case E_PWM_CH1:
785 bPolarity = (HAL_PWM_Read2Byte(REG_PWM1_PORARITY) & BMASK(8:8)) >> 8;
786 break;
787 case E_PWM_CH2:
788 bPolarity = (HAL_PWM_Read2Byte(REG_PWM2_PORARITY) & BMASK(8:8)) >> 8;
789 break;
790 case E_PWM_CH3:
791 bPolarity = (HAL_PWM_Read2Byte(REG_PWM3_PORARITY) & BMASK(8:8)) >> 8;
792 break;
793 case E_PWM_CH4:
794 bPolarity = (HAL_PWM_Read2Byte(REG_PWM4_PORARITY) & BMASK(8:8)) >> 8;
795 break;
796 case E_PWM_CH5:
797 case E_PWM_CH6:
798 case E_PWM_CH7:
799 case E_PWM_CH8:
800 case E_PWM_CH9:
801 printf("[Utopia] The PWM%d is not support\n", (int)index);
802 break;
803 default:
804 break;
805 }
806 HAL_SUBBANK0;
807
808 return bPolarity;
809 }
810
811 ////////////////////////////////////////////////////////////////////////////////
812 /// @brief \b Function \b Name : HAL_PWM_VDBen
813 /// @brief \b Function \b Description : Set the Vsync Double buffer of the specific pwm
814 /// @param <IN> \b PWM_ChNum : Enum of the PWM CH
815 /// @param <IN> \b MS_BOOL : 1 for enable; 0 for disable
816 /// @param <OUT> \b None :
817 /// @param <RET> \b None :
818 /// @param <GLOBAL> \b None :
819 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_VDBen(PWM_ChNum index,MS_BOOL bVdbenPWM)820 void HAL_PWM_VDBen(PWM_ChNum index, MS_BOOL bVdbenPWM)
821 {
822 _gPWM_VDBen = bVdbenPWM;
823
824 HAL_SUBBANK1;
825
826 switch(index)
827 {
828 case E_PWM_CH0:
829 HAL_PWM_WriteRegBit(REG_PWM0_VDBEN,BITS(9:9,bVdbenPWM),BMASK(9:9));
830 break;
831 case E_PWM_CH1:
832 HAL_PWM_WriteRegBit(REG_PWM1_VDBEN,BITS(9:9,bVdbenPWM),BMASK(9:9));
833 break;
834 case E_PWM_CH2:
835 HAL_PWM_WriteRegBit(REG_PWM2_VDBEN,BITS(9:9,bVdbenPWM),BMASK(9:9));
836 break;
837 case E_PWM_CH3:
838 HAL_PWM_WriteRegBit(REG_PWM3_VDBEN,BITS(9:9,bVdbenPWM),BMASK(9:9));
839 break;
840 case E_PWM_CH4:
841 HAL_PWM_WriteRegBit(REG_PWM4_VDBEN,BITS(9:9,bVdbenPWM),BMASK(9:9));
842 break;
843 case E_PWM_CH5:
844 case E_PWM_CH6:
845 case E_PWM_CH7:
846 case E_PWM_CH8:
847 case E_PWM_CH9:
848 printf("[Utopia] The PWM%d is not support\n", (int)index);
849 UNUSED(bVdbenPWM);
850 break;
851 default:
852 break;
853 }
854
855 HAL_SUBBANK0;
856 }
857 ////////////////////////////////////////////////////////////////////////////////
858 /// @brief \b Function \b Name : HAL_PWM_GetVDBen
859 /// @brief \b Function \b Description :Get the Vsync Double buffer of the specific pwm
860 /// @param <IN> \b PWM_ChNum : Enum of the PWM CH
861 /// @param <OUT> \b None :
862 /// @param <RET> \b MS_BOOL : 1 for enable; 0 for disable
863 /// @param <GLOBAL> \b None :
864 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_GetVDBen(PWM_ChNum index)865 MS_BOOL HAL_PWM_GetVDBen(PWM_ChNum index)
866 {
867 MS_BOOL bVdbenPWM = FALSE;
868
869 HAL_SUBBANK1;
870
871 switch(index)
872 {
873 case E_PWM_CH0:
874 bVdbenPWM = (HAL_PWM_Read2Byte(REG_PWM0_VDBEN) & BMASK(9:9)) >> 9;
875 break;
876 case E_PWM_CH1:
877 bVdbenPWM = (HAL_PWM_Read2Byte(REG_PWM1_VDBEN) & BMASK(9:9)) >> 9;
878 break;
879 case E_PWM_CH2:
880 bVdbenPWM = (HAL_PWM_Read2Byte(REG_PWM2_VDBEN) & BMASK(9:9)) >> 9;
881 break;
882 case E_PWM_CH3:
883 bVdbenPWM = (HAL_PWM_Read2Byte(REG_PWM3_VDBEN) & BMASK(9:9)) >> 9;
884 break;
885 case E_PWM_CH4:
886 bVdbenPWM = (HAL_PWM_Read2Byte(REG_PWM4_VDBEN) & BMASK(9:9)) >> 9;
887 break;
888 case E_PWM_CH5:
889 case E_PWM_CH6:
890 case E_PWM_CH7:
891 case E_PWM_CH8:
892 case E_PWM_CH9:
893 printf("[Utopia] The PWM%d is not support\n", (int)index);
894 break;
895 default:
896 break;
897 }
898
899 HAL_SUBBANK0;
900 return bVdbenPWM;
901 }
902
903 ////////////////////////////////////////////////////////////////////////////////
904 /// @brief \b Function \b Name : HAL_PWM_Vrest
905 /// @brief \b Function \b Description : Set the Hsync reset of the specific pwm
906 /// @param <IN> \b PWM_ChNum : Enum of the PWM CH
907 /// @param <IN> \b MS_BOOL : 1 for enable; 0 for disable
908 /// @param <OUT> \b None :
909 /// @param <RET> \b None :
910 /// @param <GLOBAL> \b None :
911 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_Vrest(PWM_ChNum index,MS_BOOL bRstPWM)912 void HAL_PWM_Vrest(PWM_ChNum index, MS_BOOL bRstPWM)
913 {
914 HAL_SUBBANK1;
915
916 switch(index)
917 {
918 case E_PWM_CH0:
919 HAL_PWM_WriteRegBit(REG_PWM0_RESET_EN,BITS(10:10,bRstPWM),BMASK(10:10));
920 break;
921 case E_PWM_CH1:
922 HAL_PWM_WriteRegBit(REG_PWM1_RESET_EN,BITS(10:10,bRstPWM),BMASK(10:10));
923 break;
924 case E_PWM_CH2:
925 HAL_PWM_WriteRegBit(REG_PWM2_RESET_EN,BITS(10:10,bRstPWM),BMASK(10:10));
926 break;
927 case E_PWM_CH3:
928 HAL_PWM_WriteRegBit(REG_PWM3_RESET_EN,BITS(10:10,bRstPWM),BMASK(10:10));
929 break;
930 case E_PWM_CH4:
931 HAL_PWM_WriteRegBit(REG_PWM4_RESET_EN,BITS(10:10,bRstPWM),BMASK(10:10));
932 break;
933 case E_PWM_CH5:
934 case E_PWM_CH6:
935 case E_PWM_CH7:
936 case E_PWM_CH8:
937 case E_PWM_CH9:
938 printf("[Utopia] The PWM%d is not support\n", (int)index);
939 UNUSED(bRstPWM);
940 break;
941 default:
942 break;
943 }
944
945 HAL_SUBBANK0;
946 }
947 ////////////////////////////////////////////////////////////////////////////////
948 /// @brief \b Function \b Name : HAL_PWM_GetVrest
949 /// @brief \b Function \b Description :Get the Hsync reset of the specific pwm
950 /// @param <IN> \b PWM_ChNum : Enum of the PWM CH
951 /// @param <OUT> \b None :
952 /// @param <RET> \b MS_BOOL : 1 for enable; 0 for disable
953 /// @param <GLOBAL> \b None :
954 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_GetVrest(PWM_ChNum index)955 MS_BOOL HAL_PWM_GetVrest(PWM_ChNum index)
956 {
957 MS_BOOL bRstPWM = 0;
958
959 HAL_SUBBANK1;
960
961 switch(index)
962 {
963 case E_PWM_CH0:
964 bRstPWM = (HAL_PWM_Read2Byte(REG_PWM0_RESET_EN) & BMASK(10:10)) >> 10;
965 break;
966 case E_PWM_CH1:
967 bRstPWM = (HAL_PWM_Read2Byte(REG_PWM1_RESET_EN) & BMASK(10:10)) >> 10;
968 break;
969 case E_PWM_CH2:
970 bRstPWM = (HAL_PWM_Read2Byte(REG_PWM2_RESET_EN) & BMASK(10:10)) >> 10;
971 break;
972 case E_PWM_CH3:
973 bRstPWM = (HAL_PWM_Read2Byte(REG_PWM3_RESET_EN) & BMASK(10:10)) >> 10;
974 break;
975 case E_PWM_CH4:
976 bRstPWM = (HAL_PWM_Read2Byte(REG_PWM4_RESET_EN) & BMASK(10:10)) >> 10;
977 break;
978 case E_PWM_CH5:
979 case E_PWM_CH6:
980 case E_PWM_CH7:
981 case E_PWM_CH8:
982 case E_PWM_CH9:
983 printf("[Utopia] The PWM%d is not support\n", (int)index);
984 break;
985 default:
986 break;
987 }
988
989 HAL_SUBBANK0;
990 return bRstPWM;
991 }
992
993 ////////////////////////////////////////////////////////////////////////////////
994 /// @brief \b Function \b Name : HAL_PWM_DBen
995 /// @brief \b Function \b Description : Set the Double buffer of the specific pwm
996 /// @param <IN> \b PWM_ChNum : Enum of the PWM CH
997 /// @param <IN> \b MS_BOOL : 1 for enable; 0 for disable
998 /// @param <OUT> \b None :
999 /// @param <RET> \b None :
1000 /// @param <GLOBAL> \b None :
1001 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_DBen(PWM_ChNum index,MS_BOOL bdbenPWM)1002 void HAL_PWM_DBen(PWM_ChNum index, MS_BOOL bdbenPWM)
1003 {
1004 //_gPWM_DBen = bdbenPWM;
1005
1006 HAL_SUBBANK1;
1007
1008 switch(index)
1009 {
1010 case E_PWM_CH0:
1011 HAL_PWM_WriteRegBit(REG_PWM0_DBEN,BITS(11:11,bdbenPWM),BMASK(11:11));
1012 break;
1013 case E_PWM_CH1:
1014 HAL_PWM_WriteRegBit(REG_PWM1_DBEN,BITS(11:11,bdbenPWM),BMASK(11:11));
1015 break;
1016 case E_PWM_CH2:
1017 HAL_PWM_WriteRegBit(REG_PWM2_DBEN,BITS(11:11,bdbenPWM),BMASK(11:11));
1018 break;
1019 case E_PWM_CH3:
1020 HAL_PWM_WriteRegBit(REG_PWM3_DBEN,BITS(11:11,bdbenPWM),BMASK(11:11));
1021 break;
1022 case E_PWM_CH4:
1023 HAL_PWM_WriteRegBit(REG_PWM4_DBEN,BITS(11:11,bdbenPWM),BMASK(11:11));
1024 break;
1025 case E_PWM_CH5:
1026 case E_PWM_CH6:
1027 case E_PWM_CH7:
1028 case E_PWM_CH8:
1029 case E_PWM_CH9:
1030 printf("[Utopia] The PWM%d is not support\n", (int)index);
1031 UNUSED(bdbenPWM);
1032 break;
1033 default:
1034 break;
1035 }
1036
1037 HAL_SUBBANK0;
1038 }
1039 ////////////////////////////////////////////////////////////////////////////////
1040 /// @brief \b Function \b Name : HAL_PWM_GetDBen
1041 /// @brief \b Function \b Description : Get the Double buffer of the specific pwm
1042 /// @param <IN> \b PWM_ChNum : Enum of the PWM CH
1043 /// @param <OUT> \b None :
1044 /// @param <RET> \b None :
1045 /// @param <GLOBAL> \b None :
1046 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_GetDBen(PWM_ChNum index)1047 MS_BOOL HAL_PWM_GetDBen(PWM_ChNum index)
1048 {
1049 MS_BOOL bdbenPWM = FALSE;
1050
1051 HAL_SUBBANK1;
1052
1053 switch(index)
1054 {
1055 case E_PWM_CH0:
1056 bdbenPWM = (HAL_PWM_Read2Byte(REG_PWM0_DBEN) & BMASK(11:11)) >> 11;
1057 break;
1058 case E_PWM_CH1:
1059 bdbenPWM = (HAL_PWM_Read2Byte(REG_PWM1_DBEN) & BMASK(11:11)) >> 11;
1060 break;
1061 case E_PWM_CH2:
1062 bdbenPWM = (HAL_PWM_Read2Byte(REG_PWM2_DBEN) & BMASK(11:11)) >> 11;
1063 break;
1064 case E_PWM_CH3:
1065 bdbenPWM = (HAL_PWM_Read2Byte(REG_PWM3_DBEN) & BMASK(11:11)) >> 11;
1066 break;
1067 case E_PWM_CH4:
1068 bdbenPWM = (HAL_PWM_Read2Byte(REG_PWM4_DBEN) & BMASK(11:11)) >> 11;
1069 break;
1070 case E_PWM_CH5:
1071 case E_PWM_CH6:
1072 case E_PWM_CH7:
1073 case E_PWM_CH8:
1074 case E_PWM_CH9:
1075 printf("[Utopia] The PWM%d is not support\n", (int)index);
1076 break;
1077 default:
1078 break;
1079 }
1080
1081 HAL_SUBBANK0;
1082
1083 return bdbenPWM;
1084 }
1085
HAL_PWM_IMPULSE_EN(PWM_ChNum index,MS_BOOL bdbenPWM)1086 void HAL_PWM_IMPULSE_EN(PWM_ChNum index, MS_BOOL bdbenPWM)
1087 {
1088 HAL_SUBBANK1;
1089
1090 switch(index)
1091 {
1092 case E_PWM_CH0:
1093 HAL_PWM_WriteRegBit(REG_PWM0_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1094 break;
1095 case E_PWM_CH1:
1096 HAL_PWM_WriteRegBit(REG_PWM1_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1097 break;
1098 case E_PWM_CH2:
1099 HAL_PWM_WriteRegBit(REG_PWM2_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1100 break;
1101 case E_PWM_CH3:
1102 HAL_PWM_WriteRegBit(REG_PWM3_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1103 break;
1104 case E_PWM_CH4:
1105 HAL_PWM_WriteRegBit(REG_PWM4_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1106 break;
1107 case E_PWM_CH5:
1108 HAL_PWM_WriteRegBit(REG_PWM5_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1109 break;
1110 case E_PWM_CH6:
1111 HAL_PWM_WriteRegBit(REG_PWM6_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1112 break;
1113 case E_PWM_CH7:
1114 HAL_PWM_WriteRegBit(REG_PWM7_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1115 break;
1116 case E_PWM_CH8:
1117 HAL_PWM_WriteRegBit(REG_PWM8_IMPULSE_EN,BITS(12:12,bdbenPWM),BMASK(12:12));
1118 break;
1119 case E_PWM_CH9:
1120 UNUSED(bdbenPWM);
1121 break;
1122 default:
1123 break;
1124 }
1125
1126 HAL_SUBBANK0;
1127 }
1128
1129
HAL_PWM_ODDEVEN_SYNC(PWM_ChNum index,MS_BOOL bdbenPWM)1130 void HAL_PWM_ODDEVEN_SYNC(PWM_ChNum index, MS_BOOL bdbenPWM)
1131 {
1132 HAL_SUBBANK1;
1133
1134 switch(index)
1135 {
1136 case E_PWM_CH0:
1137 HAL_PWM_WriteRegBit(REG_PWM0_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1138 break;
1139 case E_PWM_CH1:
1140 HAL_PWM_WriteRegBit(REG_PWM1_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1141 break;
1142 case E_PWM_CH2:
1143 HAL_PWM_WriteRegBit(REG_PWM2_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1144 break;
1145 case E_PWM_CH3:
1146 HAL_PWM_WriteRegBit(REG_PWM3_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1147 break;
1148 case E_PWM_CH4:
1149 HAL_PWM_WriteRegBit(REG_PWM4_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1150 break;
1151 case E_PWM_CH5:
1152 HAL_PWM_WriteRegBit(REG_PWM5_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1153 break;
1154 case E_PWM_CH6:
1155 HAL_PWM_WriteRegBit(REG_PWM6_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1156 break;
1157 case E_PWM_CH7:
1158 HAL_PWM_WriteRegBit(REG_PWM7_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1159 break;
1160 case E_PWM_CH8:
1161 HAL_PWM_WriteRegBit(REG_PWM8_ODDEVEN_SYNC,BITS(13:13,bdbenPWM),BMASK(13:13));
1162 break;
1163 case E_PWM_CH9:
1164 UNUSED(bdbenPWM);
1165 break;
1166 default:
1167 break;
1168 }
1169
1170 HAL_SUBBANK0;
1171 }
1172
1173 ////////////////////////////////////////////////////////////////////////////////
1174 /// @brief \b Function \b Name : HAL_PWM_RstMux
1175 /// @brief \b Function \b Description : Set the Rst Mux of the specific pwm
1176 /// @param <IN> \b PWM_ChNum : Enum of the PWM CH
1177 /// @param <IN> \b MS_BOOL : 1 for Hsync; 0 for Vsync
1178 /// @param <OUT> \b None :
1179 /// @param <RET> \b None :
1180 /// @param <GLOBAL> \b None :
1181 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_RstMux(PWM_ChNum index,MS_BOOL bMuxPWM)1182 void HAL_PWM_RstMux(PWM_ChNum index, MS_BOOL bMuxPWM)
1183 {
1184 HAL_SUBBANK1;
1185
1186 switch(index)
1187 {
1188 case E_PWM_CH0:
1189 HAL_PWM_WriteRegBit(REG_RST_MUX0,BITS(15:15,bMuxPWM),BMASK(15:15));
1190 break;
1191 case E_PWM_CH1:
1192 HAL_PWM_WriteRegBit(REG_RST_MUX1,BITS(7:7,bMuxPWM),BMASK(7:7));
1193 break;
1194 case E_PWM_CH2:
1195 HAL_PWM_WriteRegBit(REG_RST_MUX2,BITS(15:15,bMuxPWM),BMASK(15:15));
1196 break;
1197 case E_PWM_CH3:
1198 HAL_PWM_WriteRegBit(REG_RST_MUX3,BITS(7:7,bMuxPWM),BMASK(7:7));
1199 break;
1200 case E_PWM_CH4:
1201 HAL_PWM_WriteRegBit(REG_RST_MUX4,BITS(15:15,bMuxPWM),BMASK(15:15));
1202 break;
1203 case E_PWM_CH5:
1204 case E_PWM_CH6:
1205 case E_PWM_CH7:
1206 case E_PWM_CH8:
1207 case E_PWM_CH9:
1208 printf("[Utopia] The PWM%d is not support\n", (int)index);
1209 UNUSED(bMuxPWM);
1210 break;
1211 default:
1212 break;
1213 }
1214
1215 HAL_SUBBANK0;
1216 }
1217
1218 ////////////////////////////////////////////////////////////////////////////////
1219 /// @brief \b Function \b Name : HAL_PWM_RstCnt
1220 /// @brief \b Function \b Description : Set the Rst_Cnt of the specific pwm
1221 /// @param <IN> \b PWM_ChNum : Enum of the PWM CH
1222 /// @param <IN> \b MS_U8 : u8RstCntPWM
1223 /// @param <OUT> \b None :
1224 /// @param <RET> \b None :
1225 /// @param <GLOBAL> \b None :
1226 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_RstCnt(PWM_ChNum index,MS_U8 u8RstCntPWM)1227 void HAL_PWM_RstCnt(PWM_ChNum index, MS_U8 u8RstCntPWM)
1228 {
1229 if( u8RstCntPWM & 0x10 )
1230 {
1231 printf("PWM%d Reset Count is too large\n", index);
1232 }
1233
1234 HAL_SUBBANK1;
1235 /* the Hsync reset counter capability is restricted to ONLY 4-bit */
1236 switch(index)
1237 {
1238 case E_PWM_CH0:
1239 HAL_PWM_WriteRegBit(REG_HS_RST_CNT0,BITS(11:8,u8RstCntPWM),BMASK(11:8));
1240 break;
1241 case E_PWM_CH1:
1242 HAL_PWM_WriteRegBit(REG_HS_RST_CNT1,BITS(3:0,u8RstCntPWM),BMASK(3:0));
1243 break;
1244 case E_PWM_CH2:
1245 HAL_PWM_WriteRegBit(REG_HS_RST_CNT2,BITS(11:8,u8RstCntPWM),BMASK(11:8));
1246 break;
1247 case E_PWM_CH3:
1248 HAL_PWM_WriteRegBit(REG_HS_RST_CNT3,BITS(3:0,u8RstCntPWM),BMASK(3:0));
1249 break;
1250 case E_PWM_CH4:
1251 HAL_PWM_WriteRegBit(REG_HS_RST_CNT4,BITS(11:8,u8RstCntPWM),BMASK(11:8));
1252 break;
1253 case E_PWM_CH5:
1254 case E_PWM_CH6:
1255 case E_PWM_CH7:
1256 case E_PWM_CH8:
1257 case E_PWM_CH9:
1258 printf("[Utopia] The PWM%d is not support\n", (int)index);
1259 UNUSED(u8RstCntPWM);
1260 break;
1261 default:
1262 break;
1263 }
1264
1265 HAL_SUBBANK0;
1266 }
1267
1268 ////////////////////////////////////////////////////////////////////////////////
1269 /// @brief \b Function \b Name : HAL_PWM_BypassUnit
1270 /// @brief \b Function \b Description : Set the Bypass Unit of the specific pwm
1271 /// @param <IN> \b PWM_ChNum : Enum of the PWM CH
1272 /// @param <IN> \b MS_BOOL : 1 for enable; 0 for disable
1273 /// @param <OUT> \b None :
1274 /// @param <RET> \b None :
1275 /// @param <GLOBAL> \b None :
1276 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_BypassUnit(PWM_ChNum index,MS_BOOL bBypassPWM)1277 void HAL_PWM_BypassUnit(PWM_ChNum index, MS_BOOL bBypassPWM)
1278 {
1279 HAL_SUBBANK1;
1280
1281 //T2 ONLY
1282
1283 switch(index)
1284 {
1285 case E_PWM_CH0:
1286 case E_PWM_CH1:
1287 case E_PWM_CH2:
1288 case E_PWM_CH3:
1289 case E_PWM_CH4:
1290 case E_PWM_CH5:
1291 case E_PWM_CH6:
1292 case E_PWM_CH7:
1293 case E_PWM_CH8:
1294 case E_PWM_CH9:
1295 printf("[Utopia] The PWM%d is not support\n", (int)index);
1296 UNUSED(bBypassPWM);
1297 break;
1298 default:
1299 break;
1300 }
1301
1302 HAL_SUBBANK0;
1303 }
1304
1305 ////////////////////////////////////////////////////////////////////////////////
1306 /// @brief \b Function \b Name : HAL_PWM01_CntMode
1307 /// @brief \b Function \b Description : Counter mode for PWM0 and PWM1
1308 /// @param <IN> \b PWM_ChNum : Enum of the Counter mode
1309 /// @param <IN> \b None :
1310 /// @param <OUT> \b None :
1311 /// @param <RET> \b PWM_Result :
1312 /// @param <GLOBAL> \b None :
1313 /// @note \n
1314 /// 11: PWM1 donate internal divider to PWM0 \n
1315 /// 10: PWM0 donate internal divider to PWM1 \n
1316 /// 0x: Normal mode \n
1317 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM01_CntMode(PWM_CntMode CntMode)1318 MS_BOOL HAL_PWM01_CntMode(PWM_CntMode CntMode)
1319 {
1320 MS_BOOL ret = FALSE;
1321 //T2 ONLY
1322 UNUSED(CntMode);
1323 return ret;
1324 }
1325
1326 ////////////////////////////////////////////////////////////////////////////////
1327 /// @brief \b Function \b Name : HAL_PWM23_CntMode
1328 /// @brief \b Function \b Description : Counter mode for PWM2 and PWM3
1329 /// @param <IN> \b PWM_ChNum : Enum of the Counter mode
1330 /// @param <IN> \b None :
1331 /// @param <OUT> \b None :
1332 /// @param <RET> \b PWM_Result :
1333 /// @param <GLOBAL> \b None :
1334 /// @note \n
1335 /// 11: PWM3 donate internal divider to PWM2 \n
1336 /// 10: PWM2 donate internal divider to PWM3 \n
1337 /// 0x: Normal mode \n
1338 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM23_CntMode(PWM_CntMode CntMode)1339 MS_BOOL HAL_PWM23_CntMode(PWM_CntMode CntMode)
1340 {
1341 MS_BOOL ret = FALSE;
1342 //T2 ONLY
1343 UNUSED(CntMode);
1344 return ret;
1345 }
1346
1347 ////////////////////////////////////////////////////////////////////////////////
1348 /// @brief \b Function \b Name : HAL_PWM67_CntMode
1349 /// @brief \b Function \b Description : Counter mode for PWM6 and PWM7
1350 /// @param <IN> \b PWM_ChNum : Enum of the Counter mode
1351 /// @param <IN> \b None :
1352 /// @param <OUT> \b None :
1353 /// @param <RET> \b PWM_Result :
1354 /// @param <GLOBAL> \b None :
1355 /// @note \n
1356 /// 11: PWM7 donate internal divider to PWM6 \n
1357 /// 10: PWM6 donate internal divider to PWM7 \n
1358 /// 0x: Normal mode \n
1359 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM67_CntMode(PWM_CntMode CntMode)1360 MS_BOOL HAL_PWM67_CntMode(PWM_CntMode CntMode)
1361 {
1362 MS_BOOL ret = FALSE;
1363 //T2 ONLY
1364 UNUSED(CntMode);
1365 return ret;
1366 }
1367
1368 ////////////////////////////////////////////////////////////////////////////////
1369 /// @brief \b Function \b Name : HAL_PWM_Shift
1370 /// @brief \b Function \b Description : Set the Shift of the specific pwm
1371 /// @param <IN> \b PWM_ChNum : Enum of the PWM CH
1372 /// @param <IN> \b MS_U16 : the 18-bit shift value
1373 /// @param <OUT> \b None :
1374 /// @param <RET> \b None :
1375 /// @param <GLOBAL> \b None :
1376 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_Shift(PWM_ChNum index,MS_U32 u32ShiftPWM)1377 MS_BOOL HAL_PWM_Shift(PWM_ChNum index, MS_U32 u32ShiftPWM)
1378 {
1379 MS_U16 Shift_L, Shift_H;
1380
1381 Shift_L = (MS_U16)(u32ShiftPWM & 0xFFFF);
1382 Shift_H = (MS_U16)(u32ShiftPWM >> 16);
1383
1384 HAL_SUBBANK1;
1385
1386 switch(index)
1387 {
1388 case E_PWM_CH0:
1389 HAL_PWM_Write2Byte(REG_PWM0_SHIFT_L, Shift_L);
1390 HAL_PWM_Write2Byte(REG_PWM0_SHIFT_H, Shift_H);
1391 break;
1392 case E_PWM_CH1:
1393 HAL_PWM_Write2Byte(REG_PWM1_SHIFT_L, Shift_L);
1394 HAL_PWM_Write2Byte(REG_PWM1_SHIFT_H, Shift_H);
1395 break;
1396 case E_PWM_CH2:
1397 HAL_PWM_Write2Byte(REG_PWM2_SHIFT_L, Shift_L);
1398 HAL_PWM_Write2Byte(REG_PWM2_SHIFT_H, Shift_H);
1399 break;
1400 case E_PWM_CH3:
1401 HAL_PWM_Write2Byte(REG_PWM3_SHIFT_L, Shift_L);
1402 HAL_PWM_Write2Byte(REG_PWM3_SHIFT_H, Shift_H);
1403 break;
1404 case E_PWM_CH4:
1405 HAL_PWM_Write2Byte(REG_PWM4_SHIFT_L, Shift_L);
1406 HAL_PWM_Write2Byte(REG_PWM4_SHIFT_H, Shift_H);
1407 break;
1408 case E_PWM_CH5:
1409 case E_PWM_CH6:
1410 case E_PWM_CH7:
1411 case E_PWM_CH8:
1412 case E_PWM_CH9:
1413 printf("[Utopia] The PWM%d is not support\n", (int)index);
1414 UNUSED(Shift_L);UNUSED(Shift_H);
1415 break;
1416 default:
1417 break;
1418 }
1419
1420 HAL_SUBBANK0;
1421
1422 return TRUE;
1423 }
1424
1425 ////////////////////////////////////////////////////////////////////////////////
1426 /// @brief \b Function \b Name : HAL_PWM_GetShift
1427 /// @brief \b Function \b Description : Set the Shift of the specific pwm
1428 /// @param <IN> \b PWM_ChNum : Enum of the PWM CH
1429 /// @param <IN> \b MS_U16 : the 18-bit shift value
1430 /// @param <OUT> \b None :
1431 /// @param <RET> \b MS_U16 : the 18-bit shift value
1432 /// @param <GLOBAL> \b None :
1433 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_GetShift(PWM_ChNum index)1434 MS_U32 HAL_PWM_GetShift(PWM_ChNum index)
1435 {
1436 MS_U16 Shift_L = 0, Shift_H = 0;
1437
1438 HAL_SUBBANK1;
1439
1440 switch(index)
1441 {
1442 case E_PWM_CH0:
1443 Shift_L = HAL_PWM_Read2Byte(REG_PWM0_SHIFT_L);
1444 Shift_H = HAL_PWM_Read2Byte(REG_PWM0_SHIFT_H);
1445 break;
1446 case E_PWM_CH1:
1447 Shift_L = HAL_PWM_Read2Byte(REG_PWM1_SHIFT_L);
1448 Shift_H = HAL_PWM_Read2Byte(REG_PWM1_SHIFT_H);
1449 break;
1450 case E_PWM_CH2:
1451 Shift_L = HAL_PWM_Read2Byte(REG_PWM2_SHIFT_L);
1452 Shift_H = HAL_PWM_Read2Byte(REG_PWM2_SHIFT_H);
1453 break;
1454 case E_PWM_CH3:
1455 Shift_L = HAL_PWM_Read2Byte(REG_PWM3_SHIFT_L);
1456 Shift_H = HAL_PWM_Read2Byte(REG_PWM3_SHIFT_H);
1457 break;
1458 case E_PWM_CH4:
1459 Shift_L = HAL_PWM_Read2Byte(REG_PWM4_SHIFT_L);
1460 Shift_H = HAL_PWM_Read2Byte(REG_PWM4_SHIFT_H);
1461 break;
1462 case E_PWM_CH5:
1463 case E_PWM_CH6:
1464 case E_PWM_CH7:
1465 case E_PWM_CH8:
1466 case E_PWM_CH9:
1467 printf("[Utopia] The PWM%d is not support\n", (int)index);
1468 break;
1469 default:
1470 break;
1471 }
1472
1473 HAL_SUBBANK0;
1474
1475 return ((Shift_H<<16) | Shift_L);
1476 }
1477
HAL_PWM_Nvsync(PWM_ChNum index,MS_BOOL bNvsPWM)1478 void HAL_PWM_Nvsync(PWM_ChNum index, MS_BOOL bNvsPWM)
1479 {
1480
1481 HAL_SUBBANK1;
1482
1483 switch(index)
1484 {
1485 case E_PWM_CH0:
1486 HAL_PWM_WriteRegBit(REG_PWM0_NVS,BITS(0:0,bNvsPWM),BMASK(0:0));
1487 break;
1488 case E_PWM_CH1:
1489 HAL_PWM_WriteRegBit(REG_PWM1_NVS,BITS(1:1,bNvsPWM),BMASK(1:1));
1490 break;
1491 case E_PWM_CH2:
1492 HAL_PWM_WriteRegBit(REG_PWM2_NVS,BITS(2:2,bNvsPWM),BMASK(2:2));
1493 break;
1494 case E_PWM_CH3:
1495 HAL_PWM_WriteRegBit(REG_PWM3_NVS,BITS(3:3,bNvsPWM),BMASK(3:3));
1496 break;
1497 case E_PWM_CH4:
1498 HAL_PWM_WriteRegBit(REG_PWM4_NVS,BITS(4:4,bNvsPWM),BMASK(4:4));
1499 break;
1500 case E_PWM_CH5:
1501 case E_PWM_CH6:
1502 case E_PWM_CH7:
1503 case E_PWM_CH8:
1504 case E_PWM_CH9:
1505 printf("[Utopia] The PWM%d is not support\n", (int)index);
1506 UNUSED(bNvsPWM);
1507 break;
1508 default:
1509 break;
1510 }
1511
1512 HAL_SUBBANK0;
1513 }
1514
HAL_PWM_Align(PWM_ChNum index,MS_BOOL bAliPWM)1515 void HAL_PWM_Align(PWM_ChNum index, MS_BOOL bAliPWM)
1516 {
1517
1518 HAL_SUBBANK1;
1519
1520 switch(index)
1521 {
1522 case E_PWM_CH0:
1523 HAL_PWM_WriteRegBit(REG_PWM0_Align,BITS(0:0,bAliPWM),BMASK(0:0));
1524 break;
1525 case E_PWM_CH1:
1526 HAL_PWM_WriteRegBit(REG_PWM1_Align,BITS(1:1,bAliPWM),BMASK(1:1));
1527 break;
1528 case E_PWM_CH2:
1529 HAL_PWM_WriteRegBit(REG_PWM2_Align,BITS(2:2,bAliPWM),BMASK(2:2));
1530 break;
1531 case E_PWM_CH3:
1532 HAL_PWM_WriteRegBit(REG_PWM3_Align,BITS(3:3,bAliPWM),BMASK(3:3));
1533 break;
1534 case E_PWM_CH4:
1535 HAL_PWM_WriteRegBit(REG_PWM4_Align,BITS(4:4,bAliPWM),BMASK(4:4));
1536 break;
1537 case E_PWM_CH5:
1538 case E_PWM_CH6:
1539 case E_PWM_CH7:
1540 case E_PWM_CH8:
1541 case E_PWM_CH9:
1542 printf("[Utopia] The PWM%d is not support\n", (int)index);
1543 UNUSED(bAliPWM);
1544 break;
1545 default:
1546 break;
1547 }
1548
1549 HAL_SUBBANK0;
1550 }
1551
1552 PWM_3D_RegisterOffset g_ArrayPWM3D_RegisterOffset[PWM_Num][MAX_3DPWM_NUM] =
1553 {
1554 { //PWM0
1555 {//PWM0_Waveform_0
1556 {0, 0}, //PWM0_Waveform_0_Shift ==> use: HAL_PWM_Shift()
1557 {0, 0}, //PWM0_Waveform_0_duty ==> use: HAL_PWM_DutyCycle()
1558 },
1559 {//PWM0_Waveform_1
1560 {REG_PWM0_HIT_CNT_ST, 16}, //PWM0_Waveform_1_Shift
1561 {REG_PWM0_HIT_CNT_END, 16}, //PWM0_Waveform_1_duty
1562 },
1563 {//PWM0_Waveform_2
1564 {REG_PWM0_HIT_CNT_ST2, 16}, //PWM0_Waveform_2_Shift
1565 {REG_PWM0_HIT_CNT_END2, 16}, //PWM0_Waveform_2_duty
1566 },
1567 {//PWM0_Waveform_3
1568 {REG_PWM0_SHIFT4, 16}, //PWM0_Waveform_3_Shift
1569 {REG_PWM0_DUTY4, 16}, //PWM0_Waveform_3_duty
1570 },
1571 },
1572
1573 { //PWM1
1574 {//PWM1_Waveform_0
1575 {0, 0}, //PWM1_Waveform_0_Shift ==> use: HAL_PWM_Shift()
1576 {0, 0}, //PWM1_Waveform_0_duty ==> use: HAL_PWM_DutyCycle()
1577 },
1578 {//PWM1_Waveform_1
1579 {REG_PWM1_HIT_CNT_ST, 16}, //PWM1_Waveform_1_Shift
1580 {REG_PWM1_HIT_CNT_END, 16}, //PWM1_Waveform_1_duty
1581 },
1582 {//PWM1_Waveform_2
1583 {REG_PWM1_HIT_CNT_ST2, 16}, //PWM1_Waveform_2_Shift
1584 {REG_PWM1_HIT_CNT_END2, 16}, //PWM1_Waveform_2_duty
1585 },
1586 {//PWM1_Waveform_3
1587 {REG_PWM1_SHIFT4, 16}, //PWM1_Waveform_3_Shift
1588 {REG_PWM1_DUTY4, 16}, //PWM1_Waveform_3_duty
1589 },
1590 },
1591 };
1592
HAL_PWM_IsSupport3D(PWM_ChNum index)1593 MS_BOOL HAL_PWM_IsSupport3D(PWM_ChNum index)
1594 {
1595 //Only PWM0 & PWM1 Support 3D Function
1596 switch (index)
1597 {
1598 case E_PWM_CH0:
1599 case E_PWM_CH1:
1600 return TRUE;
1601
1602 default:
1603 return FALSE;
1604 }
1605 }
1606
HAL_PWM_SetMultiDiff(MS_BOOL bEnable)1607 void HAL_PWM_SetMultiDiff(MS_BOOL bEnable)
1608 {
1609 HAL_SUBBANK1;
1610 HAL_PWM_WriteRegBit(REG_PWM_MULTI_DIFF, PWM_MULTI_DIEF_EN, bEnable);
1611 HAL_SUBBANK0;
1612 }
1613
HAL_PWM_Set3D_DiffWaveform(PWM_ChNum index,MS_U8 u8WaveformIndex,MS_U32 u32Shift,MS_U32 u32Duty)1614 MS_BOOL HAL_PWM_Set3D_DiffWaveform(PWM_ChNum index, MS_U8 u8WaveformIndex, MS_U32 u32Shift, MS_U32 u32Duty)
1615 {
1616 MS_BOOL bReturn = TRUE;
1617 PWM_3D_RegisterOffset *pReigsterOffset = (PWM_3D_RegisterOffset *)&g_ArrayPWM3D_RegisterOffset[index][u8WaveformIndex];
1618
1619 if (u8WaveformIndex == 0)
1620 {
1621 bReturn &= HAL_PWM_Shift(index, u32Shift);
1622 HAL_PWM_DutyCycle(index, u32Duty);
1623 }
1624 else
1625 {
1626 HAL_SUBBANK1;
1627 bReturn &= HAL_PWM_WriteNumberByte(pReigsterOffset->regShift.u32RegOffset, u32Shift, pReigsterOffset->regShift.u8NumBit);
1628 bReturn &= HAL_PWM_WriteNumberByte(pReigsterOffset->regDuty.u32RegOffset, u32Duty, pReigsterOffset->regDuty.u8NumBit);
1629 HAL_SUBBANK0
1630 }
1631
1632 return bReturn;
1633 }
1634
1635 //---------------------------PM Base--------------------------------//
1636
HAL_PM_PWM_Enable(void)1637 void HAL_PM_PWM_Enable(void)
1638 {
1639 HAL_PM_WriteRegBit(REG_PM_PWM0_IS_GPIO,BITS(5:5,0),BMASK(5:5));
1640 HAL_PM_WriteRegBit(reg_pwm_as_chip_config,BITS(0:0,0),BMASK(0:0));//reg_pwm_pm_is_PWM
1641 }
1642
HAL_PM_PWM_Period(MS_U16 u16PeriodPWM)1643 void HAL_PM_PWM_Period(MS_U16 u16PeriodPWM)
1644 {
1645 MS_U16 Period;
1646 Period = u16PeriodPWM;
1647 HAL_PM_Write2Byte(REG_PM_PWM0_PERIOD, Period);
1648 }
1649
HAL_PM_PWM_DutyCycle(MS_U16 u16DutyPWM)1650 void HAL_PM_PWM_DutyCycle(MS_U16 u16DutyPWM)
1651 {
1652 MS_U16 Duty;
1653 Duty =u16DutyPWM;
1654 HAL_PM_Write2Byte(REG_PM_PWM0_DUTY, Duty);
1655 }
1656
HAL_PM_PWM_Div(MS_U8 u8DivPWM)1657 void HAL_PM_PWM_Div(MS_U8 u8DivPWM)
1658 {
1659 MS_U8 Div;
1660 Div = u8DivPWM;
1661 HAL_PM_Write2Byte(REG_PM_PWM0_DIV, Div);
1662 }
1663
HAL_PM_PWM_Polarity(MS_BOOL bPolPWM)1664 void HAL_PM_PWM_Polarity(MS_BOOL bPolPWM)
1665 {
1666 HAL_PM_WriteRegBit(REG_PM_PWM0_PORARITY,BITS(0:0,bPolPWM),BMASK(0:0));
1667 }
1668
HAL_PM_PWM_DBen(MS_BOOL bdbenPWM)1669 void HAL_PM_PWM_DBen(MS_BOOL bdbenPWM)
1670 {
1671 HAL_PM_WriteRegBit(REG_PM_PWM0_DBEN,BITS(1:1,bdbenPWM),BMASK(1:1));
1672 }
1673
1674 ////////////////////////////////////////////////////////////////////////////////
1675 /// @brief \b Function \b Name : HAL_PWM_INV_3D_Flag
1676 /// @brief \b Function \b Description : Set Inverse 3D flag
1677 /// @param <IN> \b MS_BOOL : 1 for Enable; 0 for Disable
1678 ////////////////////////////////////////////////////////////////////////////////
HAL_PWM_INV_3D_Flag(MS_BOOL bInvPWM)1679 MS_BOOL HAL_PWM_INV_3D_Flag(MS_BOOL bInvPWM)
1680 {
1681 MS_BOOL ret = FALSE;
1682 HAL_SUBBANK1;
1683 HAL_PM_WriteRegBit(REG_INV_3D_FLAG,BITS(15:15,bInvPWM),BMASK(15:15));
1684 ret = true;
1685 HAL_SUBBANK0;
1686 return ret;
1687 }
1688
HAL_PWM_LR_RST_RISING(PWM_ChNum index,MS_BOOL bMask)1689 static void HAL_PWM_LR_RST_RISING(PWM_ChNum index, MS_BOOL bMask)
1690 {
1691 switch (index)
1692 {
1693 case E_PWM_CH0:
1694 HAL_PWM_WriteRegBit(REG_INV_3D_FLAG, BITS(0:0, bMask), BMASK(0:0));
1695 break;
1696
1697 case E_PWM_CH1:
1698 HAL_PWM_WriteRegBit(REG_INV_3D_FLAG, BITS(1:1, bMask), BMASK(1:1));
1699 break;
1700
1701 case E_PWM_CH2:
1702 HAL_PWM_WriteRegBit(REG_INV_3D_FLAG, BITS(2:2, bMask), BMASK(2:2));
1703 break;
1704
1705 case E_PWM_CH3:
1706 HAL_PWM_WriteRegBit(REG_INV_3D_FLAG, BITS(3:3, bMask), BMASK(3:3));
1707 break;
1708
1709 default:
1710 break;
1711 }
1712 }
1713
HAL_PWM_LR_RST_FALLING(PWM_ChNum index,MS_BOOL bMask)1714 static void HAL_PWM_LR_RST_FALLING(PWM_ChNum index, MS_BOOL bMask)
1715 {
1716 switch (index)
1717 {
1718 case E_PWM_CH0:
1719 HAL_PWM_WriteRegBit(REG_INV_3D_FLAG, BITS(8:8, bMask), BMASK(8:8));
1720 break;
1721
1722 case E_PWM_CH1:
1723 HAL_PWM_WriteRegBit(REG_INV_3D_FLAG, BITS(9:9, bMask), BMASK(9:9));
1724 break;
1725
1726 case E_PWM_CH2:
1727 HAL_PWM_WriteRegBit(REG_INV_3D_FLAG, BITS(10:10, bMask), BMASK(10:10));
1728 break;
1729
1730 case E_PWM_CH3:
1731 HAL_PWM_WriteRegBit(REG_INV_3D_FLAG, BITS(11:11, bMask), BMASK(11:11));
1732 break;
1733
1734 default:
1735 break;
1736 }
1737 }
1738
HAL_PWM_LR_RST_SEL(PWM_ChNum index,N_LR_SYNC_SEL eLR_Sync)1739 void HAL_PWM_LR_RST_SEL(PWM_ChNum index, N_LR_SYNC_SEL eLR_Sync)
1740 {
1741 switch (eLR_Sync)
1742 {
1743 case E_VSYNC:
1744 HAL_PWM_LR_RST_RISING(index, FALSE);
1745 HAL_PWM_LR_RST_FALLING(index, FALSE);
1746 break;
1747
1748 case E_LR_RISING:
1749 HAL_PWM_LR_RST_RISING(index, TRUE);
1750 HAL_PWM_LR_RST_FALLING(index, FALSE);
1751 break;
1752
1753 case E_LR_FALLING:
1754 HAL_PWM_LR_RST_RISING(index, FALSE);
1755 HAL_PWM_LR_RST_FALLING(index, TRUE);
1756 break;
1757
1758 case E_LR_RISING_FALLING:
1759 HAL_PWM_LR_RST_RISING(index, TRUE);
1760 HAL_PWM_LR_RST_FALLING(index, TRUE);
1761 break;
1762
1763 default:
1764 break;
1765 }
1766 }
1767