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Searched refs:REG_PWM0_NVS (Results 1 – 22 of 22) sorted by relevance

/utopia/UTPA2-700.0.x/modules/pwm/hal/macan/pwm/
H A DregPWM.h296 #define REG_PWM0_NVS (0x34) //bit0 macro
H A DhalPWM.c1169 HAL_PWM_WriteRegBit(REG_PWM0_NVS,BITS(0:0,bNvsPWM),BMASK(0:0)); in HAL_PWM_Nvsync()
/utopia/UTPA2-700.0.x/modules/pwm/hal/messi/pwm/
H A DregPWM.h296 #define REG_PWM0_NVS (0x34) //bit0 macro
H A DhalPWM.c1494 HAL_PWM_WriteRegBit(REG_PWM0_NVS,BITS(0:0,bNvsPWM),BMASK(0:0)); in HAL_PWM_Nvsync()
/utopia/UTPA2-700.0.x/modules/pwm/hal/mooney/pwm/
H A DregPWM.h296 #define REG_PWM0_NVS (0x34) //bit0 macro
H A DhalPWM.c1486 HAL_PWM_WriteRegBit(REG_PWM0_NVS,BITS(0:0,bNvsPWM),BMASK(0:0)); in HAL_PWM_Nvsync()
/utopia/UTPA2-700.0.x/modules/pwm/hal/mainz/pwm/
H A DregPWM.h296 #define REG_PWM0_NVS (0x34) //bit0 macro
H A DhalPWM.c1489 HAL_PWM_WriteRegBit(REG_PWM0_NVS,BITS(0:0,bNvsPWM),BMASK(0:0)); in HAL_PWM_Nvsync()
/utopia/UTPA2-700.0.x/modules/pwm/hal/manhattan/pwm/
H A DregPWM.h296 #define REG_PWM0_NVS (0x34) //bit0 macro
H A DhalPWM.c1486 HAL_PWM_WriteRegBit(REG_PWM0_NVS,BITS(0:0,bNvsPWM),BMASK(0:0)); in HAL_PWM_Nvsync()
/utopia/UTPA2-700.0.x/modules/pwm/hal/maxim/pwm/
H A DregPWM.h305 #define REG_PWM0_NVS (0x34) //bit0 macro
H A DhalPWM.c1486 HAL_PWM_WriteRegBit(REG_PWM0_NVS,BITS(0:0,bNvsPWM),BMASK(0:0)); in HAL_PWM_Nvsync()
/utopia/UTPA2-700.0.x/modules/pwm/hal/mustang/pwm/
H A DregPWM.h288 #define REG_PWM0_NVS (0x34) //bit0 macro
H A DhalPWM.c1175 HAL_PWM_WriteRegBit(REG_PWM0_NVS, BITS(0:0, bNvsPWM), BMASK(0:0)); in HAL_PWM_Nvsync()
/utopia/UTPA2-700.0.x/modules/pwm/hal/M7621/pwm/
H A DregPWM.h305 #define REG_PWM0_NVS (0x34) //bit0 macro
H A DhalPWM.c1486 HAL_PWM_WriteRegBit(REG_PWM0_NVS,BITS(0:0,bNvsPWM),BMASK(0:0)); in HAL_PWM_Nvsync()
/utopia/UTPA2-700.0.x/modules/pwm/hal/M7821/pwm/
H A DregPWM.h305 #define REG_PWM0_NVS (0x34) //bit0 macro
H A DhalPWM.c1487 HAL_PWM_WriteRegBit(REG_PWM0_NVS,BITS(0:0,bNvsPWM),BMASK(0:0)); in HAL_PWM_Nvsync()
/utopia/UTPA2-700.0.x/modules/pwm/hal/maldives/pwm/
H A DregPWM.h284 #define REG_PWM0_NVS (0x34) //bit0 macro
H A DhalPWM.c1170 HAL_PWM_WriteRegBit(REG_PWM0_NVS, BITS(0:0, bNvsPWM), BMASK(0:0)); in HAL_PWM_Nvsync()
/utopia/UTPA2-700.0.x/modules/pwm/hal/maserati/pwm/
H A DregPWM.h305 #define REG_PWM0_NVS (0x34) //bit0 macro
H A DhalPWM.c1487 HAL_PWM_WriteRegBit(REG_PWM0_NVS,BITS(0:0,bNvsPWM),BMASK(0:0)); in HAL_PWM_Nvsync()