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Searched refs:REG_DVI_DTOP_DUAL_P0_BASE (Results 1 – 25 of 27) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/
H A Dhwreg_hdmi.h3563 #define REG_DVI_DTOP_DUAL_P0_00_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x00)
3564 #define REG_DVI_DTOP_DUAL_P0_00_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x01)
3565 #define REG_DVI_DTOP_DUAL_P0_01_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x02)
3566 #define REG_DVI_DTOP_DUAL_P0_01_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x03)
3567 #define REG_DVI_DTOP_DUAL_P0_02_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x04)
3568 #define REG_DVI_DTOP_DUAL_P0_02_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x05)
3569 #define REG_DVI_DTOP_DUAL_P0_03_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x06)
3570 #define REG_DVI_DTOP_DUAL_P0_03_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x07)
3571 #define REG_DVI_DTOP_DUAL_P0_04_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x08)
3572 #define REG_DVI_DTOP_DUAL_P0_04_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h588 #define REG_DVI_DTOP_DUAL_P0_BASE 0x171000UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/
H A Dhwreg_hdmi.h3565 #define REG_DVI_DTOP_DUAL_P0_00_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x00)
3566 #define REG_DVI_DTOP_DUAL_P0_00_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x01)
3567 #define REG_DVI_DTOP_DUAL_P0_01_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x02)
3568 #define REG_DVI_DTOP_DUAL_P0_01_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x03)
3569 #define REG_DVI_DTOP_DUAL_P0_02_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x04)
3570 #define REG_DVI_DTOP_DUAL_P0_02_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x05)
3571 #define REG_DVI_DTOP_DUAL_P0_03_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x06)
3572 #define REG_DVI_DTOP_DUAL_P0_03_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x07)
3573 #define REG_DVI_DTOP_DUAL_P0_04_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x08)
3574 #define REG_DVI_DTOP_DUAL_P0_04_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h570 #define REG_DVI_DTOP_DUAL_P0_BASE 0x172000UL macro
573 #define REG_DVI_DTOP_DUAL_P1_BASE REG_DVI_DTOP_DUAL_P0_BASE
576 #define REG_DVI_DTOP_DUAL_P2_BASE REG_DVI_DTOP_DUAL_P0_BASE
579 #define REG_DVI_DTOP_DUAL_P3_BASE REG_DVI_DTOP_DUAL_P0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/
H A Dhwreg_hdmi.h3563 #define REG_DVI_DTOP_DUAL_P0_00_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x00)
3564 #define REG_DVI_DTOP_DUAL_P0_00_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x01)
3565 #define REG_DVI_DTOP_DUAL_P0_01_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x02)
3566 #define REG_DVI_DTOP_DUAL_P0_01_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x03)
3567 #define REG_DVI_DTOP_DUAL_P0_02_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x04)
3568 #define REG_DVI_DTOP_DUAL_P0_02_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x05)
3569 #define REG_DVI_DTOP_DUAL_P0_03_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x06)
3570 #define REG_DVI_DTOP_DUAL_P0_03_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x07)
3571 #define REG_DVI_DTOP_DUAL_P0_04_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x08)
3572 #define REG_DVI_DTOP_DUAL_P0_04_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h548 #define REG_DVI_DTOP_DUAL_P0_BASE 0x171000UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/
H A Dhwreg_hdmi.h3565 #define REG_DVI_DTOP_DUAL_P0_00_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x00)
3566 #define REG_DVI_DTOP_DUAL_P0_00_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x01)
3567 #define REG_DVI_DTOP_DUAL_P0_01_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x02)
3568 #define REG_DVI_DTOP_DUAL_P0_01_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x03)
3569 #define REG_DVI_DTOP_DUAL_P0_02_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x04)
3570 #define REG_DVI_DTOP_DUAL_P0_02_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x05)
3571 #define REG_DVI_DTOP_DUAL_P0_03_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x06)
3572 #define REG_DVI_DTOP_DUAL_P0_03_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x07)
3573 #define REG_DVI_DTOP_DUAL_P0_04_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x08)
3574 #define REG_DVI_DTOP_DUAL_P0_04_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h572 #define REG_DVI_DTOP_DUAL_P0_BASE 0x172000UL macro
575 #define REG_DVI_DTOP_DUAL_P1_BASE REG_DVI_DTOP_DUAL_P0_BASE
578 #define REG_DVI_DTOP_DUAL_P2_BASE REG_DVI_DTOP_DUAL_P0_BASE
581 #define REG_DVI_DTOP_DUAL_P3_BASE REG_DVI_DTOP_DUAL_P0_BASE
H A Dmhal_xc_chip_config.h.0571 #define REG_DVI_DTOP_DUAL_P0_BASE 0x172000UL
574 #define REG_DVI_DTOP_DUAL_P1_BASE REG_DVI_DTOP_DUAL_P0_BASE
577 #define REG_DVI_DTOP_DUAL_P2_BASE REG_DVI_DTOP_DUAL_P0_BASE
580 #define REG_DVI_DTOP_DUAL_P3_BASE REG_DVI_DTOP_DUAL_P0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/
H A Dhwreg_hdmi.h3563 #define REG_DVI_DTOP_DUAL_P0_00_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x00)
3564 #define REG_DVI_DTOP_DUAL_P0_00_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x01)
3565 #define REG_DVI_DTOP_DUAL_P0_01_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x02)
3566 #define REG_DVI_DTOP_DUAL_P0_01_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x03)
3567 #define REG_DVI_DTOP_DUAL_P0_02_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x04)
3568 #define REG_DVI_DTOP_DUAL_P0_02_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x05)
3569 #define REG_DVI_DTOP_DUAL_P0_03_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x06)
3570 #define REG_DVI_DTOP_DUAL_P0_03_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x07)
3571 #define REG_DVI_DTOP_DUAL_P0_04_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x08)
3572 #define REG_DVI_DTOP_DUAL_P0_04_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h575 #define REG_DVI_DTOP_DUAL_P0_BASE 0x171000UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/
H A Dhwreg_hdmi.h3565 #define REG_DVI_DTOP_DUAL_P0_00_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x00)
3566 #define REG_DVI_DTOP_DUAL_P0_00_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x01)
3567 #define REG_DVI_DTOP_DUAL_P0_01_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x02)
3568 #define REG_DVI_DTOP_DUAL_P0_01_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x03)
3569 #define REG_DVI_DTOP_DUAL_P0_02_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x04)
3570 #define REG_DVI_DTOP_DUAL_P0_02_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x05)
3571 #define REG_DVI_DTOP_DUAL_P0_03_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x06)
3572 #define REG_DVI_DTOP_DUAL_P0_03_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x07)
3573 #define REG_DVI_DTOP_DUAL_P0_04_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x08)
3574 #define REG_DVI_DTOP_DUAL_P0_04_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h564 #define REG_DVI_DTOP_DUAL_P0_BASE 0x172000UL macro
567 #define REG_DVI_DTOP_DUAL_P1_BASE REG_DVI_DTOP_DUAL_P0_BASE
570 #define REG_DVI_DTOP_DUAL_P2_BASE REG_DVI_DTOP_DUAL_P0_BASE
573 #define REG_DVI_DTOP_DUAL_P3_BASE REG_DVI_DTOP_DUAL_P0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/
H A Dhwreg_hdmi.h3565 #define REG_DVI_DTOP_DUAL_P0_00_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x00)
3566 #define REG_DVI_DTOP_DUAL_P0_00_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x01)
3567 #define REG_DVI_DTOP_DUAL_P0_01_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x02)
3568 #define REG_DVI_DTOP_DUAL_P0_01_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x03)
3569 #define REG_DVI_DTOP_DUAL_P0_02_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x04)
3570 #define REG_DVI_DTOP_DUAL_P0_02_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x05)
3571 #define REG_DVI_DTOP_DUAL_P0_03_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x06)
3572 #define REG_DVI_DTOP_DUAL_P0_03_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x07)
3573 #define REG_DVI_DTOP_DUAL_P0_04_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x08)
3574 #define REG_DVI_DTOP_DUAL_P0_04_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h570 #define REG_DVI_DTOP_DUAL_P0_BASE 0x172000UL macro
573 #define REG_DVI_DTOP_DUAL_P1_BASE REG_DVI_DTOP_DUAL_P0_BASE
576 #define REG_DVI_DTOP_DUAL_P2_BASE REG_DVI_DTOP_DUAL_P0_BASE
579 #define REG_DVI_DTOP_DUAL_P3_BASE REG_DVI_DTOP_DUAL_P0_BASE
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/
H A Dhwreg_hdmi.h3563 #define REG_DVI_DTOP_DUAL_P0_00_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x00)
3564 #define REG_DVI_DTOP_DUAL_P0_00_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x01)
3565 #define REG_DVI_DTOP_DUAL_P0_01_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x02)
3566 #define REG_DVI_DTOP_DUAL_P0_01_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x03)
3567 #define REG_DVI_DTOP_DUAL_P0_02_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x04)
3568 #define REG_DVI_DTOP_DUAL_P0_02_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x05)
3569 #define REG_DVI_DTOP_DUAL_P0_03_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x06)
3570 #define REG_DVI_DTOP_DUAL_P0_03_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x07)
3571 #define REG_DVI_DTOP_DUAL_P0_04_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x08)
3572 #define REG_DVI_DTOP_DUAL_P0_04_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h546 #define REG_DVI_DTOP_DUAL_P0_BASE 0x171000UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/
H A Dhwreg_hdmi.h3564 #define REG_DVI_DTOP_DUAL_P0_00_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x00)
3565 #define REG_DVI_DTOP_DUAL_P0_00_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x01)
3566 #define REG_DVI_DTOP_DUAL_P0_01_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x02)
3567 #define REG_DVI_DTOP_DUAL_P0_01_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x03)
3568 #define REG_DVI_DTOP_DUAL_P0_02_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x04)
3569 #define REG_DVI_DTOP_DUAL_P0_02_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x05)
3570 #define REG_DVI_DTOP_DUAL_P0_03_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x06)
3571 #define REG_DVI_DTOP_DUAL_P0_03_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x07)
3572 #define REG_DVI_DTOP_DUAL_P0_04_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x08)
3573 #define REG_DVI_DTOP_DUAL_P0_04_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h529 #define REG_DVI_DTOP_DUAL_P0_BASE 0x171000UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/
H A Dhwreg_hdmi.h3563 #define REG_DVI_DTOP_DUAL_P0_00_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x00)
3564 #define REG_DVI_DTOP_DUAL_P0_00_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x01)
3565 #define REG_DVI_DTOP_DUAL_P0_01_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x02)
3566 #define REG_DVI_DTOP_DUAL_P0_01_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x03)
3567 #define REG_DVI_DTOP_DUAL_P0_02_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x04)
3568 #define REG_DVI_DTOP_DUAL_P0_02_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x05)
3569 #define REG_DVI_DTOP_DUAL_P0_03_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x06)
3570 #define REG_DVI_DTOP_DUAL_P0_03_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x07)
3571 #define REG_DVI_DTOP_DUAL_P0_04_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x08)
3572 #define REG_DVI_DTOP_DUAL_P0_04_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h622 #define REG_DVI_DTOP_DUAL_P0_BASE 0x171000UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/include/
H A Dhwreg_hdmi.h3563 #define REG_DVI_DTOP_DUAL_P0_00_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x00)
3564 #define REG_DVI_DTOP_DUAL_P0_00_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x01)
3565 #define REG_DVI_DTOP_DUAL_P0_01_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x02)
3566 #define REG_DVI_DTOP_DUAL_P0_01_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x03)
3567 #define REG_DVI_DTOP_DUAL_P0_02_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x04)
3568 #define REG_DVI_DTOP_DUAL_P0_02_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x05)
3569 #define REG_DVI_DTOP_DUAL_P0_03_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x06)
3570 #define REG_DVI_DTOP_DUAL_P0_03_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x07)
3571 #define REG_DVI_DTOP_DUAL_P0_04_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x08)
3572 #define REG_DVI_DTOP_DUAL_P0_04_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x09)
[all …]
H A Dmhal_xc_chip_config.h634 #define REG_DVI_DTOP_DUAL_P0_BASE 0x171000UL macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/
H A Dhwreg_hdmi.h3563 #define REG_DVI_DTOP_DUAL_P0_00_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x00)
3564 #define REG_DVI_DTOP_DUAL_P0_00_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x01)
3565 #define REG_DVI_DTOP_DUAL_P0_01_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x02)
3566 #define REG_DVI_DTOP_DUAL_P0_01_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x03)
3567 #define REG_DVI_DTOP_DUAL_P0_02_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x04)
3568 #define REG_DVI_DTOP_DUAL_P0_02_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x05)
3569 #define REG_DVI_DTOP_DUAL_P0_03_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x06)
3570 #define REG_DVI_DTOP_DUAL_P0_03_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x07)
3571 #define REG_DVI_DTOP_DUAL_P0_04_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x08)
3572 #define REG_DVI_DTOP_DUAL_P0_04_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x09)
[all …]
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/include/
H A Dhwreg_hdmi.h3563 #define REG_DVI_DTOP_DUAL_P0_00_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x00)
3564 #define REG_DVI_DTOP_DUAL_P0_00_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x01)
3565 #define REG_DVI_DTOP_DUAL_P0_01_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x02)
3566 #define REG_DVI_DTOP_DUAL_P0_01_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x03)
3567 #define REG_DVI_DTOP_DUAL_P0_02_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x04)
3568 #define REG_DVI_DTOP_DUAL_P0_02_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x05)
3569 #define REG_DVI_DTOP_DUAL_P0_03_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x06)
3570 #define REG_DVI_DTOP_DUAL_P0_03_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x07)
3571 #define REG_DVI_DTOP_DUAL_P0_04_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x08)
3572 #define REG_DVI_DTOP_DUAL_P0_04_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x09)
[all …]

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