1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HWREG_HDMI_H_ 96 #define _HWREG_HDMI_H_ 97 98 99 //============================================================= 100 // DVI DTOP 101 102 #define REG_DVI_DTOP_00_L (REG_DVI_DTOP_BASE + 0x00) 103 #define REG_DVI_DTOP_00_H (REG_DVI_DTOP_BASE + 0x01) 104 #define REG_DVI_DTOP_01_L (REG_DVI_DTOP_BASE + 0x02) 105 #define REG_DVI_DTOP_01_H (REG_DVI_DTOP_BASE + 0x03) 106 #define REG_DVI_DTOP_02_L (REG_DVI_DTOP_BASE + 0x04) 107 #define REG_DVI_DTOP_02_H (REG_DVI_DTOP_BASE + 0x05) 108 #define REG_DVI_DTOP_03_L (REG_DVI_DTOP_BASE + 0x06) 109 #define REG_DVI_DTOP_03_H (REG_DVI_DTOP_BASE + 0x07) 110 #define REG_DVI_DTOP_04_L (REG_DVI_DTOP_BASE + 0x08) 111 #define REG_DVI_DTOP_04_H (REG_DVI_DTOP_BASE + 0x09) 112 #define REG_DVI_DTOP_05_L (REG_DVI_DTOP_BASE + 0x0A) 113 #define REG_DVI_DTOP_05_H (REG_DVI_DTOP_BASE + 0x0B) 114 #define REG_DVI_DTOP_06_L (REG_DVI_DTOP_BASE + 0x0C) 115 #define REG_DVI_DTOP_06_H (REG_DVI_DTOP_BASE + 0x0D) 116 #define REG_DVI_DTOP_07_L (REG_DVI_DTOP_BASE + 0x0E) 117 #define REG_DVI_DTOP_07_H (REG_DVI_DTOP_BASE + 0x0F) 118 #define REG_DVI_DTOP_08_L (REG_DVI_DTOP_BASE + 0x10) 119 #define REG_DVI_DTOP_08_H (REG_DVI_DTOP_BASE + 0x11) 120 #define REG_DVI_DTOP_09_L (REG_DVI_DTOP_BASE + 0x12) 121 #define REG_DVI_DTOP_09_H (REG_DVI_DTOP_BASE + 0x13) 122 #define REG_DVI_DTOP_0A_L (REG_DVI_DTOP_BASE + 0x14) 123 #define REG_DVI_DTOP_0A_H (REG_DVI_DTOP_BASE + 0x15) 124 #define REG_DVI_DTOP_0B_L (REG_DVI_DTOP_BASE + 0x16) 125 #define REG_DVI_DTOP_0B_H (REG_DVI_DTOP_BASE + 0x17) 126 #define REG_DVI_DTOP_0C_L (REG_DVI_DTOP_BASE + 0x18) 127 #define REG_DVI_DTOP_0C_H (REG_DVI_DTOP_BASE + 0x19) 128 #define REG_DVI_DTOP_0D_L (REG_DVI_DTOP_BASE + 0x1A) 129 #define REG_DVI_DTOP_0D_H (REG_DVI_DTOP_BASE + 0x1B) 130 #define REG_DVI_DTOP_0E_L (REG_DVI_DTOP_BASE + 0x1C) 131 #define REG_DVI_DTOP_0E_H (REG_DVI_DTOP_BASE + 0x1D) 132 #define REG_DVI_DTOP_0F_L (REG_DVI_DTOP_BASE + 0x1E) 133 #define REG_DVI_DTOP_0F_H (REG_DVI_DTOP_BASE + 0x1F) 134 #define REG_DVI_DTOP_10_L (REG_DVI_DTOP_BASE + 0x20) 135 #define REG_DVI_DTOP_10_H (REG_DVI_DTOP_BASE + 0x21) 136 #define REG_DVI_DTOP_11_L (REG_DVI_DTOP_BASE + 0x22) 137 #define REG_DVI_DTOP_11_H (REG_DVI_DTOP_BASE + 0x23) 138 #define REG_DVI_DTOP_12_L (REG_DVI_DTOP_BASE + 0x24) 139 #define REG_DVI_DTOP_12_H (REG_DVI_DTOP_BASE + 0x25) 140 #define REG_DVI_DTOP_13_L (REG_DVI_DTOP_BASE + 0x26) 141 #define REG_DVI_DTOP_13_H (REG_DVI_DTOP_BASE + 0x27) 142 #define REG_DVI_DTOP_14_L (REG_DVI_DTOP_BASE + 0x28) 143 #define REG_DVI_DTOP_14_H (REG_DVI_DTOP_BASE + 0x29) 144 #define REG_DVI_DTOP_15_L (REG_DVI_DTOP_BASE + 0x2A) 145 #define REG_DVI_DTOP_15_H (REG_DVI_DTOP_BASE + 0x2B) 146 #define REG_DVI_DTOP_16_L (REG_DVI_DTOP_BASE + 0x2C) 147 #define REG_DVI_DTOP_16_H (REG_DVI_DTOP_BASE + 0x2D) 148 #define REG_DVI_DTOP_17_L (REG_DVI_DTOP_BASE + 0x2E) 149 #define REG_DVI_DTOP_17_H (REG_DVI_DTOP_BASE + 0x2F) 150 #define REG_DVI_DTOP_18_L (REG_DVI_DTOP_BASE + 0x30) 151 #define REG_DVI_DTOP_18_H (REG_DVI_DTOP_BASE + 0x31) 152 #define REG_DVI_DTOP_19_L (REG_DVI_DTOP_BASE + 0x32) 153 #define REG_DVI_DTOP_19_H (REG_DVI_DTOP_BASE + 0x33) 154 #define REG_DVI_DTOP_1A_L (REG_DVI_DTOP_BASE + 0x34) 155 #define REG_DVI_DTOP_1A_H (REG_DVI_DTOP_BASE + 0x35) 156 #define REG_DVI_DTOP_1B_L (REG_DVI_DTOP_BASE + 0x36) 157 #define REG_DVI_DTOP_1B_H (REG_DVI_DTOP_BASE + 0x37) 158 #define REG_DVI_DTOP_1C_L (REG_DVI_DTOP_BASE + 0x38) 159 #define REG_DVI_DTOP_1C_H (REG_DVI_DTOP_BASE + 0x39) 160 #define REG_DVI_DTOP_1D_L (REG_DVI_DTOP_BASE + 0x3A) 161 #define REG_DVI_DTOP_1D_H (REG_DVI_DTOP_BASE + 0x3B) 162 #define REG_DVI_DTOP_1E_L (REG_DVI_DTOP_BASE + 0x3C) 163 #define REG_DVI_DTOP_1E_H (REG_DVI_DTOP_BASE + 0x3D) 164 #define REG_DVI_DTOP_1F_L (REG_DVI_DTOP_BASE + 0x3E) 165 #define REG_DVI_DTOP_1F_H (REG_DVI_DTOP_BASE + 0x3F) 166 #define REG_DVI_DTOP_20_L (REG_DVI_DTOP_BASE + 0x40) 167 #define REG_DVI_DTOP_20_H (REG_DVI_DTOP_BASE + 0x41) 168 #define REG_DVI_DTOP_21_L (REG_DVI_DTOP_BASE + 0x42) 169 #define REG_DVI_DTOP_21_H (REG_DVI_DTOP_BASE + 0x43) 170 #define REG_DVI_DTOP_22_L (REG_DVI_DTOP_BASE + 0x44) 171 #define REG_DVI_DTOP_22_H (REG_DVI_DTOP_BASE + 0x45) 172 #define REG_DVI_DTOP_23_L (REG_DVI_DTOP_BASE + 0x46) 173 #define REG_DVI_DTOP_23_H (REG_DVI_DTOP_BASE + 0x47) 174 #define REG_DVI_DTOP_24_L (REG_DVI_DTOP_BASE + 0x48) 175 #define REG_DVI_DTOP_24_H (REG_DVI_DTOP_BASE + 0x49) 176 #define REG_DVI_DTOP_25_L (REG_DVI_DTOP_BASE + 0x4A) 177 #define REG_DVI_DTOP_25_H (REG_DVI_DTOP_BASE + 0x4B) 178 #define REG_DVI_DTOP_26_L (REG_DVI_DTOP_BASE + 0x4C) 179 #define REG_DVI_DTOP_26_H (REG_DVI_DTOP_BASE + 0x4D) 180 #define REG_DVI_DTOP_27_L (REG_DVI_DTOP_BASE + 0x4E) 181 #define REG_DVI_DTOP_27_H (REG_DVI_DTOP_BASE + 0x4F) 182 #define REG_DVI_DTOP_28_L (REG_DVI_DTOP_BASE + 0x50) 183 #define REG_DVI_DTOP_28_H (REG_DVI_DTOP_BASE + 0x51) 184 #define REG_DVI_DTOP_29_L (REG_DVI_DTOP_BASE + 0x52) 185 #define REG_DVI_DTOP_29_H (REG_DVI_DTOP_BASE + 0x53) 186 #define REG_DVI_DTOP_2A_L (REG_DVI_DTOP_BASE + 0x54) 187 #define REG_DVI_DTOP_2A_H (REG_DVI_DTOP_BASE + 0x55) 188 #define REG_DVI_DTOP_2B_L (REG_DVI_DTOP_BASE + 0x56) 189 #define REG_DVI_DTOP_2B_H (REG_DVI_DTOP_BASE + 0x57) 190 #define REG_DVI_DTOP_2C_L (REG_DVI_DTOP_BASE + 0x58) 191 #define REG_DVI_DTOP_2C_H (REG_DVI_DTOP_BASE + 0x59) 192 #define REG_DVI_DTOP_2D_L (REG_DVI_DTOP_BASE + 0x5A) 193 #define REG_DVI_DTOP_2D_H (REG_DVI_DTOP_BASE + 0x5B) 194 #define REG_DVI_DTOP_2E_L (REG_DVI_DTOP_BASE + 0x5C) 195 #define REG_DVI_DTOP_2E_H (REG_DVI_DTOP_BASE + 0x5D) 196 #define REG_DVI_DTOP_2F_L (REG_DVI_DTOP_BASE + 0x5E) 197 #define REG_DVI_DTOP_2F_H (REG_DVI_DTOP_BASE + 0x5F) 198 #define REG_DVI_DTOP_30_L (REG_DVI_DTOP_BASE + 0x60) 199 #define REG_DVI_DTOP_30_H (REG_DVI_DTOP_BASE + 0x61) 200 #define REG_DVI_DTOP_31_L (REG_DVI_DTOP_BASE + 0x62) 201 #define REG_DVI_DTOP_31_H (REG_DVI_DTOP_BASE + 0x63) 202 #define REG_DVI_DTOP_32_L (REG_DVI_DTOP_BASE + 0x64) 203 #define REG_DVI_DTOP_32_H (REG_DVI_DTOP_BASE + 0x65) 204 #define REG_DVI_DTOP_33_L (REG_DVI_DTOP_BASE + 0x66) 205 #define REG_DVI_DTOP_33_H (REG_DVI_DTOP_BASE + 0x67) 206 #define REG_DVI_DTOP_34_L (REG_DVI_DTOP_BASE + 0x68) 207 #define REG_DVI_DTOP_34_H (REG_DVI_DTOP_BASE + 0x69) 208 #define REG_DVI_DTOP_35_L (REG_DVI_DTOP_BASE + 0x6A) 209 #define REG_DVI_DTOP_35_H (REG_DVI_DTOP_BASE + 0x6B) 210 #define REG_DVI_DTOP_36_L (REG_DVI_DTOP_BASE + 0x6C) 211 #define REG_DVI_DTOP_36_H (REG_DVI_DTOP_BASE + 0x6D) 212 #define REG_DVI_DTOP_37_L (REG_DVI_DTOP_BASE + 0x6E) 213 #define REG_DVI_DTOP_37_H (REG_DVI_DTOP_BASE + 0x6F) 214 #define REG_DVI_DTOP_38_L (REG_DVI_DTOP_BASE + 0x70) 215 #define REG_DVI_DTOP_38_H (REG_DVI_DTOP_BASE + 0x71) 216 #define REG_DVI_DTOP_39_L (REG_DVI_DTOP_BASE + 0x72) 217 #define REG_DVI_DTOP_39_H (REG_DVI_DTOP_BASE + 0x73) 218 #define REG_DVI_DTOP_3A_L (REG_DVI_DTOP_BASE + 0x74) 219 #define REG_DVI_DTOP_3A_H (REG_DVI_DTOP_BASE + 0x75) 220 #define REG_DVI_DTOP_3B_L (REG_DVI_DTOP_BASE + 0x76) 221 #define REG_DVI_DTOP_3B_H (REG_DVI_DTOP_BASE + 0x77) 222 #define REG_DVI_DTOP_3C_L (REG_DVI_DTOP_BASE + 0x78) 223 #define REG_DVI_DTOP_3C_H (REG_DVI_DTOP_BASE + 0x79) 224 #define REG_DVI_DTOP_3D_L (REG_DVI_DTOP_BASE + 0x7A) 225 #define REG_DVI_DTOP_3D_H (REG_DVI_DTOP_BASE + 0x7B) 226 #define REG_DVI_DTOP_3E_L (REG_DVI_DTOP_BASE + 0x7C) 227 #define REG_DVI_DTOP_3E_H (REG_DVI_DTOP_BASE + 0x7D) 228 #define REG_DVI_DTOP_3F_L (REG_DVI_DTOP_BASE + 0x7E) 229 #define REG_DVI_DTOP_3F_H (REG_DVI_DTOP_BASE + 0x7F) 230 231 // DVI DTOP1 232 #define REG_DVI_DTOP1_00_L (REG_DVI_DTOP1_BASE + 0x00) 233 #define REG_DVI_DTOP1_00_H (REG_DVI_DTOP1_BASE + 0x01) 234 #define REG_DVI_DTOP1_01_L (REG_DVI_DTOP1_BASE + 0x02) 235 #define REG_DVI_DTOP1_01_H (REG_DVI_DTOP1_BASE + 0x03) 236 #define REG_DVI_DTOP1_02_L (REG_DVI_DTOP1_BASE + 0x04) 237 #define REG_DVI_DTOP1_02_H (REG_DVI_DTOP1_BASE + 0x05) 238 #define REG_DVI_DTOP1_03_L (REG_DVI_DTOP1_BASE + 0x06) 239 #define REG_DVI_DTOP1_03_H (REG_DVI_DTOP1_BASE + 0x07) 240 #define REG_DVI_DTOP1_05_L (REG_DVI_DTOP1_BASE + 0x0A) 241 #define REG_DVI_DTOP1_05_H (REG_DVI_DTOP1_BASE + 0x0B) 242 #define REG_DVI_DTOP1_0B_L (REG_DVI_DTOP1_BASE + 0x16) 243 #define REG_DVI_DTOP1_0B_H (REG_DVI_DTOP1_BASE + 0x17) 244 #define REG_DVI_DTOP1_0E_L (REG_DVI_DTOP1_BASE + 0x1C) 245 #define REG_DVI_DTOP1_0E_H (REG_DVI_DTOP1_BASE + 0x1D) 246 #define REG_DVI_DTOP1_16_L (REG_DVI_DTOP1_BASE + 0x2C) 247 #define REG_DVI_DTOP1_16_H (REG_DVI_DTOP1_BASE + 0x2D) 248 #define REG_DVI_DTOP1_17_L (REG_DVI_DTOP1_BASE + 0x2E) 249 #define REG_DVI_DTOP1_17_H (REG_DVI_DTOP1_BASE + 0x2F) 250 #define REG_DVI_DTOP1_19_L (REG_DVI_DTOP1_BASE + 0x32) 251 #define REG_DVI_DTOP1_19_H (REG_DVI_DTOP1_BASE + 0x33) 252 #define REG_DVI_DTOP1_1E_L (REG_DVI_DTOP1_BASE + 0x3C) 253 #define REG_DVI_DTOP1_1E_H (REG_DVI_DTOP1_BASE + 0x3D) 254 #define REG_DVI_DTOP1_21_L (REG_DVI_DTOP1_BASE + 0x42) 255 #define REG_DVI_DTOP1_21_H (REG_DVI_DTOP1_BASE + 0x43) 256 #define REG_DVI_DTOP1_23_L (REG_DVI_DTOP1_BASE + 0x46) 257 #define REG_DVI_DTOP1_24_L (REG_DVI_DTOP1_BASE + 0x48) 258 #define REG_DVI_DTOP1_24_H (REG_DVI_DTOP1_BASE + 0x49) 259 #define REG_DVI_DTOP1_25_L (REG_DVI_DTOP1_BASE + 0x4A) 260 #define REG_DVI_DTOP1_25_H (REG_DVI_DTOP1_BASE + 0x4B) 261 #define REG_DVI_DTOP1_29_L (REG_DVI_DTOP1_BASE + 0x52) 262 #define REG_DVI_DTOP1_29_H (REG_DVI_DTOP1_BASE + 0x53) 263 #define REG_DVI_DTOP1_2A_L (REG_DVI_DTOP1_BASE + 0x54) 264 #define REG_DVI_DTOP1_2A_H (REG_DVI_DTOP1_BASE + 0x55) 265 #define REG_DVI_DTOP1_2F_L (REG_DVI_DTOP1_BASE + 0x5E) 266 #define REG_DVI_DTOP1_2F_H (REG_DVI_DTOP1_BASE + 0x5F) 267 #define REG_DVI_DTOP1_30_L (REG_DVI_DTOP1_BASE + 0x60) 268 #define REG_DVI_DTOP1_30_H (REG_DVI_DTOP1_BASE + 0x61) 269 #define REG_DVI_DTOP1_31_L (REG_DVI_DTOP1_BASE + 0x62) 270 #define REG_DVI_DTOP1_31_H (REG_DVI_DTOP1_BASE + 0x63) 271 272 // DVI DTOP2 273 #define REG_DVI_DTOP2_00_L (REG_DVI_DTOP2_BASE + 0x00) 274 #define REG_DVI_DTOP2_00_H (REG_DVI_DTOP2_BASE + 0x01) 275 #define REG_DVI_DTOP2_01_L (REG_DVI_DTOP2_BASE + 0x02) 276 #define REG_DVI_DTOP2_01_H (REG_DVI_DTOP2_BASE + 0x03) 277 #define REG_DVI_DTOP2_02_L (REG_DVI_DTOP2_BASE + 0x04) 278 #define REG_DVI_DTOP2_02_H (REG_DVI_DTOP2_BASE + 0x05) 279 #define REG_DVI_DTOP2_03_L (REG_DVI_DTOP2_BASE + 0x06) 280 #define REG_DVI_DTOP2_03_H (REG_DVI_DTOP2_BASE + 0x07) 281 #define REG_DVI_DTOP2_05_L (REG_DVI_DTOP2_BASE + 0x0A) 282 #define REG_DVI_DTOP2_05_H (REG_DVI_DTOP2_BASE + 0x0B) 283 #define REG_DVI_DTOP2_0B_L (REG_DVI_DTOP2_BASE + 0x16) 284 #define REG_DVI_DTOP2_0B_H (REG_DVI_DTOP2_BASE + 0x17) 285 #define REG_DVI_DTOP2_0E_L (REG_DVI_DTOP2_BASE + 0x1C) 286 #define REG_DVI_DTOP2_0E_H (REG_DVI_DTOP2_BASE + 0x1D) 287 #define REG_DVI_DTOP2_16_L (REG_DVI_DTOP2_BASE + 0x2C) 288 #define REG_DVI_DTOP2_16_H (REG_DVI_DTOP2_BASE + 0x2D) 289 #define REG_DVI_DTOP2_17_L (REG_DVI_DTOP2_BASE + 0x2E) 290 #define REG_DVI_DTOP2_17_H (REG_DVI_DTOP2_BASE + 0x2F) 291 #define REG_DVI_DTOP2_19_L (REG_DVI_DTOP2_BASE + 0x32) 292 #define REG_DVI_DTOP2_19_H (REG_DVI_DTOP2_BASE + 0x33) 293 #define REG_DVI_DTOP2_20_L (REG_DVI_DTOP2_BASE + 0x40) 294 #define REG_DVI_DTOP2_20_H (REG_DVI_DTOP2_BASE + 0x41) 295 #define REG_DVI_DTOP2_1E_L (REG_DVI_DTOP2_BASE + 0x3C) 296 #define REG_DVI_DTOP2_1E_H (REG_DVI_DTOP2_BASE + 0x3D) 297 #define REG_DVI_DTOP2_1F_L (REG_DVI_DTOP2_BASE + 0x3E) 298 #define REG_DVI_DTOP2_1F_H (REG_DVI_DTOP2_BASE + 0x3F) 299 #define REG_DVI_DTOP2_20_L (REG_DVI_DTOP2_BASE + 0x40) 300 #define REG_DVI_DTOP2_20_H (REG_DVI_DTOP2_BASE + 0x41) 301 #define REG_DVI_DTOP2_21_L (REG_DVI_DTOP2_BASE + 0x42) 302 #define REG_DVI_DTOP2_21_H (REG_DVI_DTOP2_BASE + 0x43) 303 #define REG_DVI_DTOP2_23_L (REG_DVI_DTOP2_BASE + 0x46) 304 #define REG_DVI_DTOP2_24_L (REG_DVI_DTOP2_BASE + 0x48) 305 #define REG_DVI_DTOP2_24_H (REG_DVI_DTOP2_BASE + 0x49) 306 #define REG_DVI_DTOP2_25_L (REG_DVI_DTOP2_BASE + 0x4A) 307 #define REG_DVI_DTOP2_25_H (REG_DVI_DTOP2_BASE + 0x4B) 308 #define REG_DVI_DTOP2_27_L (REG_DVI_DTOP2_BASE + 0x4E) 309 #define REG_DVI_DTOP2_27_H (REG_DVI_DTOP2_BASE + 0x4F) 310 #define REG_DVI_DTOP2_28_L (REG_DVI_DTOP2_BASE + 0x50) 311 #define REG_DVI_DTOP2_28_H (REG_DVI_DTOP2_BASE + 0x51) 312 #define REG_DVI_DTOP2_29_L (REG_DVI_DTOP2_BASE + 0x52) 313 #define REG_DVI_DTOP2_29_H (REG_DVI_DTOP2_BASE + 0x53) 314 #define REG_DVI_DTOP2_2A_L (REG_DVI_DTOP2_BASE + 0x54) 315 #define REG_DVI_DTOP2_2A_H (REG_DVI_DTOP2_BASE + 0x55) 316 #define REG_DVI_DTOP2_2E_L (REG_DVI_DTOP2_BASE + 0x5C) 317 #define REG_DVI_DTOP2_2E_H (REG_DVI_DTOP2_BASE + 0x5D) 318 #define REG_DVI_DTOP2_2F_L (REG_DVI_DTOP2_BASE + 0x5E) 319 #define REG_DVI_DTOP2_2F_H (REG_DVI_DTOP2_BASE + 0x5F) 320 #define REG_DVI_DTOP2_30_L (REG_DVI_DTOP2_BASE + 0x60) 321 #define REG_DVI_DTOP2_30_H (REG_DVI_DTOP2_BASE + 0x61) 322 #define REG_DVI_DTOP2_31_L (REG_DVI_DTOP2_BASE + 0x62) 323 #define REG_DVI_DTOP2_31_H (REG_DVI_DTOP2_BASE + 0x63) 324 #define REG_DVI_DTOP2_37_L (REG_DVI_DTOP2_BASE + 0x6E) 325 #define REG_DVI_DTOP2_3A_L (REG_DVI_DTOP2_BASE + 0x74) 326 #define REG_DVI_DTOP2_3A_H (REG_DVI_DTOP2_BASE + 0x75) 327 #define REG_DVI_DTOP2_3B_L (REG_DVI_DTOP2_BASE + 0x76) 328 #define REG_DVI_DTOP2_3B_H (REG_DVI_DTOP2_BASE + 0x77) 329 #define REG_DVI_DTOP2_3C_L (REG_DVI_DTOP2_BASE + 0x78) 330 #define REG_DVI_DTOP2_3C_H (REG_DVI_DTOP2_BASE + 0x79) 331 #define REG_DVI_DTOP2_3D_L (REG_DVI_DTOP2_BASE + 0x7A) 332 #define REG_DVI_DTOP2_3D_H (REG_DVI_DTOP2_BASE + 0x7B) 333 #define REG_DVI_DTOP2_3E_L (REG_DVI_DTOP2_BASE + 0x7C) 334 #define REG_DVI_DTOP2_3E_H (REG_DVI_DTOP2_BASE + 0x7D) 335 #define REG_DVI_DTOP2_3F_L (REG_DVI_DTOP2_BASE + 0x7E) 336 #define REG_DVI_DTOP2_3F_H (REG_DVI_DTOP2_BASE + 0x7F) 337 338 // DVI DTOP3 339 #define REG_DVI_DTOP3_00_L (REG_DVI_DTOP3_BASE + 0x00) 340 #define REG_DVI_DTOP3_00_H (REG_DVI_DTOP3_BASE + 0x01) 341 #define REG_DVI_DTOP3_01_L (REG_DVI_DTOP3_BASE + 0x02) 342 #define REG_DVI_DTOP3_01_H (REG_DVI_DTOP3_BASE + 0x03) 343 #define REG_DVI_DTOP3_02_L (REG_DVI_DTOP3_BASE + 0x04) 344 #define REG_DVI_DTOP3_02_H (REG_DVI_DTOP3_BASE + 0x05) 345 #define REG_DVI_DTOP3_03_L (REG_DVI_DTOP3_BASE + 0x06) 346 #define REG_DVI_DTOP3_03_H (REG_DVI_DTOP3_BASE + 0x07) 347 #define REG_DVI_DTOP3_04_L (REG_DVI_DTOP3_BASE + 0x08) 348 #define REG_DVI_DTOP3_04_H (REG_DVI_DTOP3_BASE + 0x09) 349 #define REG_DVI_DTOP3_05_L (REG_DVI_DTOP3_BASE + 0x0A) 350 #define REG_DVI_DTOP3_05_H (REG_DVI_DTOP3_BASE + 0x0B) 351 #define REG_DVI_DTOP3_0B_L (REG_DVI_DTOP3_BASE + 0x16) 352 #define REG_DVI_DTOP3_0B_H (REG_DVI_DTOP3_BASE + 0x17) 353 #define REG_DVI_DTOP3_0C_L (REG_DVI_DTOP3_BASE + 0x18) 354 #define REG_DVI_DTOP3_0C_H (REG_DVI_DTOP3_BASE + 0x19) 355 #define REG_DVI_DTOP3_0E_L (REG_DVI_DTOP3_BASE + 0x1C) 356 #define REG_DVI_DTOP3_0E_H (REG_DVI_DTOP3_BASE + 0x1D) 357 #define REG_DVI_DTOP3_16_L (REG_DVI_DTOP3_BASE + 0x2C) 358 #define REG_DVI_DTOP3_16_H (REG_DVI_DTOP3_BASE + 0x2D) 359 #define REG_DVI_DTOP3_17_L (REG_DVI_DTOP3_BASE + 0x2E) 360 #define REG_DVI_DTOP3_17_H (REG_DVI_DTOP3_BASE + 0x2F) 361 #define REG_DVI_DTOP3_19_L (REG_DVI_DTOP3_BASE + 0x32) 362 #define REG_DVI_DTOP3_19_H (REG_DVI_DTOP3_BASE + 0x33) 363 #define REG_DVI_DTOP3_1E_L (REG_DVI_DTOP3_BASE + 0x3C) 364 #define REG_DVI_DTOP3_1E_H (REG_DVI_DTOP3_BASE + 0x3D) 365 #define REG_DVI_DTOP3_1F_L (REG_DVI_DTOP3_BASE + 0x3E) 366 #define REG_DVI_DTOP3_1F_H (REG_DVI_DTOP3_BASE + 0x3F) 367 #define REG_DVI_DTOP3_20_L (REG_DVI_DTOP3_BASE + 0x40) 368 #define REG_DVI_DTOP3_21_L (REG_DVI_DTOP3_BASE + 0x42) 369 #define REG_DVI_DTOP3_21_H (REG_DVI_DTOP3_BASE + 0x43) 370 #define REG_DVI_DTOP3_23_L (REG_DVI_DTOP3_BASE + 0x46) 371 #define REG_DVI_DTOP3_23_H (REG_DVI_DTOP3_BASE + 0x47) 372 #define REG_DVI_DTOP3_24_L (REG_DVI_DTOP3_BASE + 0x48) 373 #define REG_DVI_DTOP3_24_H (REG_DVI_DTOP3_BASE + 0x49) 374 #define REG_DVI_DTOP3_25_L (REG_DVI_DTOP3_BASE + 0x4A) 375 #define REG_DVI_DTOP3_25_H (REG_DVI_DTOP3_BASE + 0x4B) 376 #define REG_DVI_DTOP3_27_L (REG_DVI_DTOP3_BASE + 0x4E) 377 #define REG_DVI_DTOP3_27_H (REG_DVI_DTOP3_BASE + 0x4F) 378 #define REG_DVI_DTOP3_28_L (REG_DVI_DTOP3_BASE + 0x50) 379 #define REG_DVI_DTOP3_28_H (REG_DVI_DTOP3_BASE + 0x51) 380 #define REG_DVI_DTOP3_29_L (REG_DVI_DTOP3_BASE + 0x52) 381 #define REG_DVI_DTOP3_29_H (REG_DVI_DTOP3_BASE + 0x53) 382 #define REG_DVI_DTOP3_2A_L (REG_DVI_DTOP3_BASE + 0x54) 383 #define REG_DVI_DTOP3_2A_H (REG_DVI_DTOP3_BASE + 0x55) 384 #define REG_DVI_DTOP3_2E_L (REG_DVI_DTOP3_BASE + 0x5C) 385 #define REG_DVI_DTOP3_2E_H (REG_DVI_DTOP3_BASE + 0x5D) 386 #define REG_DVI_DTOP3_2F_L (REG_DVI_DTOP3_BASE + 0x5E) 387 #define REG_DVI_DTOP3_2F_H (REG_DVI_DTOP3_BASE + 0x5F) 388 #define REG_DVI_DTOP3_30_L (REG_DVI_DTOP3_BASE + 0x60) 389 #define REG_DVI_DTOP3_30_H (REG_DVI_DTOP3_BASE + 0x61) 390 #define REG_DVI_DTOP3_31_L (REG_DVI_DTOP3_BASE + 0x62) 391 #define REG_DVI_DTOP3_31_H (REG_DVI_DTOP3_BASE + 0x63) 392 #define REG_DVI_DTOP3_37_L (REG_DVI_DTOP3_BASE + 0x6E) 393 #define REG_DVI_DTOP3_37_H (REG_DVI_DTOP3_BASE + 0x6F) 394 #define REG_DVI_DTOP3_3A_L (REG_DVI_DTOP3_BASE + 0x74) 395 #define REG_DVI_DTOP3_3B_L (REG_DVI_DTOP3_BASE + 0x76) 396 #define REG_DVI_DTOP3_3C_L (REG_DVI_DTOP3_BASE + 0x78) 397 #define REG_DVI_DTOP3_3D_L (REG_DVI_DTOP3_BASE + 0x7A) 398 #define REG_DVI_DTOP3_3E_L (REG_DVI_DTOP3_BASE + 0x7C) 399 #define REG_DVI_DTOP3_3E_H (REG_DVI_DTOP3_BASE + 0x7D) 400 #define REG_DVI_DTOP3_3F_L (REG_DVI_DTOP3_BASE + 0x7E) 401 402 403 //============================================================= 404 // DVI EQ 405 406 #define REG_DVI_EQ_00_L (REG_DVI_EQ_BASE + 0x00) 407 #define REG_DVI_EQ_00_H (REG_DVI_EQ_BASE + 0x01) 408 #define REG_DVI_EQ_01_L (REG_DVI_EQ_BASE + 0x02) 409 #define REG_DVI_EQ_01_H (REG_DVI_EQ_BASE + 0x03) 410 #define REG_DVI_EQ_02_L (REG_DVI_EQ_BASE + 0x04) 411 #define REG_DVI_EQ_02_H (REG_DVI_EQ_BASE + 0x05) 412 #define REG_DVI_EQ_03_L (REG_DVI_EQ_BASE + 0x06) 413 #define REG_DVI_EQ_03_H (REG_DVI_EQ_BASE + 0x07) 414 #define REG_DVI_EQ_04_L (REG_DVI_EQ_BASE + 0x08) 415 #define REG_DVI_EQ_04_H (REG_DVI_EQ_BASE + 0x09) 416 #define REG_DVI_EQ_05_L (REG_DVI_EQ_BASE + 0x0A) 417 #define REG_DVI_EQ_05_H (REG_DVI_EQ_BASE + 0x0B) 418 #define REG_DVI_EQ_06_L (REG_DVI_EQ_BASE + 0x0C) 419 #define REG_DVI_EQ_06_H (REG_DVI_EQ_BASE + 0x0D) 420 #define REG_DVI_EQ_07_L (REG_DVI_EQ_BASE + 0x0E) 421 #define REG_DVI_EQ_07_H (REG_DVI_EQ_BASE + 0x0F) 422 #define REG_DVI_EQ_08_L (REG_DVI_EQ_BASE + 0x10) 423 #define REG_DVI_EQ_08_H (REG_DVI_EQ_BASE + 0x11) 424 #define REG_DVI_EQ_09_L (REG_DVI_EQ_BASE + 0x12) 425 #define REG_DVI_EQ_09_H (REG_DVI_EQ_BASE + 0x13) 426 #define REG_DVI_EQ_0A_L (REG_DVI_EQ_BASE + 0x14) 427 #define REG_DVI_EQ_0A_H (REG_DVI_EQ_BASE + 0x15) 428 #define REG_DVI_EQ_0B_L (REG_DVI_EQ_BASE + 0x16) 429 #define REG_DVI_EQ_0B_H (REG_DVI_EQ_BASE + 0x17) 430 #define REG_DVI_EQ_0C_L (REG_DVI_EQ_BASE + 0x18) 431 #define REG_DVI_EQ_0C_H (REG_DVI_EQ_BASE + 0x19) 432 #define REG_DVI_EQ_0D_L (REG_DVI_EQ_BASE + 0x1A) 433 #define REG_DVI_EQ_0D_H (REG_DVI_EQ_BASE + 0x1B) 434 #define REG_DVI_EQ_0E_L (REG_DVI_EQ_BASE + 0x1C) 435 #define REG_DVI_EQ_0E_H (REG_DVI_EQ_BASE + 0x1D) 436 #define REG_DVI_EQ_0F_L (REG_DVI_EQ_BASE + 0x1E) 437 #define REG_DVI_EQ_0F_H (REG_DVI_EQ_BASE + 0x1F) 438 #define REG_DVI_EQ_10_L (REG_DVI_EQ_BASE + 0x20) 439 #define REG_DVI_EQ_10_H (REG_DVI_EQ_BASE + 0x21) 440 #define REG_DVI_EQ_11_L (REG_DVI_EQ_BASE + 0x22) 441 #define REG_DVI_EQ_11_H (REG_DVI_EQ_BASE + 0x23) 442 #define REG_DVI_EQ_12_L (REG_DVI_EQ_BASE + 0x24) 443 #define REG_DVI_EQ_12_H (REG_DVI_EQ_BASE + 0x25) 444 #define REG_DVI_EQ_13_L (REG_DVI_EQ_BASE + 0x26) 445 #define REG_DVI_EQ_13_H (REG_DVI_EQ_BASE + 0x27) 446 #define REG_DVI_EQ_14_L (REG_DVI_EQ_BASE + 0x28) 447 #define REG_DVI_EQ_14_H (REG_DVI_EQ_BASE + 0x29) 448 #define REG_DVI_EQ_15_L (REG_DVI_EQ_BASE + 0x2A) 449 #define REG_DVI_EQ_15_H (REG_DVI_EQ_BASE + 0x2B) 450 #define REG_DVI_EQ_16_L (REG_DVI_EQ_BASE + 0x2C) 451 #define REG_DVI_EQ_16_H (REG_DVI_EQ_BASE + 0x2D) 452 #define REG_DVI_EQ_17_L (REG_DVI_EQ_BASE + 0x2E) 453 #define REG_DVI_EQ_17_H (REG_DVI_EQ_BASE + 0x2F) 454 #define REG_DVI_EQ_18_L (REG_DVI_EQ_BASE + 0x30) 455 #define REG_DVI_EQ_18_H (REG_DVI_EQ_BASE + 0x31) 456 #define REG_DVI_EQ_19_L (REG_DVI_EQ_BASE + 0x32) 457 #define REG_DVI_EQ_19_H (REG_DVI_EQ_BASE + 0x33) 458 #define REG_DVI_EQ_1A_L (REG_DVI_EQ_BASE + 0x34) 459 #define REG_DVI_EQ_1A_H (REG_DVI_EQ_BASE + 0x35) 460 #define REG_DVI_EQ_1B_L (REG_DVI_EQ_BASE + 0x36) 461 #define REG_DVI_EQ_1B_H (REG_DVI_EQ_BASE + 0x37) 462 #define REG_DVI_EQ_1C_L (REG_DVI_EQ_BASE + 0x38) 463 #define REG_DVI_EQ_1C_H (REG_DVI_EQ_BASE + 0x39) 464 #define REG_DVI_EQ_1D_L (REG_DVI_EQ_BASE + 0x3A) 465 #define REG_DVI_EQ_1D_H (REG_DVI_EQ_BASE + 0x3B) 466 #define REG_DVI_EQ_1E_L (REG_DVI_EQ_BASE + 0x3C) 467 #define REG_DVI_EQ_1E_H (REG_DVI_EQ_BASE + 0x3D) 468 #define REG_DVI_EQ_1F_L (REG_DVI_EQ_BASE + 0x3E) 469 470 // DVI EQ1 471 #define REG_DVI_EQ1_00_L (REG_DVI_EQ1_BASE + 0x00) 472 #define REG_DVI_EQ1_00_H (REG_DVI_EQ1_BASE + 0x01) 473 #define REG_DVI_EQ1_01_L (REG_DVI_EQ1_BASE + 0x02) 474 #define REG_DVI_EQ1_01_H (REG_DVI_EQ1_BASE + 0x03) 475 #define REG_DVI_EQ1_02_L (REG_DVI_EQ1_BASE + 0x04) 476 #define REG_DVI_EQ1_02_H (REG_DVI_EQ1_BASE + 0x05) 477 #define REG_DVI_EQ1_04_L (REG_DVI_EQ1_BASE + 0x08) 478 #define REG_DVI_EQ1_04_H (REG_DVI_EQ1_BASE + 0x09) 479 #define REG_DVI_EQ1_10_L (REG_DVI_EQ1_BASE + 0x20) 480 #define REG_DVI_EQ1_10_H (REG_DVI_EQ1_BASE + 0x21) 481 #define REG_DVI_EQ1_11_L (REG_DVI_EQ1_BASE + 0x22) 482 #define REG_DVI_EQ1_11_H (REG_DVI_EQ1_BASE + 0x23) 483 #define REG_DVI_EQ1_12_L (REG_DVI_EQ1_BASE + 0x24) 484 #define REG_DVI_EQ1_12_H (REG_DVI_EQ1_BASE + 0x25) 485 #define REG_DVI_EQ1_17_L (REG_DVI_EQ1_BASE + 0x2E) 486 #define REG_DVI_EQ1_17_H (REG_DVI_EQ1_BASE + 0x2F) 487 488 // DVI EQ2 489 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00) 490 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01) 491 #define REG_DVI_EQ2_01_L (REG_DVI_EQ2_BASE + 0x02) 492 #define REG_DVI_EQ2_01_H (REG_DVI_EQ2_BASE + 0x03) 493 #define REG_DVI_EQ2_02_L (REG_DVI_EQ2_BASE + 0x04) 494 #define REG_DVI_EQ2_02_H (REG_DVI_EQ2_BASE + 0x05) 495 #define REG_DVI_EQ2_04_L (REG_DVI_EQ2_BASE + 0x08) 496 #define REG_DVI_EQ2_04_H (REG_DVI_EQ2_BASE + 0x09) 497 #define REG_DVI_EQ2_10_L (REG_DVI_EQ2_BASE + 0x20) 498 #define REG_DVI_EQ2_10_H (REG_DVI_EQ2_BASE + 0x21) 499 #define REG_DVI_EQ2_11_L (REG_DVI_EQ2_BASE + 0x22) 500 #define REG_DVI_EQ2_11_H (REG_DVI_EQ2_BASE + 0x23) 501 #define REG_DVI_EQ2_12_L (REG_DVI_EQ2_BASE + 0x24) 502 #define REG_DVI_EQ2_12_H (REG_DVI_EQ2_BASE + 0x25) 503 #define REG_DVI_EQ2_17_L (REG_DVI_EQ2_BASE + 0x2E) 504 #define REG_DVI_EQ2_17_H (REG_DVI_EQ2_BASE + 0x2F) 505 506 // DVI EQ3 507 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00) 508 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01) 509 #define REG_DVI_EQ3_01_L (REG_DVI_EQ3_BASE + 0x02) 510 #define REG_DVI_EQ3_01_H (REG_DVI_EQ3_BASE + 0x03) 511 #define REG_DVI_EQ3_02_L (REG_DVI_EQ3_BASE + 0x04) 512 #define REG_DVI_EQ3_02_H (REG_DVI_EQ3_BASE + 0x05) 513 #define REG_DVI_EQ3_04_L (REG_DVI_EQ3_BASE + 0x08) 514 #define REG_DVI_EQ3_04_H (REG_DVI_EQ3_BASE + 0x09) 515 #define REG_DVI_EQ3_10_L (REG_DVI_EQ3_BASE + 0x20) 516 #define REG_DVI_EQ3_10_H (REG_DVI_EQ3_BASE + 0x21) 517 #define REG_DVI_EQ3_11_L (REG_DVI_EQ3_BASE + 0x22) 518 #define REG_DVI_EQ3_11_H (REG_DVI_EQ3_BASE + 0x23) 519 #define REG_DVI_EQ3_12_L (REG_DVI_EQ3_BASE + 0x24) 520 #define REG_DVI_EQ3_12_H (REG_DVI_EQ3_BASE + 0x25) 521 #define REG_DVI_EQ3_17_L (REG_DVI_EQ3_BASE + 0x2E) 522 #define REG_DVI_EQ3_17_H (REG_DVI_EQ3_BASE + 0x2F) 523 524 //============================================================= 525 // DVI ATOP 526 527 #define REG_DVI_ATOP_00_L (REG_DVI_ATOP_BASE + 0x00) 528 #define REG_DVI_ATOP_00_H (REG_DVI_ATOP_BASE + 0x01) 529 #define REG_DVI_ATOP_01_L (REG_DVI_ATOP_BASE + 0x02) 530 #define REG_DVI_ATOP_01_H (REG_DVI_ATOP_BASE + 0x03) 531 #define REG_DVI_ATOP_02_L (REG_DVI_ATOP_BASE + 0x04) 532 #define REG_DVI_ATOP_02_H (REG_DVI_ATOP_BASE + 0x05) 533 #define REG_DVI_ATOP_03_L (REG_DVI_ATOP_BASE + 0x06) 534 #define REG_DVI_ATOP_03_H (REG_DVI_ATOP_BASE + 0x07) 535 #define REG_DVI_ATOP_04_L (REG_DVI_ATOP_BASE + 0x08) 536 #define REG_DVI_ATOP_04_H (REG_DVI_ATOP_BASE + 0x09) 537 #define REG_DVI_ATOP_05_L (REG_DVI_ATOP_BASE + 0x0A) 538 #define REG_DVI_ATOP_05_H (REG_DVI_ATOP_BASE + 0x0B) 539 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) 540 #define REG_DVI_ATOP_06_H (REG_DVI_ATOP_BASE + 0x0D) 541 #define REG_DVI_ATOP_07_L (REG_DVI_ATOP_BASE + 0x0E) 542 #define REG_DVI_ATOP_07_H (REG_DVI_ATOP_BASE + 0x0F) 543 #define REG_DVI_ATOP_08_L (REG_DVI_ATOP_BASE + 0x10) 544 #define REG_DVI_ATOP_08_H (REG_DVI_ATOP_BASE + 0x11) 545 #define REG_DVI_ATOP_09_L (REG_DVI_ATOP_BASE + 0x12) 546 #define REG_DVI_ATOP_09_H (REG_DVI_ATOP_BASE + 0x13) 547 #define REG_DVI_ATOP_0A_L (REG_DVI_ATOP_BASE + 0x14) 548 #define REG_DVI_ATOP_0A_H (REG_DVI_ATOP_BASE + 0x15) 549 #define REG_DVI_ATOP_0B_L (REG_DVI_ATOP_BASE + 0x16) 550 #define REG_DVI_ATOP_0B_H (REG_DVI_ATOP_BASE + 0x17) 551 #define REG_DVI_ATOP_0C_L (REG_DVI_ATOP_BASE + 0x18) 552 #define REG_DVI_ATOP_0C_H (REG_DVI_ATOP_BASE + 0x19) 553 #define REG_DVI_ATOP_0D_L (REG_DVI_ATOP_BASE + 0x1A) 554 #define REG_DVI_ATOP_0D_H (REG_DVI_ATOP_BASE + 0x1B) 555 #define REG_DVI_ATOP_0E_L (REG_DVI_ATOP_BASE + 0x1C) 556 #define REG_DVI_ATOP_0E_H (REG_DVI_ATOP_BASE + 0x1D) 557 #define REG_DVI_ATOP_0F_L (REG_DVI_ATOP_BASE + 0x1E) 558 #define REG_DVI_ATOP_0F_H (REG_DVI_ATOP_BASE + 0x1F) 559 #define REG_DVI_ATOP_10_L (REG_DVI_ATOP_BASE + 0x20) 560 #define REG_DVI_ATOP_10_H (REG_DVI_ATOP_BASE + 0x21) 561 #define REG_DVI_ATOP_11_L (REG_DVI_ATOP_BASE + 0x22) 562 #define REG_DVI_ATOP_11_H (REG_DVI_ATOP_BASE + 0x23) 563 #define REG_DVI_ATOP_12_L (REG_DVI_ATOP_BASE + 0x24) 564 #define REG_DVI_ATOP_12_H (REG_DVI_ATOP_BASE + 0x25) 565 #define REG_DVI_ATOP_13_L (REG_DVI_ATOP_BASE + 0x26) 566 #define REG_DVI_ATOP_13_H (REG_DVI_ATOP_BASE + 0x27) 567 #define REG_DVI_ATOP_14_L (REG_DVI_ATOP_BASE + 0x28) 568 #define REG_DVI_ATOP_14_H (REG_DVI_ATOP_BASE + 0x29) 569 #define REG_DVI_ATOP_15_L (REG_DVI_ATOP_BASE + 0x2A) 570 #define REG_DVI_ATOP_15_H (REG_DVI_ATOP_BASE + 0x2B) 571 #define REG_DVI_ATOP_16_L (REG_DVI_ATOP_BASE + 0x2C) 572 #define REG_DVI_ATOP_16_H (REG_DVI_ATOP_BASE + 0x2D) 573 #define REG_DVI_ATOP_17_L (REG_DVI_ATOP_BASE + 0x2E) 574 #define REG_DVI_ATOP_17_H (REG_DVI_ATOP_BASE + 0x2F) 575 #define REG_DVI_ATOP_18_L (REG_DVI_ATOP_BASE + 0x30) 576 #define REG_DVI_ATOP_18_H (REG_DVI_ATOP_BASE + 0x31) 577 #define REG_DVI_ATOP_19_L (REG_DVI_ATOP_BASE + 0x32) 578 #define REG_DVI_ATOP_19_H (REG_DVI_ATOP_BASE + 0x33) 579 #define REG_DVI_ATOP_1A_L (REG_DVI_ATOP_BASE + 0x34) 580 #define REG_DVI_ATOP_1A_H (REG_DVI_ATOP_BASE + 0x35) 581 #define REG_DVI_ATOP_1B_L (REG_DVI_ATOP_BASE + 0x36) 582 #define REG_DVI_ATOP_1B_H (REG_DVI_ATOP_BASE + 0x37) 583 #define REG_DVI_ATOP_1C_L (REG_DVI_ATOP_BASE + 0x38) 584 #define REG_DVI_ATOP_1C_H (REG_DVI_ATOP_BASE + 0x39) 585 #define REG_DVI_ATOP_1D_L (REG_DVI_ATOP_BASE + 0x3A) 586 #define REG_DVI_ATOP_1D_H (REG_DVI_ATOP_BASE + 0x3B) 587 #define REG_DVI_ATOP_1E_L (REG_DVI_ATOP_BASE + 0x3C) 588 #define REG_DVI_ATOP_1E_H (REG_DVI_ATOP_BASE + 0x3D) 589 #define REG_DVI_ATOP_1F_L (REG_DVI_ATOP_BASE + 0x3E) 590 #define REG_DVI_ATOP_1F_H (REG_DVI_ATOP_BASE + 0x3F) 591 #define REG_DVI_ATOP_20_L (REG_DVI_ATOP_BASE + 0x40) 592 #define REG_DVI_ATOP_20_H (REG_DVI_ATOP_BASE + 0x41) 593 #define REG_DVI_ATOP_21_L (REG_DVI_ATOP_BASE + 0x42) 594 #define REG_DVI_ATOP_21_H (REG_DVI_ATOP_BASE + 0x43) 595 #define REG_DVI_ATOP_22_L (REG_DVI_ATOP_BASE + 0x44) 596 #define REG_DVI_ATOP_22_H (REG_DVI_ATOP_BASE + 0x45) 597 #define REG_DVI_ATOP_23_L (REG_DVI_ATOP_BASE + 0x46) 598 #define REG_DVI_ATOP_23_H (REG_DVI_ATOP_BASE + 0x47) 599 #define REG_DVI_ATOP_24_L (REG_DVI_ATOP_BASE + 0x48) 600 #define REG_DVI_ATOP_24_H (REG_DVI_ATOP_BASE + 0x49) 601 #define REG_DVI_ATOP_25_L (REG_DVI_ATOP_BASE + 0x4A) 602 #define REG_DVI_ATOP_25_H (REG_DVI_ATOP_BASE + 0x4B) 603 #define REG_DVI_ATOP_26_L (REG_DVI_ATOP_BASE + 0x4C) 604 #define REG_DVI_ATOP_26_H (REG_DVI_ATOP_BASE + 0x4D) 605 #define REG_DVI_ATOP_27_L (REG_DVI_ATOP_BASE + 0x4E) 606 #define REG_DVI_ATOP_27_H (REG_DVI_ATOP_BASE + 0x4F) 607 #define REG_DVI_ATOP_28_L (REG_DVI_ATOP_BASE + 0x50) 608 #define REG_DVI_ATOP_28_H (REG_DVI_ATOP_BASE + 0x51) 609 #define REG_DVI_ATOP_29_L (REG_DVI_ATOP_BASE + 0x52) 610 #define REG_DVI_ATOP_29_H (REG_DVI_ATOP_BASE + 0x53) 611 #define REG_DVI_ATOP_2A_L (REG_DVI_ATOP_BASE + 0x54) 612 #define REG_DVI_ATOP_2A_H (REG_DVI_ATOP_BASE + 0x55) 613 #define REG_DVI_ATOP_2B_L (REG_DVI_ATOP_BASE + 0x56) 614 #define REG_DVI_ATOP_2B_H (REG_DVI_ATOP_BASE + 0x57) 615 #define REG_DVI_ATOP_2C_L (REG_DVI_ATOP_BASE + 0x58) 616 #define REG_DVI_ATOP_2C_H (REG_DVI_ATOP_BASE + 0x59) 617 #define REG_DVI_ATOP_2D_L (REG_DVI_ATOP_BASE + 0x5A) 618 #define REG_DVI_ATOP_2D_H (REG_DVI_ATOP_BASE + 0x5B) 619 #define REG_DVI_ATOP_2E_L (REG_DVI_ATOP_BASE + 0x5C) 620 #define REG_DVI_ATOP_2E_H (REG_DVI_ATOP_BASE + 0x5D) 621 #define REG_DVI_ATOP_2F_L (REG_DVI_ATOP_BASE + 0x5E) 622 #define REG_DVI_ATOP_2F_H (REG_DVI_ATOP_BASE + 0x5F) 623 #define REG_DVI_ATOP_30_L (REG_DVI_ATOP_BASE + 0x60) 624 #define REG_DVI_ATOP_30_H (REG_DVI_ATOP_BASE + 0x61) 625 #define REG_DVI_ATOP_31_L (REG_DVI_ATOP_BASE + 0x62) 626 #define REG_DVI_ATOP_31_H (REG_DVI_ATOP_BASE + 0x63) 627 #define REG_DVI_ATOP_32_L (REG_DVI_ATOP_BASE + 0x64) 628 #define REG_DVI_ATOP_32_H (REG_DVI_ATOP_BASE + 0x65) 629 #define REG_DVI_ATOP_33_L (REG_DVI_ATOP_BASE + 0x66) 630 #define REG_DVI_ATOP_33_H (REG_DVI_ATOP_BASE + 0x67) 631 #define REG_DVI_ATOP_34_L (REG_DVI_ATOP_BASE + 0x68) 632 #define REG_DVI_ATOP_34_H (REG_DVI_ATOP_BASE + 0x69) 633 #define REG_DVI_ATOP_35_L (REG_DVI_ATOP_BASE + 0x6A) 634 #define REG_DVI_ATOP_35_H (REG_DVI_ATOP_BASE + 0x6B) 635 #define REG_DVI_ATOP_36_L (REG_DVI_ATOP_BASE + 0x6C) 636 #define REG_DVI_ATOP_36_H (REG_DVI_ATOP_BASE + 0x6D) 637 #define REG_DVI_ATOP_37_L (REG_DVI_ATOP_BASE + 0x6E) 638 #define REG_DVI_ATOP_37_H (REG_DVI_ATOP_BASE + 0x6F) 639 #define REG_DVI_ATOP_38_L (REG_DVI_ATOP_BASE + 0x70) 640 #define REG_DVI_ATOP_38_H (REG_DVI_ATOP_BASE + 0x71) 641 #define REG_DVI_ATOP_39_L (REG_DVI_ATOP_BASE + 0x72) 642 #define REG_DVI_ATOP_39_H (REG_DVI_ATOP_BASE + 0x73) 643 #define REG_DVI_ATOP_3A_L (REG_DVI_ATOP_BASE + 0x74) 644 #define REG_DVI_ATOP_3A_H (REG_DVI_ATOP_BASE + 0x75) 645 #define REG_DVI_ATOP_3B_L (REG_DVI_ATOP_BASE + 0x76) 646 #define REG_DVI_ATOP_3B_H (REG_DVI_ATOP_BASE + 0x77) 647 #define REG_DVI_ATOP_3C_L (REG_DVI_ATOP_BASE + 0x78) 648 #define REG_DVI_ATOP_3C_H (REG_DVI_ATOP_BASE + 0x79) 649 #define REG_DVI_ATOP_3D_L (REG_DVI_ATOP_BASE + 0x7A) 650 #define REG_DVI_ATOP_3D_H (REG_DVI_ATOP_BASE + 0x7B) 651 #define REG_DVI_ATOP_3E_L (REG_DVI_ATOP_BASE + 0x7C) 652 #define REG_DVI_ATOP_3E_H (REG_DVI_ATOP_BASE + 0x7D) 653 #define REG_DVI_ATOP_3F_L (REG_DVI_ATOP_BASE + 0x7E) 654 #define REG_DVI_ATOP_3F_H (REG_DVI_ATOP_BASE + 0x7F) 655 #define REG_DVI_ATOP_40_L (REG_DVI_ATOP_BASE + 0x80) 656 #define REG_DVI_ATOP_40_H (REG_DVI_ATOP_BASE + 0x81) 657 #define REG_DVI_ATOP_41_L (REG_DVI_ATOP_BASE + 0x82) 658 #define REG_DVI_ATOP_41_H (REG_DVI_ATOP_BASE + 0x83) 659 #define REG_DVI_ATOP_42_L (REG_DVI_ATOP_BASE + 0x84) 660 #define REG_DVI_ATOP_42_H (REG_DVI_ATOP_BASE + 0x85) 661 #define REG_DVI_ATOP_43_L (REG_DVI_ATOP_BASE + 0x86) 662 #define REG_DVI_ATOP_43_H (REG_DVI_ATOP_BASE + 0x87) 663 #define REG_DVI_ATOP_44_L (REG_DVI_ATOP_BASE + 0x88) 664 #define REG_DVI_ATOP_44_H (REG_DVI_ATOP_BASE + 0x89) 665 #define REG_DVI_ATOP_45_L (REG_DVI_ATOP_BASE + 0x8A) 666 #define REG_DVI_ATOP_45_H (REG_DVI_ATOP_BASE + 0x8B) 667 #define REG_DVI_ATOP_46_L (REG_DVI_ATOP_BASE + 0x8C) 668 #define REG_DVI_ATOP_46_H (REG_DVI_ATOP_BASE + 0x8D) 669 #define REG_DVI_ATOP_47_L (REG_DVI_ATOP_BASE + 0x8E) 670 #define REG_DVI_ATOP_47_H (REG_DVI_ATOP_BASE + 0x8F) 671 #define REG_DVI_ATOP_48_L (REG_DVI_ATOP_BASE + 0x90) 672 #define REG_DVI_ATOP_48_H (REG_DVI_ATOP_BASE + 0x91) 673 #define REG_DVI_ATOP_49_L (REG_DVI_ATOP_BASE + 0x92) 674 #define REG_DVI_ATOP_49_H (REG_DVI_ATOP_BASE + 0x93) 675 #define REG_DVI_ATOP_4A_L (REG_DVI_ATOP_BASE + 0x94) 676 #define REG_DVI_ATOP_4A_H (REG_DVI_ATOP_BASE + 0x95) 677 #define REG_DVI_ATOP_4B_L (REG_DVI_ATOP_BASE + 0x96) 678 #define REG_DVI_ATOP_4B_H (REG_DVI_ATOP_BASE + 0x97) 679 #define REG_DVI_ATOP_4C_L (REG_DVI_ATOP_BASE + 0x98) 680 #define REG_DVI_ATOP_4C_H (REG_DVI_ATOP_BASE + 0x99) 681 #define REG_DVI_ATOP_4D_L (REG_DVI_ATOP_BASE + 0x9A) 682 #define REG_DVI_ATOP_4D_H (REG_DVI_ATOP_BASE + 0x9B) 683 #define REG_DVI_ATOP_4E_L (REG_DVI_ATOP_BASE + 0x9C) 684 #define REG_DVI_ATOP_4E_H (REG_DVI_ATOP_BASE + 0x9D) 685 #define REG_DVI_ATOP_4F_L (REG_DVI_ATOP_BASE + 0x9E) 686 #define REG_DVI_ATOP_4F_H (REG_DVI_ATOP_BASE + 0x9F) 687 #define REG_DVI_ATOP_50_L (REG_DVI_ATOP_BASE + 0xA0) 688 #define REG_DVI_ATOP_50_H (REG_DVI_ATOP_BASE + 0xA1) 689 #define REG_DVI_ATOP_51_L (REG_DVI_ATOP_BASE + 0xA2) 690 #define REG_DVI_ATOP_51_H (REG_DVI_ATOP_BASE + 0xA3) 691 #define REG_DVI_ATOP_52_L (REG_DVI_ATOP_BASE + 0xA4) 692 #define REG_DVI_ATOP_52_H (REG_DVI_ATOP_BASE + 0xA5) 693 #define REG_DVI_ATOP_53_L (REG_DVI_ATOP_BASE + 0xA6) 694 #define REG_DVI_ATOP_53_H (REG_DVI_ATOP_BASE + 0xA7) 695 #define REG_DVI_ATOP_54_L (REG_DVI_ATOP_BASE + 0xA8) 696 #define REG_DVI_ATOP_54_H (REG_DVI_ATOP_BASE + 0xA9) 697 #define REG_DVI_ATOP_55_L (REG_DVI_ATOP_BASE + 0xAA) 698 #define REG_DVI_ATOP_55_H (REG_DVI_ATOP_BASE + 0xAB) 699 #define REG_DVI_ATOP_56_L (REG_DVI_ATOP_BASE + 0xAC) 700 #define REG_DVI_ATOP_56_H (REG_DVI_ATOP_BASE + 0xAD) 701 #define REG_DVI_ATOP_57_L (REG_DVI_ATOP_BASE + 0xAE) 702 #define REG_DVI_ATOP_57_H (REG_DVI_ATOP_BASE + 0xAF) 703 #define REG_DVI_ATOP_58_L (REG_DVI_ATOP_BASE + 0xB0) 704 #define REG_DVI_ATOP_58_H (REG_DVI_ATOP_BASE + 0xB1) 705 #define REG_DVI_ATOP_59_L (REG_DVI_ATOP_BASE + 0xB2) 706 #define REG_DVI_ATOP_59_H (REG_DVI_ATOP_BASE + 0xB3) 707 #define REG_DVI_ATOP_5A_L (REG_DVI_ATOP_BASE + 0xB4) 708 #define REG_DVI_ATOP_5A_H (REG_DVI_ATOP_BASE + 0xB5) 709 #define REG_DVI_ATOP_5B_L (REG_DVI_ATOP_BASE + 0xB6) 710 #define REG_DVI_ATOP_5B_H (REG_DVI_ATOP_BASE + 0xB7) 711 #define REG_DVI_ATOP_5C_L (REG_DVI_ATOP_BASE + 0xB8) 712 #define REG_DVI_ATOP_5C_H (REG_DVI_ATOP_BASE + 0xB9) 713 #define REG_DVI_ATOP_5D_L (REG_DVI_ATOP_BASE + 0xBA) 714 #define REG_DVI_ATOP_5D_H (REG_DVI_ATOP_BASE + 0xBB) 715 #define REG_DVI_ATOP_5E_L (REG_DVI_ATOP_BASE + 0xBC) 716 #define REG_DVI_ATOP_5E_H (REG_DVI_ATOP_BASE + 0xBD) 717 #define REG_DVI_ATOP_5F_L (REG_DVI_ATOP_BASE + 0xBE) 718 #define REG_DVI_ATOP_5F_H (REG_DVI_ATOP_BASE + 0xBF) 719 #define REG_DVI_ATOP_60_L (REG_DVI_ATOP_BASE + 0xC0) 720 #define REG_DVI_ATOP_60_H (REG_DVI_ATOP_BASE + 0xC1) 721 #define REG_DVI_ATOP_61_L (REG_DVI_ATOP_BASE + 0xC2) 722 #define REG_DVI_ATOP_61_H (REG_DVI_ATOP_BASE + 0xC3) 723 #define REG_DVI_ATOP_62_L (REG_DVI_ATOP_BASE + 0xC4) 724 #define REG_DVI_ATOP_62_H (REG_DVI_ATOP_BASE + 0xC5) 725 #define REG_DVI_ATOP_63_L (REG_DVI_ATOP_BASE + 0xC6) 726 #define REG_DVI_ATOP_63_H (REG_DVI_ATOP_BASE + 0xC7) 727 #define REG_DVI_ATOP_64_L (REG_DVI_ATOP_BASE + 0xC8) 728 #define REG_DVI_ATOP_64_H (REG_DVI_ATOP_BASE + 0xC9) 729 #define REG_DVI_ATOP_65_L (REG_DVI_ATOP_BASE + 0xCA) 730 #define REG_DVI_ATOP_65_H (REG_DVI_ATOP_BASE + 0xCB) 731 #define REG_DVI_ATOP_66_L (REG_DVI_ATOP_BASE + 0xCC) 732 #define REG_DVI_ATOP_66_H (REG_DVI_ATOP_BASE + 0xCD) 733 #define REG_DVI_ATOP_67_L (REG_DVI_ATOP_BASE + 0xCE) 734 #define REG_DVI_ATOP_67_H (REG_DVI_ATOP_BASE + 0xCF) 735 #define REG_DVI_ATOP_68_L (REG_DVI_ATOP_BASE + 0xD0) 736 #define REG_DVI_ATOP_68_H (REG_DVI_ATOP_BASE + 0xD1) 737 #define REG_DVI_ATOP_69_L (REG_DVI_ATOP_BASE + 0xD2) 738 #define REG_DVI_ATOP_69_H (REG_DVI_ATOP_BASE + 0xD3) 739 #define REG_DVI_ATOP_6A_L (REG_DVI_ATOP_BASE + 0xD4) 740 #define REG_DVI_ATOP_6A_H (REG_DVI_ATOP_BASE + 0xD5) 741 #define REG_DVI_ATOP_6B_L (REG_DVI_ATOP_BASE + 0xD6) 742 #define REG_DVI_ATOP_6B_H (REG_DVI_ATOP_BASE + 0xD7) 743 #define REG_DVI_ATOP_6C_L (REG_DVI_ATOP_BASE + 0xD8) 744 #define REG_DVI_ATOP_6C_H (REG_DVI_ATOP_BASE + 0xD9) 745 #define REG_DVI_ATOP_6D_L (REG_DVI_ATOP_BASE + 0xDA) 746 #define REG_DVI_ATOP_6D_H (REG_DVI_ATOP_BASE + 0xDB) 747 #define REG_DVI_ATOP_6E_L (REG_DVI_ATOP_BASE + 0xDC) 748 #define REG_DVI_ATOP_6E_H (REG_DVI_ATOP_BASE + 0xDD) 749 #define REG_DVI_ATOP_6F_L (REG_DVI_ATOP_BASE + 0xDE) 750 #define REG_DVI_ATOP_6F_H (REG_DVI_ATOP_BASE + 0xDF) 751 #define REG_DVI_ATOP_70_L (REG_DVI_ATOP_BASE + 0xE0) 752 #define REG_DVI_ATOP_70_H (REG_DVI_ATOP_BASE + 0xE1) 753 #define REG_DVI_ATOP_71_L (REG_DVI_ATOP_BASE + 0xE2) 754 #define REG_DVI_ATOP_71_H (REG_DVI_ATOP_BASE + 0xE3) 755 #define REG_DVI_ATOP_72_L (REG_DVI_ATOP_BASE + 0xE4) 756 #define REG_DVI_ATOP_72_H (REG_DVI_ATOP_BASE + 0xE5) 757 #define REG_DVI_ATOP_73_L (REG_DVI_ATOP_BASE + 0xE6) 758 #define REG_DVI_ATOP_73_H (REG_DVI_ATOP_BASE + 0xE7) 759 #define REG_DVI_ATOP_74_L (REG_DVI_ATOP_BASE + 0xE8) 760 #define REG_DVI_ATOP_74_H (REG_DVI_ATOP_BASE + 0xE9) 761 #define REG_DVI_ATOP_75_L (REG_DVI_ATOP_BASE + 0xEA) 762 #define REG_DVI_ATOP_75_H (REG_DVI_ATOP_BASE + 0xEB) 763 #define REG_DVI_ATOP_76_L (REG_DVI_ATOP_BASE + 0xEC) 764 #define REG_DVI_ATOP_76_H (REG_DVI_ATOP_BASE + 0xED) 765 #define REG_DVI_ATOP_77_L (REG_DVI_ATOP_BASE + 0xEE) 766 #define REG_DVI_ATOP_77_H (REG_DVI_ATOP_BASE + 0xEF) 767 #define REG_DVI_ATOP_78_L (REG_DVI_ATOP_BASE + 0xF0) 768 #define REG_DVI_ATOP_78_H (REG_DVI_ATOP_BASE + 0xF1) 769 #define REG_DVI_ATOP_79_L (REG_DVI_ATOP_BASE + 0xF2) 770 #define REG_DVI_ATOP_79_H (REG_DVI_ATOP_BASE + 0xF3) 771 #define REG_DVI_ATOP_7A_L (REG_DVI_ATOP_BASE + 0xF4) 772 #define REG_DVI_ATOP_7A_H (REG_DVI_ATOP_BASE + 0xF5) 773 #define REG_DVI_ATOP_7B_L (REG_DVI_ATOP_BASE + 0xF6) 774 #define REG_DVI_ATOP_7B_H (REG_DVI_ATOP_BASE + 0xF7) 775 #define REG_DVI_ATOP_7C_L (REG_DVI_ATOP_BASE + 0xF8) 776 #define REG_DVI_ATOP_7C_H (REG_DVI_ATOP_BASE + 0xF9) 777 #define REG_DVI_ATOP_7D_L (REG_DVI_ATOP_BASE + 0xFA) 778 #define REG_DVI_ATOP_7D_H (REG_DVI_ATOP_BASE + 0xFB) 779 #define REG_DVI_ATOP_7E_L (REG_DVI_ATOP_BASE + 0xFC) 780 #define REG_DVI_ATOP_7E_H (REG_DVI_ATOP_BASE + 0xFD) 781 #define REG_DVI_ATOP_7F_L (REG_DVI_ATOP_BASE + 0xFE) 782 #define REG_DVI_ATOP_7F_H (REG_DVI_ATOP_BASE + 0xFF) 783 784 // DVI ATOP1 785 #define REG_DVI_ATOP1_00_L (REG_DVI_ATOP1_BASE + 0x00) 786 #define REG_DVI_ATOP1_00_H (REG_DVI_ATOP1_BASE + 0x01) 787 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) 788 #define REG_DVI_ATOP1_06_H (REG_DVI_ATOP1_BASE + 0x0D) 789 #define REG_DVI_ATOP1_07_L (REG_DVI_ATOP1_BASE + 0x0E) // ENABLE_PATCH_HDCP_FOR_SEC_PC 790 #define REG_DVI_ATOP1_32_L (REG_DVI_ATOP1_BASE + 0x64) 791 #define REG_DVI_ATOP1_32_H (REG_DVI_ATOP1_BASE + 0x65) 792 #define REG_DVI_ATOP1_5E_L (REG_DVI_ATOP1_BASE + 0xBC) 793 #define REG_DVI_ATOP1_5E_H (REG_DVI_ATOP1_BASE + 0xBD) 794 #define REG_DVI_ATOP1_60_L (REG_DVI_ATOP1_BASE + 0xC0) 795 #define REG_DVI_ATOP1_60_H (REG_DVI_ATOP1_BASE + 0xC1) 796 #define REG_DVI_ATOP1_61_L (REG_DVI_ATOP1_BASE + 0xC2) 797 #define REG_DVI_ATOP1_61_H (REG_DVI_ATOP1_BASE + 0xC3) 798 #define REG_DVI_ATOP1_62_L (REG_DVI_ATOP1_BASE + 0xC4) 799 #define REG_DVI_ATOP1_63_L (REG_DVI_ATOP1_BASE + 0xC6) 800 #define REG_DVI_ATOP1_63_H (REG_DVI_ATOP1_BASE + 0xC7) 801 #define REG_DVI_ATOP1_64_L (REG_DVI_ATOP1_BASE + 0xC8) 802 803 #define REG_DVI_ATOP1_65_L (REG_DVI_ATOP1_BASE + 0xCA) 804 #define REG_DVI_ATOP1_67_L (REG_DVI_ATOP1_BASE + 0xCE) 805 #define REG_DVI_ATOP1_68_L (REG_DVI_ATOP1_BASE + 0xD0) 806 #define REG_DVI_ATOP1_68_H (REG_DVI_ATOP1_BASE + 0xD1) 807 808 #define REG_DVI_ATOP1_70_L (REG_DVI_ATOP1_BASE + 0xE0) 809 #define REG_DVI_ATOP1_70_H (REG_DVI_ATOP1_BASE + 0xE1) 810 #define REG_DVI_ATOP1_71_L (REG_DVI_ATOP1_BASE + 0xE2) 811 #define REG_DVI_ATOP1_71_H (REG_DVI_ATOP1_BASE + 0xE3) 812 #define REG_DVI_ATOP1_74_L (REG_DVI_ATOP1_BASE + 0xE8) 813 814 // DVI ATOP2 815 #define REG_DVI_ATOP2_00_L (REG_DVI_ATOP2_BASE + 0x00) 816 #define REG_DVI_ATOP2_00_H (REG_DVI_ATOP2_BASE + 0x01) 817 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C) 818 #define REG_DVI_ATOP2_06_H (REG_DVI_ATOP2_BASE + 0x0D) 819 #define REG_DVI_ATOP2_07_L (REG_DVI_ATOP2_BASE + 0x0E) // ENABLE_PATCH_HDCP_FOR_SEC_PC 820 #define REG_DVI_ATOP2_32_L (REG_DVI_ATOP2_BASE + 0x64) 821 #define REG_DVI_ATOP2_32_H (REG_DVI_ATOP2_BASE + 0x65) 822 #define REG_DVI_ATOP2_5E_L (REG_DVI_ATOP2_BASE + 0xBC) 823 #define REG_DVI_ATOP2_5E_H (REG_DVI_ATOP2_BASE + 0xBD) 824 #define REG_DVI_ATOP2_60_L (REG_DVI_ATOP2_BASE + 0xC0) 825 #define REG_DVI_ATOP2_60_H (REG_DVI_ATOP2_BASE + 0xC1) 826 #define REG_DVI_ATOP2_61_L (REG_DVI_ATOP2_BASE + 0xC2) 827 #define REG_DVI_ATOP2_61_H (REG_DVI_ATOP2_BASE + 0xC3) 828 #define REG_DVI_ATOP2_62_L (REG_DVI_ATOP2_BASE + 0xC4) 829 #define REG_DVI_ATOP2_62_H (REG_DVI_ATOP2_BASE + 0xC5) 830 #define REG_DVI_ATOP2_63_L (REG_DVI_ATOP2_BASE + 0xC6) 831 #define REG_DVI_ATOP2_63_H (REG_DVI_ATOP2_BASE + 0xC7) 832 833 #define REG_DVI_ATOP2_64_L (REG_DVI_ATOP2_BASE + 0xC8) 834 #define REG_DVI_ATOP2_64_H (REG_DVI_ATOP2_BASE + 0xC9) 835 #define REG_DVI_ATOP2_65_L (REG_DVI_ATOP2_BASE + 0xCA) 836 #define REG_DVI_ATOP2_66_L (REG_DVI_ATOP2_BASE + 0xCC) 837 #define REG_DVI_ATOP2_66_H (REG_DVI_ATOP2_BASE + 0xCD) 838 #define REG_DVI_ATOP2_67_L (REG_DVI_ATOP2_BASE + 0xCE) 839 #define REG_DVI_ATOP2_68_L (REG_DVI_ATOP2_BASE + 0xD0) 840 #define REG_DVI_ATOP2_68_H (REG_DVI_ATOP2_BASE + 0xD1) 841 842 #define REG_DVI_ATOP2_69_L (REG_DVI_ATOP2_BASE + 0xD2) 843 #define REG_DVI_ATOP2_69_H (REG_DVI_ATOP2_BASE + 0xD3) 844 #define REG_DVI_ATOP2_6D_L (REG_DVI_ATOP2_BASE + 0xDA) 845 #define REG_DVI_ATOP2_6D_H (REG_DVI_ATOP2_BASE + 0xDB) 846 #define REG_DVI_ATOP2_70_L (REG_DVI_ATOP2_BASE + 0xE0) 847 #define REG_DVI_ATOP2_70_H (REG_DVI_ATOP2_BASE + 0xE1) 848 #define REG_DVI_ATOP2_71_L (REG_DVI_ATOP2_BASE + 0xE2) 849 #define REG_DVI_ATOP2_71_H (REG_DVI_ATOP2_BASE + 0xE3) 850 #define REG_DVI_ATOP2_74_L (REG_DVI_ATOP2_BASE + 0xE8) 851 852 // DVI ATOP3 853 #define REG_DVI_ATOP3_00_L (REG_DVI_ATOP3_BASE + 0x00) 854 #define REG_DVI_ATOP3_00_H (REG_DVI_ATOP3_BASE + 0x01) 855 #define REG_DVI_ATOP3_06_L (REG_DVI_ATOP3_BASE + 0x0C) 856 #define REG_DVI_ATOP3_06_H (REG_DVI_ATOP3_BASE + 0x0D) 857 #define REG_DVI_ATOP3_07_L (REG_DVI_ATOP3_BASE + 0x0E) 858 #define REG_DVI_ATOP3_07_H (REG_DVI_ATOP3_BASE + 0x0F) 859 #define REG_DVI_ATOP3_0A_L (REG_DVI_ATOP3_BASE + 0x14) 860 #define REG_DVI_ATOP3_0A_H (REG_DVI_ATOP3_BASE + 0x15) 861 #define REG_DVI_ATOP3_0B_L (REG_DVI_ATOP3_BASE + 0x16) 862 #define REG_DVI_ATOP3_0B_H (REG_DVI_ATOP3_BASE + 0x17) 863 #define REG_DVI_ATOP3_0C_L (REG_DVI_ATOP3_BASE + 0x18) 864 #define REG_DVI_ATOP3_0C_H (REG_DVI_ATOP3_BASE + 0x19) 865 #define REG_DVI_ATOP3_5E_L (REG_DVI_ATOP3_BASE + 0xBC) 866 #define REG_DVI_ATOP3_5E_H (REG_DVI_ATOP3_BASE + 0xBD) 867 #define REG_DVI_ATOP3_60_L (REG_DVI_ATOP3_BASE + 0xC0) 868 #define REG_DVI_ATOP3_60_H (REG_DVI_ATOP3_BASE + 0xC1) 869 #define REG_DVI_ATOP3_61_L (REG_DVI_ATOP3_BASE + 0xC2) 870 #define REG_DVI_ATOP3_61_H (REG_DVI_ATOP3_BASE + 0xC3) 871 #define REG_DVI_ATOP3_62_L (REG_DVI_ATOP3_BASE + 0xC4) 872 #define REG_DVI_ATOP3_62_H (REG_DVI_ATOP3_BASE + 0xC5) 873 #define REG_DVI_ATOP3_63_L (REG_DVI_ATOP3_BASE + 0xC6) 874 #define REG_DVI_ATOP3_63_H (REG_DVI_ATOP3_BASE + 0xC7) 875 #define REG_DVI_ATOP3_64_L (REG_DVI_ATOP3_BASE + 0xC8) 876 #define REG_DVI_ATOP3_64_H (REG_DVI_ATOP3_BASE + 0xC9) 877 #define REG_DVI_ATOP3_65_L (REG_DVI_ATOP3_BASE + 0xCA) 878 #define REG_DVI_ATOP3_65_H (REG_DVI_ATOP3_BASE + 0xCB) 879 #define REG_DVI_ATOP3_67_L (REG_DVI_ATOP3_BASE + 0xCE) 880 #define REG_DVI_ATOP3_67_H (REG_DVI_ATOP3_BASE + 0xCF) 881 #define REG_DVI_ATOP3_68_L (REG_DVI_ATOP3_BASE + 0xD0) 882 #define REG_DVI_ATOP3_68_H (REG_DVI_ATOP3_BASE + 0xD1) 883 884 #define REG_DVI_ATOP3_70_L (REG_DVI_ATOP3_BASE + 0xE0) 885 #define REG_DVI_ATOP3_70_H (REG_DVI_ATOP3_BASE + 0xE1) 886 #define REG_DVI_ATOP3_71_L (REG_DVI_ATOP3_BASE + 0xE2) 887 #define REG_DVI_ATOP3_71_H (REG_DVI_ATOP3_BASE + 0xE3) 888 #define REG_DVI_ATOP3_74_L (REG_DVI_ATOP3_BASE + 0xE8) 889 #define REG_DVI_ATOP3_74_H (REG_DVI_ATOP3_BASE + 0xE9) 890 891 //============================================================= 892 // DVI Power Saving 893 #define REG_DVI_PS_00_L (REG_DVI_PS_BASE + 0x00) 894 #define REG_DVI_PS_00_H (REG_DVI_PS_BASE + 0x01) 895 #define REG_DVI_PS_01_L (REG_DVI_PS_BASE + 0x02) 896 #define REG_DVI_PS_01_H (REG_DVI_PS_BASE + 0x03) 897 #define REG_DVI_PS_02_L (REG_DVI_PS_BASE + 0x04) 898 #define REG_DVI_PS_02_H (REG_DVI_PS_BASE + 0x05) 899 #define REG_DVI_PS_03_L (REG_DVI_PS_BASE + 0x06) 900 #define REG_DVI_PS_03_H (REG_DVI_PS_BASE + 0x07) 901 #define REG_DVI_PS_04_L (REG_DVI_PS_BASE + 0x08) // 902 #define REG_DVI_PS_04_H (REG_DVI_PS_BASE + 0x09) //add DVI VDE period change tolerance 903 #define REG_DVI_PS_06_L (REG_DVI_PS_BASE + 0x0C) 904 #define REG_DVI_PS_06_H (REG_DVI_PS_BASE + 0x0D) 905 #define REG_DVI_PS_0A_L (REG_DVI_PS_BASE + 0x14) 906 #define REG_DVI_PS_0A_H (REG_DVI_PS_BASE + 0x15) 907 #define REG_DVI_PS_0B_L (REG_DVI_PS_BASE + 0x16) 908 #define REG_DVI_PS_0B_H (REG_DVI_PS_BASE + 0x17) 909 #define REG_DVI_PS_12_L (REG_DVI_PS_BASE + 0x24) 910 #define REG_DVI_PS_12_H (REG_DVI_PS_BASE + 0x25) 911 912 913 // DVI PS1 914 #define REG_DVI_PS1_00_L (REG_DVI_PS1_BASE + 0x00) 915 #define REG_DVI_PS1_00_H (REG_DVI_PS1_BASE + 0x01) 916 #define REG_DVI_PS1_01_L (REG_DVI_PS1_BASE + 0x02) 917 #define REG_DVI_PS1_01_H (REG_DVI_PS1_BASE + 0x03) 918 #define REG_DVI_PS1_0B_L (REG_DVI_PS1_BASE + 0x16) 919 #define REG_DVI_PS1_0B_H (REG_DVI_PS1_BASE + 0x17) 920 // DVI PS2 921 #define REG_DVI_PS2_00_L (REG_DVI_PS2_BASE + 0x00) 922 #define REG_DVI_PS2_00_H (REG_DVI_PS2_BASE + 0x01) 923 #define REG_DVI_PS2_01_L (REG_DVI_PS2_BASE + 0x02) 924 #define REG_DVI_PS2_01_H (REG_DVI_PS2_BASE + 0x03) 925 #define REG_DVI_PS2_0B_L (REG_DVI_PS2_BASE + 0x16) 926 #define REG_DVI_PS2_0B_H (REG_DVI_PS2_BASE + 0x17) 927 // DVI PS3 928 #define REG_DVI_PS3_00_L (REG_DVI_PS3_BASE + 0x00) 929 #define REG_DVI_PS3_00_H (REG_DVI_PS3_BASE + 0x01) 930 #define REG_DVI_PS3_01_L (REG_DVI_PS3_BASE + 0x02) 931 #define REG_DVI_PS3_01_H (REG_DVI_PS3_BASE + 0x03) 932 #define REG_DVI_PS3_0B_L (REG_DVI_PS3_BASE + 0x16) 933 #define REG_DVI_PS3_0B_H (REG_DVI_PS3_BASE + 0x17) 934 //============================================================= 935 //HDMI 936 //#define REG_HDMI_BASE 0x2700 937 938 #define REG_HDMI_00_L (REG_HDMI_BASE + 0x00) 939 #define REG_HDMI_00_H (REG_HDMI_BASE + 0x01) 940 #define REG_HDMI_01_L (REG_HDMI_BASE + 0x02) 941 #define REG_HDMI_01_H (REG_HDMI_BASE + 0x03) 942 #define REG_HDMI_02_L (REG_HDMI_BASE + 0x04) 943 #define REG_HDMI_02_H (REG_HDMI_BASE + 0x05) 944 #define REG_HDMI_03_L (REG_HDMI_BASE + 0x06) 945 #define REG_HDMI_03_H (REG_HDMI_BASE + 0x07) 946 #define REG_HDMI_04_L (REG_HDMI_BASE + 0x08) 947 #define REG_HDMI_04_H (REG_HDMI_BASE + 0x09) 948 #define REG_HDMI_05_L (REG_HDMI_BASE + 0x0A) 949 #define REG_HDMI_05_H (REG_HDMI_BASE + 0x0B) 950 #define REG_HDMI_06_L (REG_HDMI_BASE + 0x0C) 951 #define REG_HDMI_06_H (REG_HDMI_BASE + 0x0D) 952 #define REG_HDMI_07_L (REG_HDMI_BASE + 0x0E) 953 #define REG_HDMI_07_H (REG_HDMI_BASE + 0x0F) 954 #define REG_HDMI_08_L (REG_HDMI_BASE + 0x10) 955 #define REG_HDMI_08_H (REG_HDMI_BASE + 0x11) 956 #define REG_HDMI_09_L (REG_HDMI_BASE + 0x12) 957 #define REG_HDMI_09_H (REG_HDMI_BASE + 0x13) 958 #define REG_HDMI_0A_L (REG_HDMI_BASE + 0x14) 959 #define REG_HDMI_0A_H (REG_HDMI_BASE + 0x15) 960 #define REG_HDMI_0B_L (REG_HDMI_BASE + 0x16) 961 #define REG_HDMI_0B_H (REG_HDMI_BASE + 0x17) 962 #define REG_HDMI_0C_L (REG_HDMI_BASE + 0x18) 963 #define REG_HDMI_0C_H (REG_HDMI_BASE + 0x19) 964 #define REG_HDMI_0D_L (REG_HDMI_BASE + 0x1A) 965 #define REG_HDMI_0D_H (REG_HDMI_BASE + 0x1B) 966 #define REG_HDMI_0E_L (REG_HDMI_BASE + 0x1C) 967 #define REG_HDMI_0E_H (REG_HDMI_BASE + 0x1D) 968 #define REG_HDMI_0F_L (REG_HDMI_BASE + 0x1E) 969 #define REG_HDMI_0F_H (REG_HDMI_BASE + 0x1F) 970 #define REG_HDMI_10_L (REG_HDMI_BASE + 0x20) 971 #define REG_HDMI_10_H (REG_HDMI_BASE + 0x21) 972 #define REG_HDMI_11_L (REG_HDMI_BASE + 0x22) 973 #define REG_HDMI_11_H (REG_HDMI_BASE + 0x23) 974 #define REG_HDMI_12_L (REG_HDMI_BASE + 0x24) 975 #define REG_HDMI_12_H (REG_HDMI_BASE + 0x25) 976 #define REG_HDMI_13_L (REG_HDMI_BASE + 0x26) 977 #define REG_HDMI_13_H (REG_HDMI_BASE + 0x27) 978 #define REG_HDMI_14_L (REG_HDMI_BASE + 0x28) 979 #define REG_HDMI_14_H (REG_HDMI_BASE + 0x29) 980 #define REG_HDMI_15_L (REG_HDMI_BASE + 0x2A) 981 #define REG_HDMI_15_H (REG_HDMI_BASE + 0x2B) 982 #define REG_HDMI_16_L (REG_HDMI_BASE + 0x2C) 983 #define REG_HDMI_16_H (REG_HDMI_BASE + 0x2D) 984 #define REG_HDMI_17_L (REG_HDMI_BASE + 0x2E) 985 #define REG_HDMI_17_H (REG_HDMI_BASE + 0x2F) 986 #define REG_HDMI_18_L (REG_HDMI_BASE + 0x30) 987 #define REG_HDMI_18_H (REG_HDMI_BASE + 0x31) 988 #define REG_HDMI_19_L (REG_HDMI_BASE + 0x32) 989 #define REG_HDMI_19_H (REG_HDMI_BASE + 0x33) 990 #define REG_HDMI_1A_L (REG_HDMI_BASE + 0x34) 991 #define REG_HDMI_1A_H (REG_HDMI_BASE + 0x35) 992 #define REG_HDMI_1B_L (REG_HDMI_BASE + 0x36) 993 #define REG_HDMI_1B_H (REG_HDMI_BASE + 0x37) 994 #define REG_HDMI_1C_L (REG_HDMI_BASE + 0x38) 995 #define REG_HDMI_1C_H (REG_HDMI_BASE + 0x39) 996 #define REG_HDMI_1D_L (REG_HDMI_BASE + 0x3A) 997 #define REG_HDMI_1D_H (REG_HDMI_BASE + 0x3B) 998 #define REG_HDMI_1E_L (REG_HDMI_BASE + 0x3C) 999 #define REG_HDMI_1E_H (REG_HDMI_BASE + 0x3D) 1000 #define REG_HDMI_1F_L (REG_HDMI_BASE + 0x3E) 1001 #define REG_HDMI_1F_H (REG_HDMI_BASE + 0x3F) 1002 #define REG_HDMI_20_L (REG_HDMI_BASE + 0x40) 1003 #define REG_HDMI_20_H (REG_HDMI_BASE + 0x41) 1004 #define REG_HDMI_21_L (REG_HDMI_BASE + 0x42) 1005 #define REG_HDMI_21_H (REG_HDMI_BASE + 0x43) 1006 #define REG_HDMI_22_L (REG_HDMI_BASE + 0x44) 1007 #define REG_HDMI_22_H (REG_HDMI_BASE + 0x45) 1008 #define REG_HDMI_23_L (REG_HDMI_BASE + 0x46) 1009 #define REG_HDMI_23_H (REG_HDMI_BASE + 0x47) 1010 #define REG_HDMI_24_L (REG_HDMI_BASE + 0x48) 1011 #define REG_HDMI_24_H (REG_HDMI_BASE + 0x49) 1012 #define REG_HDMI_25_L (REG_HDMI_BASE + 0x4A) 1013 #define REG_HDMI_25_H (REG_HDMI_BASE + 0x4B) 1014 #define REG_HDMI_26_L (REG_HDMI_BASE + 0x4C) 1015 #define REG_HDMI_26_H (REG_HDMI_BASE + 0x4D) 1016 #define REG_HDMI_27_L (REG_HDMI_BASE + 0x4E) 1017 #define REG_HDMI_27_H (REG_HDMI_BASE + 0x4F) 1018 #define REG_HDMI_28_L (REG_HDMI_BASE + 0x50) 1019 #define REG_HDMI_28_H (REG_HDMI_BASE + 0x51) 1020 #define REG_HDMI_29_L (REG_HDMI_BASE + 0x52) 1021 #define REG_HDMI_29_H (REG_HDMI_BASE + 0x53) 1022 #define REG_HDMI_2A_L (REG_HDMI_BASE + 0x54) 1023 #define REG_HDMI_2A_H (REG_HDMI_BASE + 0x55) 1024 #define REG_HDMI_2B_L (REG_HDMI_BASE + 0x56) 1025 #define REG_HDMI_2B_H (REG_HDMI_BASE + 0x57) 1026 #define REG_HDMI_2C_L (REG_HDMI_BASE + 0x58) 1027 #define REG_HDMI_2C_H (REG_HDMI_BASE + 0x59) 1028 #define REG_HDMI_2D_L (REG_HDMI_BASE + 0x5A) 1029 #define REG_HDMI_2D_H (REG_HDMI_BASE + 0x5B) 1030 #define REG_HDMI_2E_L (REG_HDMI_BASE + 0x5C) 1031 #define REG_HDMI_2E_H (REG_HDMI_BASE + 0x5D) 1032 #define REG_HDMI_2F_L (REG_HDMI_BASE + 0x5E) 1033 #define REG_HDMI_2F_H (REG_HDMI_BASE + 0x5F) 1034 #define REG_HDMI_30_L (REG_HDMI_BASE + 0x60) 1035 #define REG_HDMI_30_H (REG_HDMI_BASE + 0x61) 1036 #define REG_HDMI_31_L (REG_HDMI_BASE + 0x62) 1037 #define REG_HDMI_31_H (REG_HDMI_BASE + 0x63) 1038 #define REG_HDMI_32_L (REG_HDMI_BASE + 0x64) 1039 #define REG_HDMI_32_H (REG_HDMI_BASE + 0x65) 1040 #define REG_HDMI_33_L (REG_HDMI_BASE + 0x66) 1041 #define REG_HDMI_33_H (REG_HDMI_BASE + 0x67) 1042 #define REG_HDMI_34_L (REG_HDMI_BASE + 0x68) 1043 #define REG_HDMI_34_H (REG_HDMI_BASE + 0x69) 1044 #define REG_HDMI_35_L (REG_HDMI_BASE + 0x6A) 1045 #define REG_HDMI_35_H (REG_HDMI_BASE + 0x6B) 1046 #define REG_HDMI_36_L (REG_HDMI_BASE + 0x6C) 1047 #define REG_HDMI_36_H (REG_HDMI_BASE + 0x6D) 1048 #define REG_HDMI_37_L (REG_HDMI_BASE + 0x6E) 1049 #define REG_HDMI_37_H (REG_HDMI_BASE + 0x6F) 1050 #define REG_HDMI_38_L (REG_HDMI_BASE + 0x70) 1051 #define REG_HDMI_38_H (REG_HDMI_BASE + 0x71) 1052 #define REG_HDMI_39_L (REG_HDMI_BASE + 0x72) 1053 #define REG_HDMI_39_H (REG_HDMI_BASE + 0x73) 1054 #define REG_HDMI_3A_L (REG_HDMI_BASE + 0x74) 1055 #define REG_HDMI_3A_H (REG_HDMI_BASE + 0x75) 1056 #define REG_HDMI_3B_L (REG_HDMI_BASE + 0x76) 1057 #define REG_HDMI_3B_H (REG_HDMI_BASE + 0x77) 1058 #define REG_HDMI_3C_L (REG_HDMI_BASE + 0x78) 1059 #define REG_HDMI_3C_H (REG_HDMI_BASE + 0x79) 1060 #define REG_HDMI_3D_L (REG_HDMI_BASE + 0x7A) 1061 #define REG_HDMI_3D_H (REG_HDMI_BASE + 0x7B) 1062 #define REG_HDMI_3E_L (REG_HDMI_BASE + 0x7C) 1063 #define REG_HDMI_3E_H (REG_HDMI_BASE + 0x7D) 1064 #define REG_HDMI_3F_L (REG_HDMI_BASE + 0x7E) 1065 #define REG_HDMI_3F_H (REG_HDMI_BASE + 0x7F) 1066 #define REG_HDMI_40_L (REG_HDMI_BASE + 0x80) 1067 #define REG_HDMI_40_H (REG_HDMI_BASE + 0x81) 1068 #define REG_HDMI_41_L (REG_HDMI_BASE + 0x82) 1069 #define REG_HDMI_41_H (REG_HDMI_BASE + 0x83) 1070 #define REG_HDMI_42_L (REG_HDMI_BASE + 0x84) 1071 #define REG_HDMI_42_H (REG_HDMI_BASE + 0x85) 1072 #define REG_HDMI_43_L (REG_HDMI_BASE + 0x86) 1073 #define REG_HDMI_43_H (REG_HDMI_BASE + 0x87) 1074 #define REG_HDMI_44_L (REG_HDMI_BASE + 0x88) 1075 #define REG_HDMI_44_H (REG_HDMI_BASE + 0x89) 1076 #define REG_HDMI_45_L (REG_HDMI_BASE + 0x8A) 1077 #define REG_HDMI_45_H (REG_HDMI_BASE + 0x8B) 1078 #define REG_HDMI_46_L (REG_HDMI_BASE + 0x8C) 1079 #define REG_HDMI_46_H (REG_HDMI_BASE + 0x8D) 1080 #define REG_HDMI_47_L (REG_HDMI_BASE + 0x8E) 1081 #define REG_HDMI_47_H (REG_HDMI_BASE + 0x8F) 1082 #define REG_HDMI_48_L (REG_HDMI_BASE + 0x90) 1083 #define REG_HDMI_48_H (REG_HDMI_BASE + 0x91) 1084 #define REG_HDMI_49_L (REG_HDMI_BASE + 0x92) 1085 #define REG_HDMI_49_H (REG_HDMI_BASE + 0x93) 1086 #define REG_HDMI_4A_L (REG_HDMI_BASE + 0x94) 1087 #define REG_HDMI_4A_H (REG_HDMI_BASE + 0x95) 1088 #define REG_HDMI_4B_L (REG_HDMI_BASE + 0x96) 1089 #define REG_HDMI_4B_H (REG_HDMI_BASE + 0x97) 1090 #define REG_HDMI_4C_L (REG_HDMI_BASE + 0x98) 1091 #define REG_HDMI_4C_H (REG_HDMI_BASE + 0x99) 1092 #define REG_HDMI_4D_L (REG_HDMI_BASE + 0x9A) 1093 #define REG_HDMI_4D_H (REG_HDMI_BASE + 0x9B) 1094 #define REG_HDMI_4E_L (REG_HDMI_BASE + 0x9C) 1095 #define REG_HDMI_4E_H (REG_HDMI_BASE + 0x9D) 1096 #define REG_HDMI_4F_L (REG_HDMI_BASE + 0x9E) 1097 #define REG_HDMI_4F_H (REG_HDMI_BASE + 0x9F) 1098 #define REG_HDMI_50_L (REG_HDMI_BASE + 0xA0) 1099 #define REG_HDMI_50_H (REG_HDMI_BASE + 0xA1) 1100 #define REG_HDMI_51_L (REG_HDMI_BASE + 0xA2) 1101 #define REG_HDMI_51_H (REG_HDMI_BASE + 0xA3) 1102 #define REG_HDMI_52_L (REG_HDMI_BASE + 0xA4) 1103 #define REG_HDMI_52_H (REG_HDMI_BASE + 0xA5) 1104 #define REG_HDMI_53_L (REG_HDMI_BASE + 0xA6) 1105 #define REG_HDMI_53_H (REG_HDMI_BASE + 0xA7) 1106 #define REG_HDMI_54_L (REG_HDMI_BASE + 0xA8) 1107 #define REG_HDMI_54_H (REG_HDMI_BASE + 0xA9) 1108 #define REG_HDMI_55_L (REG_HDMI_BASE + 0xAA) 1109 #define REG_HDMI_55_H (REG_HDMI_BASE + 0xAB) 1110 #define REG_HDMI_56_L (REG_HDMI_BASE + 0xAC) 1111 #define REG_HDMI_56_H (REG_HDMI_BASE + 0xAD) 1112 #define REG_HDMI_57_L (REG_HDMI_BASE + 0xAE) 1113 #define REG_HDMI_57_H (REG_HDMI_BASE + 0xAF) 1114 #define REG_HDMI_58_L (REG_HDMI_BASE + 0xB0) 1115 #define REG_HDMI_58_H (REG_HDMI_BASE + 0xB1) 1116 #define REG_HDMI_59_L (REG_HDMI_BASE + 0xB2) 1117 #define REG_HDMI_59_H (REG_HDMI_BASE + 0xB3) 1118 #define REG_HDMI_5A_L (REG_HDMI_BASE + 0xB4) 1119 #define REG_HDMI_5A_H (REG_HDMI_BASE + 0xB5) 1120 #define REG_HDMI_5B_L (REG_HDMI_BASE + 0xB6) 1121 #define REG_HDMI_5B_H (REG_HDMI_BASE + 0xB7) 1122 #define REG_HDMI_5C_L (REG_HDMI_BASE + 0xB8) 1123 #define REG_HDMI_5C_H (REG_HDMI_BASE + 0xB9) 1124 #define REG_HDMI_5D_L (REG_HDMI_BASE + 0xBA) 1125 #define REG_HDMI_5D_H (REG_HDMI_BASE + 0xBB) 1126 #define REG_HDMI_5E_L (REG_HDMI_BASE + 0xBC) 1127 #define REG_HDMI_5E_H (REG_HDMI_BASE + 0xBD) 1128 #define REG_HDMI_5F_L (REG_HDMI_BASE + 0xBE) 1129 #define REG_HDMI_5F_H (REG_HDMI_BASE + 0xBF) 1130 #define REG_HDMI_60_L (REG_HDMI_BASE + 0xC0) 1131 #define REG_HDMI_60_H (REG_HDMI_BASE + 0xC1) 1132 #define REG_HDMI_61_L (REG_HDMI_BASE + 0xC2) 1133 #define REG_HDMI_61_H (REG_HDMI_BASE + 0xC3) 1134 #define REG_HDMI_62_L (REG_HDMI_BASE + 0xC4) 1135 #define REG_HDMI_62_H (REG_HDMI_BASE + 0xC5) 1136 #define REG_HDMI_63_L (REG_HDMI_BASE + 0xC6) 1137 #define REG_HDMI_63_H (REG_HDMI_BASE + 0xC7) 1138 #define REG_HDMI_64_L (REG_HDMI_BASE + 0xC8) 1139 #define REG_HDMI_64_H (REG_HDMI_BASE + 0xC9) 1140 #define REG_HDMI_65_L (REG_HDMI_BASE + 0xCA) 1141 #define REG_HDMI_65_H (REG_HDMI_BASE + 0xCB) 1142 #define REG_HDMI_66_L (REG_HDMI_BASE + 0xCC) 1143 #define REG_HDMI_66_H (REG_HDMI_BASE + 0xCD) 1144 #define REG_HDMI_67_L (REG_HDMI_BASE + 0xCE) 1145 #define REG_HDMI_67_H (REG_HDMI_BASE + 0xCF) 1146 #define REG_HDMI_68_L (REG_HDMI_BASE + 0xD0) 1147 #define REG_HDMI_68_H (REG_HDMI_BASE + 0xD1) 1148 #define REG_HDMI_69_L (REG_HDMI_BASE + 0xD2) 1149 #define REG_HDMI_69_H (REG_HDMI_BASE + 0xD3) 1150 #define REG_HDMI_6A_L (REG_HDMI_BASE + 0xD4) 1151 #define REG_HDMI_6A_H (REG_HDMI_BASE + 0xD5) 1152 #define REG_HDMI_6B_L (REG_HDMI_BASE + 0xD6) 1153 #define REG_HDMI_6B_H (REG_HDMI_BASE + 0xD7) 1154 #define REG_HDMI_6C_L (REG_HDMI_BASE + 0xD8) 1155 #define REG_HDMI_6C_H (REG_HDMI_BASE + 0xD9) 1156 #define REG_HDMI_6D_L (REG_HDMI_BASE + 0xDA) 1157 #define REG_HDMI_6D_H (REG_HDMI_BASE + 0xDB) 1158 #define REG_HDMI_6E_L (REG_HDMI_BASE + 0xDC) 1159 #define REG_HDMI_6E_H (REG_HDMI_BASE + 0xDD) 1160 #define REG_HDMI_6F_L (REG_HDMI_BASE + 0xDE) 1161 #define REG_HDMI_6F_H (REG_HDMI_BASE + 0xDF) 1162 #define REG_HDMI_70_L (REG_HDMI_BASE + 0xE0) 1163 #define REG_HDMI_70_H (REG_HDMI_BASE + 0xE1) 1164 #define REG_HDMI_71_L (REG_HDMI_BASE + 0xE2) 1165 #define REG_HDMI_71_H (REG_HDMI_BASE + 0xE3) 1166 #define REG_HDMI_72_L (REG_HDMI_BASE + 0xE4) 1167 #define REG_HDMI_72_H (REG_HDMI_BASE + 0xE5) 1168 #define REG_HDMI_73_L (REG_HDMI_BASE + 0xE6) 1169 #define REG_HDMI_73_H (REG_HDMI_BASE + 0xE7) 1170 #define REG_HDMI_74_L (REG_HDMI_BASE + 0xE8) 1171 #define REG_HDMI_74_H (REG_HDMI_BASE + 0xE9) 1172 #define REG_HDMI_75_L (REG_HDMI_BASE + 0xEA) 1173 #define REG_HDMI_75_H (REG_HDMI_BASE + 0xEB) 1174 #define REG_HDMI_76_L (REG_HDMI_BASE + 0xEC) 1175 #define REG_HDMI_76_H (REG_HDMI_BASE + 0xED) 1176 #define REG_HDMI_77_L (REG_HDMI_BASE + 0xEE) 1177 #define REG_HDMI_77_H (REG_HDMI_BASE + 0xEF) 1178 #define REG_HDMI_78_L (REG_HDMI_BASE + 0xF0) 1179 #define REG_HDMI_78_H (REG_HDMI_BASE + 0xF1) 1180 #define REG_HDMI_79_L (REG_HDMI_BASE + 0xF2) 1181 #define REG_HDMI_79_H (REG_HDMI_BASE + 0xF3) 1182 #define REG_HDMI_7A_L (REG_HDMI_BASE + 0xF4) 1183 #define REG_HDMI_7A_H (REG_HDMI_BASE + 0xF5) 1184 #define REG_HDMI_7B_L (REG_HDMI_BASE + 0xF6) 1185 #define REG_HDMI_7B_H (REG_HDMI_BASE + 0xF7) 1186 #define REG_HDMI_7C_L (REG_HDMI_BASE + 0xF8) 1187 #define REG_HDMI_7C_H (REG_HDMI_BASE + 0xF9) 1188 #define REG_HDMI_7D_L (REG_HDMI_BASE + 0xFA) 1189 #define REG_HDMI_7D_H (REG_HDMI_BASE + 0xFB) 1190 #define REG_HDMI_7E_L (REG_HDMI_BASE + 0xFC) 1191 #define REG_HDMI_7E_H (REG_HDMI_BASE + 0xFD) 1192 #define REG_HDMI_7F_L (REG_HDMI_BASE + 0xFE) 1193 #define REG_HDMI_7F_H (REG_HDMI_BASE + 0xFF) 1194 1195 // HDMI2 1196 #define REG_HDMI2_01_L (REG_HDMI2_BASE + 0x02) 1197 #define REG_HDMI2_01_H (REG_HDMI2_BASE + 0x03) 1198 #define REG_HDMI2_02_L (REG_HDMI2_BASE + 0x04) 1199 #define REG_HDMI2_02_H (REG_HDMI2_BASE + 0x05) 1200 #define REG_HDMI2_03_L (REG_HDMI2_BASE + 0x06) 1201 #define REG_HDMI2_03_H (REG_HDMI2_BASE + 0x07) 1202 #define REG_HDMI2_06_L (REG_HDMI2_BASE + 0x0C) 1203 #define REG_HDMI2_06_H (REG_HDMI2_BASE + 0x0D) 1204 #define REG_HDMI2_08_L (REG_HDMI2_BASE + 0x10) 1205 #define REG_HDMI2_08_H (REG_HDMI2_BASE + 0x11) 1206 #define REG_HDMI2_10_L (REG_HDMI2_BASE + 0x20) 1207 #define REG_HDMI2_10_H (REG_HDMI2_BASE + 0x21) 1208 #define REG_HDMI2_11_L (REG_HDMI2_BASE + 0x22) 1209 #define REG_HDMI2_11_H (REG_HDMI2_BASE + 0x23) 1210 #define REG_HDMI2_12_L (REG_HDMI2_BASE + 0x24) 1211 #define REG_HDMI2_12_H (REG_HDMI2_BASE + 0x25) 1212 #define REG_HDMI2_13_L (REG_HDMI2_BASE + 0x26) 1213 #define REG_HDMI2_13_H (REG_HDMI2_BASE + 0x27) 1214 #define REG_HDMI2_15_L (REG_HDMI2_BASE + 0x2A) 1215 #define REG_HDMI2_15_H (REG_HDMI2_BASE + 0x2B) 1216 #define REG_HDMI2_20_L (REG_HDMI2_BASE + 0x40) 1217 #define REG_HDMI2_20_H (REG_HDMI2_BASE + 0x41) 1218 #define REG_HDMI2_25_L (REG_HDMI2_BASE + 0x4A) 1219 #define REG_HDMI2_25_H (REG_HDMI2_BASE + 0x4B) 1220 #define REG_HDMI2_26_L (REG_HDMI2_BASE + 0x4C) 1221 #define REG_HDMI2_26_H (REG_HDMI2_BASE + 0x4D) 1222 #define REG_HDMI2_27_L (REG_HDMI2_BASE + 0x4E) 1223 #define REG_HDMI2_27_H (REG_HDMI2_BASE + 0x4F) 1224 #define REG_HDMI2_33_L (REG_HDMI2_BASE + 0x66) 1225 #define REG_HDMI2_34_L (REG_HDMI2_BASE + 0x68) 1226 #define REG_HDMI2_35_L (REG_HDMI2_BASE + 0x6A) 1227 #define REG_HDMI2_36_L (REG_HDMI2_BASE + 0x6C) 1228 #define REG_HDMI2_36_H (REG_HDMI2_BASE + 0x6D) 1229 1230 //#define REG_MHL_TMDS_BASE 0x2700 1231 #define REG_MHL_TMDS_00_L (REG_MHL_TMDS_BASE + 0x00) 1232 #define REG_MHL_TMDS_00_H (REG_MHL_TMDS_BASE + 0x01) 1233 #define REG_MHL_TMDS_01_L (REG_MHL_TMDS_BASE + 0x02) 1234 #define REG_MHL_TMDS_01_H (REG_MHL_TMDS_BASE + 0x03) 1235 #define REG_MHL_TMDS_02_L (REG_MHL_TMDS_BASE + 0x04) 1236 #define REG_MHL_TMDS_02_H (REG_MHL_TMDS_BASE + 0x05) 1237 #define REG_MHL_TMDS_03_L (REG_MHL_TMDS_BASE + 0x06) 1238 #define REG_MHL_TMDS_03_H (REG_MHL_TMDS_BASE + 0x07) 1239 #define REG_MHL_TMDS_04_L (REG_MHL_TMDS_BASE + 0x08) 1240 #define REG_MHL_TMDS_04_H (REG_MHL_TMDS_BASE + 0x09) 1241 #define REG_MHL_TMDS_05_L (REG_MHL_TMDS_BASE + 0x0A) 1242 #define REG_MHL_TMDS_05_H (REG_MHL_TMDS_BASE + 0x0B) 1243 #define REG_MHL_TMDS_06_L (REG_MHL_TMDS_BASE + 0x0C) 1244 #define REG_MHL_TMDS_06_H (REG_MHL_TMDS_BASE + 0x0D) 1245 #define REG_MHL_TMDS_07_L (REG_MHL_TMDS_BASE + 0x0E) 1246 #define REG_MHL_TMDS_07_H (REG_MHL_TMDS_BASE + 0x0F) 1247 #define REG_MHL_TMDS_08_L (REG_MHL_TMDS_BASE + 0x10) 1248 #define REG_MHL_TMDS_08_H (REG_MHL_TMDS_BASE + 0x11) 1249 #define REG_MHL_TMDS_09_L (REG_MHL_TMDS_BASE + 0x12) 1250 #define REG_MHL_TMDS_09_H (REG_MHL_TMDS_BASE + 0x13) 1251 #define REG_MHL_TMDS_0A_L (REG_MHL_TMDS_BASE + 0x14) 1252 #define REG_MHL_TMDS_0A_H (REG_MHL_TMDS_BASE + 0x15) 1253 #define REG_MHL_TMDS_0B_L (REG_MHL_TMDS_BASE + 0x16) 1254 #define REG_MHL_TMDS_0B_H (REG_MHL_TMDS_BASE + 0x17) 1255 #define REG_MHL_TMDS_0C_L (REG_MHL_TMDS_BASE + 0x18) 1256 #define REG_MHL_TMDS_0C_H (REG_MHL_TMDS_BASE + 0x19) 1257 #define REG_MHL_TMDS_0D_L (REG_MHL_TMDS_BASE + 0x1A) 1258 #define REG_MHL_TMDS_0D_H (REG_MHL_TMDS_BASE + 0x1B) 1259 #define REG_MHL_TMDS_0E_L (REG_MHL_TMDS_BASE + 0x1C) 1260 #define REG_MHL_TMDS_0E_H (REG_MHL_TMDS_BASE + 0x1D) 1261 #define REG_MHL_TMDS_0F_L (REG_MHL_TMDS_BASE + 0x1E) 1262 #define REG_MHL_TMDS_0F_H (REG_MHL_TMDS_BASE + 0x1F) 1263 #define REG_MHL_TMDS_10_L (REG_MHL_TMDS_BASE + 0x20) 1264 #define REG_MHL_TMDS_10_H (REG_MHL_TMDS_BASE + 0x21) 1265 #define REG_MHL_TMDS_11_L (REG_MHL_TMDS_BASE + 0x22) 1266 #define REG_MHL_TMDS_11_H (REG_MHL_TMDS_BASE + 0x23) 1267 #define REG_MHL_TMDS_12_L (REG_MHL_TMDS_BASE + 0x24) 1268 #define REG_MHL_TMDS_12_H (REG_MHL_TMDS_BASE + 0x25) 1269 #define REG_MHL_TMDS_13_L (REG_MHL_TMDS_BASE + 0x26) 1270 #define REG_MHL_TMDS_13_H (REG_MHL_TMDS_BASE + 0x27) 1271 #define REG_MHL_TMDS_14_L (REG_MHL_TMDS_BASE + 0x28) 1272 #define REG_MHL_TMDS_14_H (REG_MHL_TMDS_BASE + 0x29) 1273 #define REG_MHL_TMDS_15_L (REG_MHL_TMDS_BASE + 0x2A) 1274 #define REG_MHL_TMDS_15_H (REG_MHL_TMDS_BASE + 0x2B) 1275 #define REG_MHL_TMDS_16_L (REG_MHL_TMDS_BASE + 0x2C) 1276 #define REG_MHL_TMDS_16_H (REG_MHL_TMDS_BASE + 0x2D) 1277 #define REG_MHL_TMDS_17_L (REG_MHL_TMDS_BASE + 0x2E) 1278 #define REG_MHL_TMDS_17_H (REG_MHL_TMDS_BASE + 0x2F) 1279 #define REG_MHL_TMDS_18_L (REG_MHL_TMDS_BASE + 0x30) 1280 #define REG_MHL_TMDS_18_H (REG_MHL_TMDS_BASE + 0x31) 1281 #define REG_MHL_TMDS_19_L (REG_MHL_TMDS_BASE + 0x32) 1282 #define REG_MHL_TMDS_19_H (REG_MHL_TMDS_BASE + 0x33) 1283 #define REG_MHL_TMDS_1A_L (REG_MHL_TMDS_BASE + 0x34) 1284 #define REG_MHL_TMDS_1A_H (REG_MHL_TMDS_BASE + 0x35) 1285 #define REG_MHL_TMDS_1B_L (REG_MHL_TMDS_BASE + 0x36) 1286 #define REG_MHL_TMDS_1B_H (REG_MHL_TMDS_BASE + 0x37) 1287 #define REG_MHL_TMDS_1C_L (REG_MHL_TMDS_BASE + 0x38) 1288 #define REG_MHL_TMDS_1C_H (REG_MHL_TMDS_BASE + 0x39) 1289 #define REG_MHL_TMDS_1D_L (REG_MHL_TMDS_BASE + 0x3A) 1290 #define REG_MHL_TMDS_1D_H (REG_MHL_TMDS_BASE + 0x3B) 1291 #define REG_MHL_TMDS_1E_L (REG_MHL_TMDS_BASE + 0x3C) 1292 #define REG_MHL_TMDS_1E_H (REG_MHL_TMDS_BASE + 0x3D) 1293 #define REG_MHL_TMDS_1F_L (REG_MHL_TMDS_BASE + 0x3E) 1294 #define REG_MHL_TMDS_1F_H (REG_MHL_TMDS_BASE + 0x3F) 1295 #define REG_MHL_TMDS_20_L (REG_MHL_TMDS_BASE + 0x40) 1296 #define REG_MHL_TMDS_20_H (REG_MHL_TMDS_BASE + 0x41) 1297 #define REG_MHL_TMDS_21_L (REG_MHL_TMDS_BASE + 0x42) 1298 #define REG_MHL_TMDS_21_H (REG_MHL_TMDS_BASE + 0x43) 1299 #define REG_MHL_TMDS_22_L (REG_MHL_TMDS_BASE + 0x44) 1300 #define REG_MHL_TMDS_22_H (REG_MHL_TMDS_BASE + 0x45) 1301 #define REG_MHL_TMDS_23_L (REG_MHL_TMDS_BASE + 0x46) 1302 #define REG_MHL_TMDS_23_H (REG_MHL_TMDS_BASE + 0x47) 1303 #define REG_MHL_TMDS_24_L (REG_MHL_TMDS_BASE + 0x48) 1304 #define REG_MHL_TMDS_24_H (REG_MHL_TMDS_BASE + 0x49) 1305 #define REG_MHL_TMDS_25_L (REG_MHL_TMDS_BASE + 0x4A) 1306 #define REG_MHL_TMDS_25_H (REG_MHL_TMDS_BASE + 0x4B) 1307 #define REG_MHL_TMDS_26_L (REG_MHL_TMDS_BASE + 0x4C) 1308 #define REG_MHL_TMDS_26_H (REG_MHL_TMDS_BASE + 0x4D) 1309 #define REG_MHL_TMDS_27_L (REG_MHL_TMDS_BASE + 0x4E) 1310 #define REG_MHL_TMDS_27_H (REG_MHL_TMDS_BASE + 0x4F) 1311 #define REG_MHL_TMDS_28_L (REG_MHL_TMDS_BASE + 0x50) 1312 #define REG_MHL_TMDS_28_H (REG_MHL_TMDS_BASE + 0x51) 1313 #define REG_MHL_TMDS_29_L (REG_MHL_TMDS_BASE + 0x52) 1314 #define REG_MHL_TMDS_29_H (REG_MHL_TMDS_BASE + 0x53) 1315 #define REG_MHL_TMDS_2A_L (REG_MHL_TMDS_BASE + 0x54) 1316 #define REG_MHL_TMDS_2A_H (REG_MHL_TMDS_BASE + 0x55) 1317 #define REG_MHL_TMDS_2B_L (REG_MHL_TMDS_BASE + 0x56) 1318 #define REG_MHL_TMDS_2B_H (REG_MHL_TMDS_BASE + 0x57) 1319 #define REG_MHL_TMDS_2C_L (REG_MHL_TMDS_BASE + 0x58) 1320 #define REG_MHL_TMDS_2C_H (REG_MHL_TMDS_BASE + 0x59) 1321 #define REG_MHL_TMDS_2D_L (REG_MHL_TMDS_BASE + 0x5A) 1322 #define REG_MHL_TMDS_2D_H (REG_MHL_TMDS_BASE + 0x5B) 1323 #define REG_MHL_TMDS_2E_L (REG_MHL_TMDS_BASE + 0x5C) 1324 #define REG_MHL_TMDS_2E_H (REG_MHL_TMDS_BASE + 0x5D) 1325 #define REG_MHL_TMDS_2F_L (REG_MHL_TMDS_BASE + 0x5E) 1326 #define REG_MHL_TMDS_2F_H (REG_MHL_TMDS_BASE + 0x5F) 1327 #define REG_MHL_TMDS_30_L (REG_MHL_TMDS_BASE + 0x60) 1328 #define REG_MHL_TMDS_30_H (REG_MHL_TMDS_BASE + 0x61) 1329 #define REG_MHL_TMDS_31_L (REG_MHL_TMDS_BASE + 0x62) 1330 #define REG_MHL_TMDS_31_H (REG_MHL_TMDS_BASE + 0x63) 1331 #define REG_MHL_TMDS_32_L (REG_MHL_TMDS_BASE + 0x64) 1332 #define REG_MHL_TMDS_32_H (REG_MHL_TMDS_BASE + 0x65) 1333 #define REG_MHL_TMDS_33_L (REG_MHL_TMDS_BASE + 0x66) 1334 #define REG_MHL_TMDS_33_H (REG_MHL_TMDS_BASE + 0x67) 1335 #define REG_MHL_TMDS_34_L (REG_MHL_TMDS_BASE + 0x68) 1336 #define REG_MHL_TMDS_34_H (REG_MHL_TMDS_BASE + 0x69) 1337 #define REG_MHL_TMDS_35_L (REG_MHL_TMDS_BASE + 0x6A) 1338 #define REG_MHL_TMDS_35_H (REG_MHL_TMDS_BASE + 0x6B) 1339 #define REG_MHL_TMDS_36_L (REG_MHL_TMDS_BASE + 0x6C) 1340 #define REG_MHL_TMDS_36_H (REG_MHL_TMDS_BASE + 0x6D) 1341 #define REG_MHL_TMDS_37_L (REG_MHL_TMDS_BASE + 0x6E) 1342 #define REG_MHL_TMDS_37_H (REG_MHL_TMDS_BASE + 0x6F) 1343 #define REG_MHL_TMDS_38_L (REG_MHL_TMDS_BASE + 0x70) 1344 #define REG_MHL_TMDS_38_H (REG_MHL_TMDS_BASE + 0x71) 1345 #define REG_MHL_TMDS_39_L (REG_MHL_TMDS_BASE + 0x72) 1346 #define REG_MHL_TMDS_39_H (REG_MHL_TMDS_BASE + 0x73) 1347 #define REG_MHL_TMDS_3A_L (REG_MHL_TMDS_BASE + 0x74) 1348 #define REG_MHL_TMDS_3A_H (REG_MHL_TMDS_BASE + 0x75) 1349 #define REG_MHL_TMDS_3B_L (REG_MHL_TMDS_BASE + 0x76) 1350 #define REG_MHL_TMDS_3B_H (REG_MHL_TMDS_BASE + 0x77) 1351 #define REG_MHL_TMDS_3C_L (REG_MHL_TMDS_BASE + 0x78) 1352 #define REG_MHL_TMDS_3C_H (REG_MHL_TMDS_BASE + 0x79) 1353 #define REG_MHL_TMDS_3D_L (REG_MHL_TMDS_BASE + 0x7A) 1354 #define REG_MHL_TMDS_3D_H (REG_MHL_TMDS_BASE + 0x7B) 1355 #define REG_MHL_TMDS_3E_L (REG_MHL_TMDS_BASE + 0x7C) 1356 #define REG_MHL_TMDS_3E_H (REG_MHL_TMDS_BASE + 0x7D) 1357 #define REG_MHL_TMDS_3F_L (REG_MHL_TMDS_BASE + 0x7E) 1358 #define REG_MHL_TMDS_3F_H (REG_MHL_TMDS_BASE + 0x7F) 1359 #define REG_MHL_TMDS_40_L (REG_MHL_TMDS_BASE + 0x80) 1360 #define REG_MHL_TMDS_40_H (REG_MHL_TMDS_BASE + 0x81) 1361 #define REG_MHL_TMDS_41_L (REG_MHL_TMDS_BASE + 0x82) 1362 #define REG_MHL_TMDS_41_H (REG_MHL_TMDS_BASE + 0x83) 1363 #define REG_MHL_TMDS_42_L (REG_MHL_TMDS_BASE + 0x84) 1364 #define REG_MHL_TMDS_42_H (REG_MHL_TMDS_BASE + 0x85) 1365 #define REG_MHL_TMDS_43_L (REG_MHL_TMDS_BASE + 0x86) 1366 #define REG_MHL_TMDS_43_H (REG_MHL_TMDS_BASE + 0x87) 1367 #define REG_MHL_TMDS_44_L (REG_MHL_TMDS_BASE + 0x88) 1368 #define REG_MHL_TMDS_44_H (REG_MHL_TMDS_BASE + 0x89) 1369 #define REG_MHL_TMDS_45_L (REG_MHL_TMDS_BASE + 0x8A) 1370 #define REG_MHL_TMDS_45_H (REG_MHL_TMDS_BASE + 0x8B) 1371 #define REG_MHL_TMDS_46_L (REG_MHL_TMDS_BASE + 0x8C) 1372 #define REG_MHL_TMDS_46_H (REG_MHL_TMDS_BASE + 0x8D) 1373 #define REG_MHL_TMDS_47_L (REG_MHL_TMDS_BASE + 0x8E) 1374 #define REG_MHL_TMDS_47_H (REG_MHL_TMDS_BASE + 0x8F) 1375 #define REG_MHL_TMDS_48_L (REG_MHL_TMDS_BASE + 0x90) 1376 #define REG_MHL_TMDS_48_H (REG_MHL_TMDS_BASE + 0x91) 1377 #define REG_MHL_TMDS_49_L (REG_MHL_TMDS_BASE + 0x92) 1378 #define REG_MHL_TMDS_49_H (REG_MHL_TMDS_BASE + 0x93) 1379 #define REG_MHL_TMDS_4A_L (REG_MHL_TMDS_BASE + 0x94) 1380 #define REG_MHL_TMDS_4A_H (REG_MHL_TMDS_BASE + 0x95) 1381 #define REG_MHL_TMDS_4B_L (REG_MHL_TMDS_BASE + 0x96) 1382 #define REG_MHL_TMDS_4B_H (REG_MHL_TMDS_BASE + 0x97) 1383 #define REG_MHL_TMDS_4C_L (REG_MHL_TMDS_BASE + 0x98) 1384 #define REG_MHL_TMDS_4C_H (REG_MHL_TMDS_BASE + 0x99) 1385 #define REG_MHL_TMDS_4D_L (REG_MHL_TMDS_BASE + 0x9A) 1386 #define REG_MHL_TMDS_4D_H (REG_MHL_TMDS_BASE + 0x9B) 1387 #define REG_MHL_TMDS_4E_L (REG_MHL_TMDS_BASE + 0x9C) 1388 #define REG_MHL_TMDS_4E_H (REG_MHL_TMDS_BASE + 0x9D) 1389 #define REG_MHL_TMDS_4F_L (REG_MHL_TMDS_BASE + 0x9E) 1390 #define REG_MHL_TMDS_4F_H (REG_MHL_TMDS_BASE + 0x9F) 1391 #define REG_MHL_TMDS_50_L (REG_MHL_TMDS_BASE + 0xA0) 1392 #define REG_MHL_TMDS_50_H (REG_MHL_TMDS_BASE + 0xA1) 1393 #define REG_MHL_TMDS_51_L (REG_MHL_TMDS_BASE + 0xA2) 1394 #define REG_MHL_TMDS_51_H (REG_MHL_TMDS_BASE + 0xA3) 1395 #define REG_MHL_TMDS_52_L (REG_MHL_TMDS_BASE + 0xA4) 1396 #define REG_MHL_TMDS_52_H (REG_MHL_TMDS_BASE + 0xA5) 1397 #define REG_MHL_TMDS_53_L (REG_MHL_TMDS_BASE + 0xA6) 1398 #define REG_MHL_TMDS_53_H (REG_MHL_TMDS_BASE + 0xA7) 1399 #define REG_MHL_TMDS_54_L (REG_MHL_TMDS_BASE + 0xA8) 1400 #define REG_MHL_TMDS_54_H (REG_MHL_TMDS_BASE + 0xA9) 1401 #define REG_MHL_TMDS_55_L (REG_MHL_TMDS_BASE + 0xAA) 1402 #define REG_MHL_TMDS_55_H (REG_MHL_TMDS_BASE + 0xAB) 1403 #define REG_MHL_TMDS_56_L (REG_MHL_TMDS_BASE + 0xAC) 1404 #define REG_MHL_TMDS_56_H (REG_MHL_TMDS_BASE + 0xAD) 1405 #define REG_MHL_TMDS_57_L (REG_MHL_TMDS_BASE + 0xAE) 1406 #define REG_MHL_TMDS_57_H (REG_MHL_TMDS_BASE + 0xAF) 1407 #define REG_MHL_TMDS_58_L (REG_MHL_TMDS_BASE + 0xB0) 1408 #define REG_MHL_TMDS_58_H (REG_MHL_TMDS_BASE + 0xB1) 1409 #define REG_MHL_TMDS_59_L (REG_MHL_TMDS_BASE + 0xB2) 1410 #define REG_MHL_TMDS_59_H (REG_MHL_TMDS_BASE + 0xB3) 1411 #define REG_MHL_TMDS_5A_L (REG_MHL_TMDS_BASE + 0xB4) 1412 #define REG_MHL_TMDS_5A_H (REG_MHL_TMDS_BASE + 0xB5) 1413 #define REG_MHL_TMDS_5B_L (REG_MHL_TMDS_BASE + 0xB6) 1414 #define REG_MHL_TMDS_5B_H (REG_MHL_TMDS_BASE + 0xB7) 1415 #define REG_MHL_TMDS_5C_L (REG_MHL_TMDS_BASE + 0xB8) 1416 #define REG_MHL_TMDS_5C_H (REG_MHL_TMDS_BASE + 0xB9) 1417 #define REG_MHL_TMDS_5D_L (REG_MHL_TMDS_BASE + 0xBA) 1418 #define REG_MHL_TMDS_5D_H (REG_MHL_TMDS_BASE + 0xBB) 1419 #define REG_MHL_TMDS_5E_L (REG_MHL_TMDS_BASE + 0xBC) 1420 #define REG_MHL_TMDS_5E_H (REG_MHL_TMDS_BASE + 0xBD) 1421 #define REG_MHL_TMDS_5F_L (REG_MHL_TMDS_BASE + 0xBE) 1422 #define REG_MHL_TMDS_5F_H (REG_MHL_TMDS_BASE + 0xBF) 1423 #define REG_MHL_TMDS_60_L (REG_MHL_TMDS_BASE + 0xC0) 1424 #define REG_MHL_TMDS_60_H (REG_MHL_TMDS_BASE + 0xC1) 1425 #define REG_MHL_TMDS_61_L (REG_MHL_TMDS_BASE + 0xC2) 1426 #define REG_MHL_TMDS_61_H (REG_MHL_TMDS_BASE + 0xC3) 1427 #define REG_MHL_TMDS_62_L (REG_MHL_TMDS_BASE + 0xC4) 1428 #define REG_MHL_TMDS_62_H (REG_MHL_TMDS_BASE + 0xC5) 1429 #define REG_MHL_TMDS_63_L (REG_MHL_TMDS_BASE + 0xC6) 1430 #define REG_MHL_TMDS_63_H (REG_MHL_TMDS_BASE + 0xC7) 1431 #define REG_MHL_TMDS_64_L (REG_MHL_TMDS_BASE + 0xC8) 1432 #define REG_MHL_TMDS_64_H (REG_MHL_TMDS_BASE + 0xC9) 1433 #define REG_MHL_TMDS_65_L (REG_MHL_TMDS_BASE + 0xCA) 1434 #define REG_MHL_TMDS_65_H (REG_MHL_TMDS_BASE + 0xCB) 1435 #define REG_MHL_TMDS_66_L (REG_MHL_TMDS_BASE + 0xCC) 1436 #define REG_MHL_TMDS_66_H (REG_MHL_TMDS_BASE + 0xCD) 1437 #define REG_MHL_TMDS_67_L (REG_MHL_TMDS_BASE + 0xCE) 1438 #define REG_MHL_TMDS_67_H (REG_MHL_TMDS_BASE + 0xCF) 1439 #define REG_MHL_TMDS_68_L (REG_MHL_TMDS_BASE + 0xD0) 1440 #define REG_MHL_TMDS_68_H (REG_MHL_TMDS_BASE + 0xD1) 1441 #define REG_MHL_TMDS_69_L (REG_MHL_TMDS_BASE + 0xD2) 1442 #define REG_MHL_TMDS_69_H (REG_MHL_TMDS_BASE + 0xD3) 1443 #define REG_MHL_TMDS_6A_L (REG_MHL_TMDS_BASE + 0xD4) 1444 #define REG_MHL_TMDS_6A_H (REG_MHL_TMDS_BASE + 0xD5) 1445 #define REG_MHL_TMDS_6B_L (REG_MHL_TMDS_BASE + 0xD6) 1446 #define REG_MHL_TMDS_6B_H (REG_MHL_TMDS_BASE + 0xD7) 1447 #define REG_MHL_TMDS_6C_L (REG_MHL_TMDS_BASE + 0xD8) 1448 #define REG_MHL_TMDS_6C_H (REG_MHL_TMDS_BASE + 0xD9) 1449 #define REG_MHL_TMDS_6D_L (REG_MHL_TMDS_BASE + 0xDA) 1450 #define REG_MHL_TMDS_6D_H (REG_MHL_TMDS_BASE + 0xDB) 1451 #define REG_MHL_TMDS_6E_L (REG_MHL_TMDS_BASE + 0xDC) 1452 #define REG_MHL_TMDS_6E_H (REG_MHL_TMDS_BASE + 0xDD) 1453 #define REG_MHL_TMDS_6F_L (REG_MHL_TMDS_BASE + 0xDE) 1454 #define REG_MHL_TMDS_6F_H (REG_MHL_TMDS_BASE + 0xDF) 1455 #define REG_MHL_TMDS_70_L (REG_MHL_TMDS_BASE + 0xE0) 1456 #define REG_MHL_TMDS_70_H (REG_MHL_TMDS_BASE + 0xE1) 1457 #define REG_MHL_TMDS_71_L (REG_MHL_TMDS_BASE + 0xE2) 1458 #define REG_MHL_TMDS_71_H (REG_MHL_TMDS_BASE + 0xE3) 1459 #define REG_MHL_TMDS_72_L (REG_MHL_TMDS_BASE + 0xE4) 1460 #define REG_MHL_TMDS_72_H (REG_MHL_TMDS_BASE + 0xE5) 1461 #define REG_MHL_TMDS_73_L (REG_MHL_TMDS_BASE + 0xE6) 1462 #define REG_MHL_TMDS_73_H (REG_MHL_TMDS_BASE + 0xE7) 1463 #define REG_MHL_TMDS_74_L (REG_MHL_TMDS_BASE + 0xE8) 1464 #define REG_MHL_TMDS_74_H (REG_MHL_TMDS_BASE + 0xE9) 1465 #define REG_MHL_TMDS_75_L (REG_MHL_TMDS_BASE + 0xEA) 1466 #define REG_MHL_TMDS_75_H (REG_MHL_TMDS_BASE + 0xEB) 1467 #define REG_MHL_TMDS_76_L (REG_MHL_TMDS_BASE + 0xEC) 1468 #define REG_MHL_TMDS_76_H (REG_MHL_TMDS_BASE + 0xED) 1469 #define REG_MHL_TMDS_77_L (REG_MHL_TMDS_BASE + 0xEE) 1470 #define REG_MHL_TMDS_77_H (REG_MHL_TMDS_BASE + 0xEF) 1471 #define REG_MHL_TMDS_78_L (REG_MHL_TMDS_BASE + 0xF0) 1472 #define REG_MHL_TMDS_78_H (REG_MHL_TMDS_BASE + 0xF1) 1473 #define REG_MHL_TMDS_79_L (REG_MHL_TMDS_BASE + 0xF2) 1474 #define REG_MHL_TMDS_79_H (REG_MHL_TMDS_BASE + 0xF3) 1475 #define REG_MHL_TMDS_7A_L (REG_MHL_TMDS_BASE + 0xF4) 1476 #define REG_MHL_TMDS_7A_H (REG_MHL_TMDS_BASE + 0xF5) 1477 #define REG_MHL_TMDS_7B_L (REG_MHL_TMDS_BASE + 0xF6) 1478 #define REG_MHL_TMDS_7B_H (REG_MHL_TMDS_BASE + 0xF7) 1479 #define REG_MHL_TMDS_7C_L (REG_MHL_TMDS_BASE + 0xF8) 1480 #define REG_MHL_TMDS_7C_H (REG_MHL_TMDS_BASE + 0xF9) 1481 #define REG_MHL_TMDS_7D_L (REG_MHL_TMDS_BASE + 0xFA) 1482 #define REG_MHL_TMDS_7D_H (REG_MHL_TMDS_BASE + 0xFB) 1483 #define REG_MHL_TMDS_7E_L (REG_MHL_TMDS_BASE + 0xFC) 1484 #define REG_MHL_TMDS_7E_H (REG_MHL_TMDS_BASE + 0xFD) 1485 #define REG_MHL_TMDS_7F_L (REG_MHL_TMDS_BASE + 0xFE) 1486 #define REG_MHL_TMDS_7F_H (REG_MHL_TMDS_BASE + 0xFF) 1487 1488 //============================================================= 1489 1490 // CHIP 1491 #define REG_CHIP_05_L (REG_CHIP_BASE + 0x0A) 1492 1493 //CHIP_GPIO1 1494 #define REG_CHIP_GPIO1_10_L (REG_CHIP_GPIO1_BASE + 0x20) 1495 1496 // COMBO_PHY0_P0 1497 #define REG_COMBO_PHY0_P0_00_L (REG_COMBO_PHY0_P0_BASE + 0x00) 1498 #define REG_COMBO_PHY0_P0_00_H (REG_COMBO_PHY0_P0_BASE + 0x01) 1499 #define REG_COMBO_PHY0_P0_01_L (REG_COMBO_PHY0_P0_BASE + 0x02) 1500 #define REG_COMBO_PHY0_P0_01_H (REG_COMBO_PHY0_P0_BASE + 0x03) 1501 #define REG_COMBO_PHY0_P0_02_L (REG_COMBO_PHY0_P0_BASE + 0x04) 1502 #define REG_COMBO_PHY0_P0_02_H (REG_COMBO_PHY0_P0_BASE + 0x05) 1503 #define REG_COMBO_PHY0_P0_03_L (REG_COMBO_PHY0_P0_BASE + 0x06) 1504 #define REG_COMBO_PHY0_P0_03_H (REG_COMBO_PHY0_P0_BASE + 0x07) 1505 #define REG_COMBO_PHY0_P0_04_L (REG_COMBO_PHY0_P0_BASE + 0x08) 1506 #define REG_COMBO_PHY0_P0_04_H (REG_COMBO_PHY0_P0_BASE + 0x09) 1507 #define REG_COMBO_PHY0_P0_05_L (REG_COMBO_PHY0_P0_BASE + 0x0A) 1508 #define REG_COMBO_PHY0_P0_05_H (REG_COMBO_PHY0_P0_BASE + 0x0B) 1509 #define REG_COMBO_PHY0_P0_06_L (REG_COMBO_PHY0_P0_BASE + 0x0C) 1510 #define REG_COMBO_PHY0_P0_06_H (REG_COMBO_PHY0_P0_BASE + 0x0D) 1511 #define REG_COMBO_PHY0_P0_07_L (REG_COMBO_PHY0_P0_BASE + 0x0E) 1512 #define REG_COMBO_PHY0_P0_07_H (REG_COMBO_PHY0_P0_BASE + 0x0F) 1513 #define REG_COMBO_PHY0_P0_08_L (REG_COMBO_PHY0_P0_BASE + 0x10) 1514 #define REG_COMBO_PHY0_P0_08_H (REG_COMBO_PHY0_P0_BASE + 0x11) 1515 #define REG_COMBO_PHY0_P0_09_L (REG_COMBO_PHY0_P0_BASE + 0x12) 1516 #define REG_COMBO_PHY0_P0_09_H (REG_COMBO_PHY0_P0_BASE + 0x13) 1517 #define REG_COMBO_PHY0_P0_0A_L (REG_COMBO_PHY0_P0_BASE + 0x14) 1518 #define REG_COMBO_PHY0_P0_0A_H (REG_COMBO_PHY0_P0_BASE + 0x15) 1519 #define REG_COMBO_PHY0_P0_0B_L (REG_COMBO_PHY0_P0_BASE + 0x16) 1520 #define REG_COMBO_PHY0_P0_0B_H (REG_COMBO_PHY0_P0_BASE + 0x17) 1521 #define REG_COMBO_PHY0_P0_0C_L (REG_COMBO_PHY0_P0_BASE + 0x18) 1522 #define REG_COMBO_PHY0_P0_0C_H (REG_COMBO_PHY0_P0_BASE + 0x19) 1523 #define REG_COMBO_PHY0_P0_0D_L (REG_COMBO_PHY0_P0_BASE + 0x1A) 1524 #define REG_COMBO_PHY0_P0_0D_H (REG_COMBO_PHY0_P0_BASE + 0x1B) 1525 #define REG_COMBO_PHY0_P0_0E_L (REG_COMBO_PHY0_P0_BASE + 0x1C) 1526 #define REG_COMBO_PHY0_P0_0E_H (REG_COMBO_PHY0_P0_BASE + 0x1D) 1527 #define REG_COMBO_PHY0_P0_0F_L (REG_COMBO_PHY0_P0_BASE + 0x1E) 1528 #define REG_COMBO_PHY0_P0_0F_H (REG_COMBO_PHY0_P0_BASE + 0x1F) 1529 #define REG_COMBO_PHY0_P0_10_L (REG_COMBO_PHY0_P0_BASE + 0x20) 1530 #define REG_COMBO_PHY0_P0_10_H (REG_COMBO_PHY0_P0_BASE + 0x21) 1531 #define REG_COMBO_PHY0_P0_11_L (REG_COMBO_PHY0_P0_BASE + 0x22) 1532 #define REG_COMBO_PHY0_P0_11_H (REG_COMBO_PHY0_P0_BASE + 0x23) 1533 #define REG_COMBO_PHY0_P0_12_L (REG_COMBO_PHY0_P0_BASE + 0x24) 1534 #define REG_COMBO_PHY0_P0_12_H (REG_COMBO_PHY0_P0_BASE + 0x25) 1535 #define REG_COMBO_PHY0_P0_13_L (REG_COMBO_PHY0_P0_BASE + 0x26) 1536 #define REG_COMBO_PHY0_P0_13_H (REG_COMBO_PHY0_P0_BASE + 0x27) 1537 #define REG_COMBO_PHY0_P0_14_L (REG_COMBO_PHY0_P0_BASE + 0x28) 1538 #define REG_COMBO_PHY0_P0_14_H (REG_COMBO_PHY0_P0_BASE + 0x29) 1539 #define REG_COMBO_PHY0_P0_15_L (REG_COMBO_PHY0_P0_BASE + 0x2A) 1540 #define REG_COMBO_PHY0_P0_15_H (REG_COMBO_PHY0_P0_BASE + 0x2B) 1541 #define REG_COMBO_PHY0_P0_16_L (REG_COMBO_PHY0_P0_BASE + 0x2C) 1542 #define REG_COMBO_PHY0_P0_16_H (REG_COMBO_PHY0_P0_BASE + 0x2D) 1543 #define REG_COMBO_PHY0_P0_17_L (REG_COMBO_PHY0_P0_BASE + 0x2E) 1544 #define REG_COMBO_PHY0_P0_17_H (REG_COMBO_PHY0_P0_BASE + 0x2F) 1545 #define REG_COMBO_PHY0_P0_18_L (REG_COMBO_PHY0_P0_BASE + 0x30) 1546 #define REG_COMBO_PHY0_P0_18_H (REG_COMBO_PHY0_P0_BASE + 0x31) 1547 #define REG_COMBO_PHY0_P0_19_L (REG_COMBO_PHY0_P0_BASE + 0x32) 1548 #define REG_COMBO_PHY0_P0_19_H (REG_COMBO_PHY0_P0_BASE + 0x33) 1549 #define REG_COMBO_PHY0_P0_1A_L (REG_COMBO_PHY0_P0_BASE + 0x34) 1550 #define REG_COMBO_PHY0_P0_1A_H (REG_COMBO_PHY0_P0_BASE + 0x35) 1551 #define REG_COMBO_PHY0_P0_1B_L (REG_COMBO_PHY0_P0_BASE + 0x36) 1552 #define REG_COMBO_PHY0_P0_1B_H (REG_COMBO_PHY0_P0_BASE + 0x37) 1553 #define REG_COMBO_PHY0_P0_1C_L (REG_COMBO_PHY0_P0_BASE + 0x38) 1554 #define REG_COMBO_PHY0_P0_1C_H (REG_COMBO_PHY0_P0_BASE + 0x39) 1555 #define REG_COMBO_PHY0_P0_1D_L (REG_COMBO_PHY0_P0_BASE + 0x3A) 1556 #define REG_COMBO_PHY0_P0_1D_H (REG_COMBO_PHY0_P0_BASE + 0x3B) 1557 #define REG_COMBO_PHY0_P0_1E_L (REG_COMBO_PHY0_P0_BASE + 0x3C) 1558 #define REG_COMBO_PHY0_P0_1E_H (REG_COMBO_PHY0_P0_BASE + 0x3D) 1559 #define REG_COMBO_PHY0_P0_1F_L (REG_COMBO_PHY0_P0_BASE + 0x3E) 1560 #define REG_COMBO_PHY0_P0_1F_H (REG_COMBO_PHY0_P0_BASE + 0x3F) 1561 #define REG_COMBO_PHY0_P0_20_L (REG_COMBO_PHY0_P0_BASE + 0x40) 1562 #define REG_COMBO_PHY0_P0_20_H (REG_COMBO_PHY0_P0_BASE + 0x41) 1563 #define REG_COMBO_PHY0_P0_21_L (REG_COMBO_PHY0_P0_BASE + 0x42) 1564 #define REG_COMBO_PHY0_P0_21_H (REG_COMBO_PHY0_P0_BASE + 0x43) 1565 #define REG_COMBO_PHY0_P0_22_L (REG_COMBO_PHY0_P0_BASE + 0x44) 1566 #define REG_COMBO_PHY0_P0_22_H (REG_COMBO_PHY0_P0_BASE + 0x45) 1567 #define REG_COMBO_PHY0_P0_23_L (REG_COMBO_PHY0_P0_BASE + 0x46) 1568 #define REG_COMBO_PHY0_P0_23_H (REG_COMBO_PHY0_P0_BASE + 0x47) 1569 #define REG_COMBO_PHY0_P0_24_L (REG_COMBO_PHY0_P0_BASE + 0x48) 1570 #define REG_COMBO_PHY0_P0_24_H (REG_COMBO_PHY0_P0_BASE + 0x49) 1571 #define REG_COMBO_PHY0_P0_25_L (REG_COMBO_PHY0_P0_BASE + 0x4A) 1572 #define REG_COMBO_PHY0_P0_25_H (REG_COMBO_PHY0_P0_BASE + 0x4B) 1573 #define REG_COMBO_PHY0_P0_26_L (REG_COMBO_PHY0_P0_BASE + 0x4C) 1574 #define REG_COMBO_PHY0_P0_26_H (REG_COMBO_PHY0_P0_BASE + 0x4D) 1575 #define REG_COMBO_PHY0_P0_27_L (REG_COMBO_PHY0_P0_BASE + 0x4E) 1576 #define REG_COMBO_PHY0_P0_27_H (REG_COMBO_PHY0_P0_BASE + 0x4F) 1577 #define REG_COMBO_PHY0_P0_28_L (REG_COMBO_PHY0_P0_BASE + 0x50) 1578 #define REG_COMBO_PHY0_P0_28_H (REG_COMBO_PHY0_P0_BASE + 0x51) 1579 #define REG_COMBO_PHY0_P0_29_L (REG_COMBO_PHY0_P0_BASE + 0x52) 1580 #define REG_COMBO_PHY0_P0_29_H (REG_COMBO_PHY0_P0_BASE + 0x53) 1581 #define REG_COMBO_PHY0_P0_2A_L (REG_COMBO_PHY0_P0_BASE + 0x54) 1582 #define REG_COMBO_PHY0_P0_2A_H (REG_COMBO_PHY0_P0_BASE + 0x55) 1583 #define REG_COMBO_PHY0_P0_2B_L (REG_COMBO_PHY0_P0_BASE + 0x56) 1584 #define REG_COMBO_PHY0_P0_2B_H (REG_COMBO_PHY0_P0_BASE + 0x57) 1585 #define REG_COMBO_PHY0_P0_2C_L (REG_COMBO_PHY0_P0_BASE + 0x58) 1586 #define REG_COMBO_PHY0_P0_2C_H (REG_COMBO_PHY0_P0_BASE + 0x59) 1587 #define REG_COMBO_PHY0_P0_2D_L (REG_COMBO_PHY0_P0_BASE + 0x5A) 1588 #define REG_COMBO_PHY0_P0_2D_H (REG_COMBO_PHY0_P0_BASE + 0x5B) 1589 #define REG_COMBO_PHY0_P0_2E_L (REG_COMBO_PHY0_P0_BASE + 0x5C) 1590 #define REG_COMBO_PHY0_P0_2E_H (REG_COMBO_PHY0_P0_BASE + 0x5D) 1591 #define REG_COMBO_PHY0_P0_2F_L (REG_COMBO_PHY0_P0_BASE + 0x5E) 1592 #define REG_COMBO_PHY0_P0_2F_H (REG_COMBO_PHY0_P0_BASE + 0x5F) 1593 #define REG_COMBO_PHY0_P0_30_L (REG_COMBO_PHY0_P0_BASE + 0x60) 1594 #define REG_COMBO_PHY0_P0_30_H (REG_COMBO_PHY0_P0_BASE + 0x61) 1595 #define REG_COMBO_PHY0_P0_31_L (REG_COMBO_PHY0_P0_BASE + 0x62) 1596 #define REG_COMBO_PHY0_P0_31_H (REG_COMBO_PHY0_P0_BASE + 0x63) 1597 #define REG_COMBO_PHY0_P0_32_L (REG_COMBO_PHY0_P0_BASE + 0x64) 1598 #define REG_COMBO_PHY0_P0_32_H (REG_COMBO_PHY0_P0_BASE + 0x65) 1599 #define REG_COMBO_PHY0_P0_33_L (REG_COMBO_PHY0_P0_BASE + 0x66) 1600 #define REG_COMBO_PHY0_P0_33_H (REG_COMBO_PHY0_P0_BASE + 0x67) 1601 #define REG_COMBO_PHY0_P0_34_L (REG_COMBO_PHY0_P0_BASE + 0x68) 1602 #define REG_COMBO_PHY0_P0_34_H (REG_COMBO_PHY0_P0_BASE + 0x69) 1603 #define REG_COMBO_PHY0_P0_35_L (REG_COMBO_PHY0_P0_BASE + 0x6A) 1604 #define REG_COMBO_PHY0_P0_35_H (REG_COMBO_PHY0_P0_BASE + 0x6B) 1605 #define REG_COMBO_PHY0_P0_36_L (REG_COMBO_PHY0_P0_BASE + 0x6C) 1606 #define REG_COMBO_PHY0_P0_36_H (REG_COMBO_PHY0_P0_BASE + 0x6D) 1607 #define REG_COMBO_PHY0_P0_37_L (REG_COMBO_PHY0_P0_BASE + 0x6E) 1608 #define REG_COMBO_PHY0_P0_37_H (REG_COMBO_PHY0_P0_BASE + 0x6F) 1609 #define REG_COMBO_PHY0_P0_38_L (REG_COMBO_PHY0_P0_BASE + 0x70) 1610 #define REG_COMBO_PHY0_P0_38_H (REG_COMBO_PHY0_P0_BASE + 0x71) 1611 #define REG_COMBO_PHY0_P0_39_L (REG_COMBO_PHY0_P0_BASE + 0x72) 1612 #define REG_COMBO_PHY0_P0_39_H (REG_COMBO_PHY0_P0_BASE + 0x73) 1613 #define REG_COMBO_PHY0_P0_3A_L (REG_COMBO_PHY0_P0_BASE + 0x74) 1614 #define REG_COMBO_PHY0_P0_3A_H (REG_COMBO_PHY0_P0_BASE + 0x75) 1615 #define REG_COMBO_PHY0_P0_3B_L (REG_COMBO_PHY0_P0_BASE + 0x76) 1616 #define REG_COMBO_PHY0_P0_3B_H (REG_COMBO_PHY0_P0_BASE + 0x77) 1617 #define REG_COMBO_PHY0_P0_3C_L (REG_COMBO_PHY0_P0_BASE + 0x78) 1618 #define REG_COMBO_PHY0_P0_3C_H (REG_COMBO_PHY0_P0_BASE + 0x79) 1619 #define REG_COMBO_PHY0_P0_3D_L (REG_COMBO_PHY0_P0_BASE + 0x7A) 1620 #define REG_COMBO_PHY0_P0_3D_H (REG_COMBO_PHY0_P0_BASE + 0x7B) 1621 #define REG_COMBO_PHY0_P0_3E_L (REG_COMBO_PHY0_P0_BASE + 0x7C) 1622 #define REG_COMBO_PHY0_P0_3E_H (REG_COMBO_PHY0_P0_BASE + 0x7D) 1623 #define REG_COMBO_PHY0_P0_3F_L (REG_COMBO_PHY0_P0_BASE + 0x7E) 1624 #define REG_COMBO_PHY0_P0_3F_H (REG_COMBO_PHY0_P0_BASE + 0x7F) 1625 #define REG_COMBO_PHY0_P0_40_L (REG_COMBO_PHY0_P0_BASE + 0x80) 1626 #define REG_COMBO_PHY0_P0_40_H (REG_COMBO_PHY0_P0_BASE + 0x81) 1627 #define REG_COMBO_PHY0_P0_41_L (REG_COMBO_PHY0_P0_BASE + 0x82) 1628 #define REG_COMBO_PHY0_P0_41_H (REG_COMBO_PHY0_P0_BASE + 0x83) 1629 #define REG_COMBO_PHY0_P0_42_L (REG_COMBO_PHY0_P0_BASE + 0x84) 1630 #define REG_COMBO_PHY0_P0_42_H (REG_COMBO_PHY0_P0_BASE + 0x85) 1631 #define REG_COMBO_PHY0_P0_43_L (REG_COMBO_PHY0_P0_BASE + 0x86) 1632 #define REG_COMBO_PHY0_P0_43_H (REG_COMBO_PHY0_P0_BASE + 0x87) 1633 #define REG_COMBO_PHY0_P0_44_L (REG_COMBO_PHY0_P0_BASE + 0x88) 1634 #define REG_COMBO_PHY0_P0_44_H (REG_COMBO_PHY0_P0_BASE + 0x89) 1635 #define REG_COMBO_PHY0_P0_45_L (REG_COMBO_PHY0_P0_BASE + 0x8A) 1636 #define REG_COMBO_PHY0_P0_45_H (REG_COMBO_PHY0_P0_BASE + 0x8B) 1637 #define REG_COMBO_PHY0_P0_46_L (REG_COMBO_PHY0_P0_BASE + 0x8C) 1638 #define REG_COMBO_PHY0_P0_46_H (REG_COMBO_PHY0_P0_BASE + 0x8D) 1639 #define REG_COMBO_PHY0_P0_47_L (REG_COMBO_PHY0_P0_BASE + 0x8E) 1640 #define REG_COMBO_PHY0_P0_47_H (REG_COMBO_PHY0_P0_BASE + 0x8F) 1641 #define REG_COMBO_PHY0_P0_48_L (REG_COMBO_PHY0_P0_BASE + 0x90) 1642 #define REG_COMBO_PHY0_P0_48_H (REG_COMBO_PHY0_P0_BASE + 0x91) 1643 #define REG_COMBO_PHY0_P0_49_L (REG_COMBO_PHY0_P0_BASE + 0x92) 1644 #define REG_COMBO_PHY0_P0_49_H (REG_COMBO_PHY0_P0_BASE + 0x93) 1645 #define REG_COMBO_PHY0_P0_4A_L (REG_COMBO_PHY0_P0_BASE + 0x94) 1646 #define REG_COMBO_PHY0_P0_4A_H (REG_COMBO_PHY0_P0_BASE + 0x95) 1647 #define REG_COMBO_PHY0_P0_4B_L (REG_COMBO_PHY0_P0_BASE + 0x96) 1648 #define REG_COMBO_PHY0_P0_4B_H (REG_COMBO_PHY0_P0_BASE + 0x97) 1649 #define REG_COMBO_PHY0_P0_4C_L (REG_COMBO_PHY0_P0_BASE + 0x98) 1650 #define REG_COMBO_PHY0_P0_4C_H (REG_COMBO_PHY0_P0_BASE + 0x99) 1651 #define REG_COMBO_PHY0_P0_4D_L (REG_COMBO_PHY0_P0_BASE + 0x9A) 1652 #define REG_COMBO_PHY0_P0_4D_H (REG_COMBO_PHY0_P0_BASE + 0x9B) 1653 #define REG_COMBO_PHY0_P0_4E_L (REG_COMBO_PHY0_P0_BASE + 0x9C) 1654 #define REG_COMBO_PHY0_P0_4E_H (REG_COMBO_PHY0_P0_BASE + 0x9D) 1655 #define REG_COMBO_PHY0_P0_4F_L (REG_COMBO_PHY0_P0_BASE + 0x9E) 1656 #define REG_COMBO_PHY0_P0_4F_H (REG_COMBO_PHY0_P0_BASE + 0x9F) 1657 #define REG_COMBO_PHY0_P0_50_L (REG_COMBO_PHY0_P0_BASE + 0xA0) 1658 #define REG_COMBO_PHY0_P0_50_H (REG_COMBO_PHY0_P0_BASE + 0xA1) 1659 #define REG_COMBO_PHY0_P0_51_L (REG_COMBO_PHY0_P0_BASE + 0xA2) 1660 #define REG_COMBO_PHY0_P0_51_H (REG_COMBO_PHY0_P0_BASE + 0xA3) 1661 #define REG_COMBO_PHY0_P0_52_L (REG_COMBO_PHY0_P0_BASE + 0xA4) 1662 #define REG_COMBO_PHY0_P0_52_H (REG_COMBO_PHY0_P0_BASE + 0xA5) 1663 #define REG_COMBO_PHY0_P0_53_L (REG_COMBO_PHY0_P0_BASE + 0xA6) 1664 #define REG_COMBO_PHY0_P0_53_H (REG_COMBO_PHY0_P0_BASE + 0xA7) 1665 #define REG_COMBO_PHY0_P0_54_L (REG_COMBO_PHY0_P0_BASE + 0xA8) 1666 #define REG_COMBO_PHY0_P0_54_H (REG_COMBO_PHY0_P0_BASE + 0xA9) 1667 #define REG_COMBO_PHY0_P0_55_L (REG_COMBO_PHY0_P0_BASE + 0xAA) 1668 #define REG_COMBO_PHY0_P0_55_H (REG_COMBO_PHY0_P0_BASE + 0xAB) 1669 #define REG_COMBO_PHY0_P0_56_L (REG_COMBO_PHY0_P0_BASE + 0xAC) 1670 #define REG_COMBO_PHY0_P0_56_H (REG_COMBO_PHY0_P0_BASE + 0xAD) 1671 #define REG_COMBO_PHY0_P0_57_L (REG_COMBO_PHY0_P0_BASE + 0xAE) 1672 #define REG_COMBO_PHY0_P0_57_H (REG_COMBO_PHY0_P0_BASE + 0xAF) 1673 #define REG_COMBO_PHY0_P0_58_L (REG_COMBO_PHY0_P0_BASE + 0xB0) 1674 #define REG_COMBO_PHY0_P0_58_H (REG_COMBO_PHY0_P0_BASE + 0xB1) 1675 #define REG_COMBO_PHY0_P0_59_L (REG_COMBO_PHY0_P0_BASE + 0xB2) 1676 #define REG_COMBO_PHY0_P0_59_H (REG_COMBO_PHY0_P0_BASE + 0xB3) 1677 #define REG_COMBO_PHY0_P0_5A_L (REG_COMBO_PHY0_P0_BASE + 0xB4) 1678 #define REG_COMBO_PHY0_P0_5A_H (REG_COMBO_PHY0_P0_BASE + 0xB5) 1679 #define REG_COMBO_PHY0_P0_5B_L (REG_COMBO_PHY0_P0_BASE + 0xB6) 1680 #define REG_COMBO_PHY0_P0_5B_H (REG_COMBO_PHY0_P0_BASE + 0xB7) 1681 #define REG_COMBO_PHY0_P0_5C_L (REG_COMBO_PHY0_P0_BASE + 0xB8) 1682 #define REG_COMBO_PHY0_P0_5C_H (REG_COMBO_PHY0_P0_BASE + 0xB9) 1683 #define REG_COMBO_PHY0_P0_5D_L (REG_COMBO_PHY0_P0_BASE + 0xBA) 1684 #define REG_COMBO_PHY0_P0_5D_H (REG_COMBO_PHY0_P0_BASE + 0xBB) 1685 #define REG_COMBO_PHY0_P0_5E_L (REG_COMBO_PHY0_P0_BASE + 0xBC) 1686 #define REG_COMBO_PHY0_P0_5E_H (REG_COMBO_PHY0_P0_BASE + 0xBD) 1687 #define REG_COMBO_PHY0_P0_5F_L (REG_COMBO_PHY0_P0_BASE + 0xBE) 1688 #define REG_COMBO_PHY0_P0_5F_H (REG_COMBO_PHY0_P0_BASE + 0xBF) 1689 #define REG_COMBO_PHY0_P0_60_L (REG_COMBO_PHY0_P0_BASE + 0xC0) 1690 #define REG_COMBO_PHY0_P0_60_H (REG_COMBO_PHY0_P0_BASE + 0xC1) 1691 #define REG_COMBO_PHY0_P0_61_L (REG_COMBO_PHY0_P0_BASE + 0xC2) 1692 #define REG_COMBO_PHY0_P0_61_H (REG_COMBO_PHY0_P0_BASE + 0xC3) 1693 #define REG_COMBO_PHY0_P0_62_L (REG_COMBO_PHY0_P0_BASE + 0xC4) 1694 #define REG_COMBO_PHY0_P0_62_H (REG_COMBO_PHY0_P0_BASE + 0xC5) 1695 #define REG_COMBO_PHY0_P0_63_L (REG_COMBO_PHY0_P0_BASE + 0xC6) 1696 #define REG_COMBO_PHY0_P0_63_H (REG_COMBO_PHY0_P0_BASE + 0xC7) 1697 #define REG_COMBO_PHY0_P0_64_L (REG_COMBO_PHY0_P0_BASE + 0xC8) 1698 #define REG_COMBO_PHY0_P0_64_H (REG_COMBO_PHY0_P0_BASE + 0xC9) 1699 #define REG_COMBO_PHY0_P0_65_L (REG_COMBO_PHY0_P0_BASE + 0xCA) 1700 #define REG_COMBO_PHY0_P0_65_H (REG_COMBO_PHY0_P0_BASE + 0xCB) 1701 #define REG_COMBO_PHY0_P0_66_L (REG_COMBO_PHY0_P0_BASE + 0xCC) 1702 #define REG_COMBO_PHY0_P0_66_H (REG_COMBO_PHY0_P0_BASE + 0xCD) 1703 #define REG_COMBO_PHY0_P0_67_L (REG_COMBO_PHY0_P0_BASE + 0xCE) 1704 #define REG_COMBO_PHY0_P0_67_H (REG_COMBO_PHY0_P0_BASE + 0xCF) 1705 #define REG_COMBO_PHY0_P0_68_L (REG_COMBO_PHY0_P0_BASE + 0xD0) 1706 #define REG_COMBO_PHY0_P0_68_H (REG_COMBO_PHY0_P0_BASE + 0xD1) 1707 #define REG_COMBO_PHY0_P0_69_L (REG_COMBO_PHY0_P0_BASE + 0xD2) 1708 #define REG_COMBO_PHY0_P0_69_H (REG_COMBO_PHY0_P0_BASE + 0xD3) 1709 #define REG_COMBO_PHY0_P0_6A_L (REG_COMBO_PHY0_P0_BASE + 0xD4) 1710 #define REG_COMBO_PHY0_P0_6A_H (REG_COMBO_PHY0_P0_BASE + 0xD5) 1711 #define REG_COMBO_PHY0_P0_6B_L (REG_COMBO_PHY0_P0_BASE + 0xD6) 1712 #define REG_COMBO_PHY0_P0_6B_H (REG_COMBO_PHY0_P0_BASE + 0xD7) 1713 #define REG_COMBO_PHY0_P0_6C_L (REG_COMBO_PHY0_P0_BASE + 0xD8) 1714 #define REG_COMBO_PHY0_P0_6C_H (REG_COMBO_PHY0_P0_BASE + 0xD9) 1715 #define REG_COMBO_PHY0_P0_6D_L (REG_COMBO_PHY0_P0_BASE + 0xDA) 1716 #define REG_COMBO_PHY0_P0_6D_H (REG_COMBO_PHY0_P0_BASE + 0xDB) 1717 #define REG_COMBO_PHY0_P0_6E_L (REG_COMBO_PHY0_P0_BASE + 0xDC) 1718 #define REG_COMBO_PHY0_P0_6E_H (REG_COMBO_PHY0_P0_BASE + 0xDD) 1719 #define REG_COMBO_PHY0_P0_6F_L (REG_COMBO_PHY0_P0_BASE + 0xDE) 1720 #define REG_COMBO_PHY0_P0_6F_H (REG_COMBO_PHY0_P0_BASE + 0xDF) 1721 #define REG_COMBO_PHY0_P0_70_L (REG_COMBO_PHY0_P0_BASE + 0xE0) 1722 #define REG_COMBO_PHY0_P0_70_H (REG_COMBO_PHY0_P0_BASE + 0xE1) 1723 #define REG_COMBO_PHY0_P0_71_L (REG_COMBO_PHY0_P0_BASE + 0xE2) 1724 #define REG_COMBO_PHY0_P0_71_H (REG_COMBO_PHY0_P0_BASE + 0xE3) 1725 #define REG_COMBO_PHY0_P0_72_L (REG_COMBO_PHY0_P0_BASE + 0xE4) 1726 #define REG_COMBO_PHY0_P0_72_H (REG_COMBO_PHY0_P0_BASE + 0xE5) 1727 #define REG_COMBO_PHY0_P0_73_L (REG_COMBO_PHY0_P0_BASE + 0xE6) 1728 #define REG_COMBO_PHY0_P0_73_H (REG_COMBO_PHY0_P0_BASE + 0xE7) 1729 #define REG_COMBO_PHY0_P0_74_L (REG_COMBO_PHY0_P0_BASE + 0xE8) 1730 #define REG_COMBO_PHY0_P0_74_H (REG_COMBO_PHY0_P0_BASE + 0xE9) 1731 #define REG_COMBO_PHY0_P0_75_L (REG_COMBO_PHY0_P0_BASE + 0xEA) 1732 #define REG_COMBO_PHY0_P0_75_H (REG_COMBO_PHY0_P0_BASE + 0xEB) 1733 #define REG_COMBO_PHY0_P0_76_L (REG_COMBO_PHY0_P0_BASE + 0xEC) 1734 #define REG_COMBO_PHY0_P0_76_H (REG_COMBO_PHY0_P0_BASE + 0xED) 1735 #define REG_COMBO_PHY0_P0_77_L (REG_COMBO_PHY0_P0_BASE + 0xEE) 1736 #define REG_COMBO_PHY0_P0_77_H (REG_COMBO_PHY0_P0_BASE + 0xEF) 1737 #define REG_COMBO_PHY0_P0_78_L (REG_COMBO_PHY0_P0_BASE + 0xF0) 1738 #define REG_COMBO_PHY0_P0_78_H (REG_COMBO_PHY0_P0_BASE + 0xF1) 1739 #define REG_COMBO_PHY0_P0_79_L (REG_COMBO_PHY0_P0_BASE + 0xF2) 1740 #define REG_COMBO_PHY0_P0_79_H (REG_COMBO_PHY0_P0_BASE + 0xF3) 1741 #define REG_COMBO_PHY0_P0_7A_L (REG_COMBO_PHY0_P0_BASE + 0xF4) 1742 #define REG_COMBO_PHY0_P0_7A_H (REG_COMBO_PHY0_P0_BASE + 0xF5) 1743 #define REG_COMBO_PHY0_P0_7B_L (REG_COMBO_PHY0_P0_BASE + 0xF6) 1744 #define REG_COMBO_PHY0_P0_7B_H (REG_COMBO_PHY0_P0_BASE + 0xF7) 1745 #define REG_COMBO_PHY0_P0_7C_L (REG_COMBO_PHY0_P0_BASE + 0xF8) 1746 #define REG_COMBO_PHY0_P0_7C_H (REG_COMBO_PHY0_P0_BASE + 0xF9) 1747 #define REG_COMBO_PHY0_P0_7D_L (REG_COMBO_PHY0_P0_BASE + 0xFA) 1748 #define REG_COMBO_PHY0_P0_7D_H (REG_COMBO_PHY0_P0_BASE + 0xFB) 1749 #define REG_COMBO_PHY0_P0_7E_L (REG_COMBO_PHY0_P0_BASE + 0xFC) 1750 #define REG_COMBO_PHY0_P0_7E_H (REG_COMBO_PHY0_P0_BASE + 0xFD) 1751 #define REG_COMBO_PHY0_P0_7F_L (REG_COMBO_PHY0_P0_BASE + 0xFE) 1752 #define REG_COMBO_PHY0_P0_7F_H (REG_COMBO_PHY0_P0_BASE + 0xFF) 1753 1754 // COMBO_PHY1_P0 1755 #define REG_COMBO_PHY1_P0_00_L (REG_COMBO_PHY1_P0_BASE + 0x00) 1756 #define REG_COMBO_PHY1_P0_00_H (REG_COMBO_PHY1_P0_BASE + 0x01) 1757 #define REG_COMBO_PHY1_P0_01_L (REG_COMBO_PHY1_P0_BASE + 0x02) 1758 #define REG_COMBO_PHY1_P0_01_H (REG_COMBO_PHY1_P0_BASE + 0x03) 1759 #define REG_COMBO_PHY1_P0_02_L (REG_COMBO_PHY1_P0_BASE + 0x04) 1760 #define REG_COMBO_PHY1_P0_02_H (REG_COMBO_PHY1_P0_BASE + 0x05) 1761 #define REG_COMBO_PHY1_P0_03_L (REG_COMBO_PHY1_P0_BASE + 0x06) 1762 #define REG_COMBO_PHY1_P0_03_H (REG_COMBO_PHY1_P0_BASE + 0x07) 1763 #define REG_COMBO_PHY1_P0_04_L (REG_COMBO_PHY1_P0_BASE + 0x08) 1764 #define REG_COMBO_PHY1_P0_04_H (REG_COMBO_PHY1_P0_BASE + 0x09) 1765 #define REG_COMBO_PHY1_P0_05_L (REG_COMBO_PHY1_P0_BASE + 0x0A) 1766 #define REG_COMBO_PHY1_P0_05_H (REG_COMBO_PHY1_P0_BASE + 0x0B) 1767 #define REG_COMBO_PHY1_P0_06_L (REG_COMBO_PHY1_P0_BASE + 0x0C) 1768 #define REG_COMBO_PHY1_P0_06_H (REG_COMBO_PHY1_P0_BASE + 0x0D) 1769 #define REG_COMBO_PHY1_P0_07_L (REG_COMBO_PHY1_P0_BASE + 0x0E) 1770 #define REG_COMBO_PHY1_P0_07_H (REG_COMBO_PHY1_P0_BASE + 0x0F) 1771 #define REG_COMBO_PHY1_P0_08_L (REG_COMBO_PHY1_P0_BASE + 0x10) 1772 #define REG_COMBO_PHY1_P0_08_H (REG_COMBO_PHY1_P0_BASE + 0x11) 1773 #define REG_COMBO_PHY1_P0_09_L (REG_COMBO_PHY1_P0_BASE + 0x12) 1774 #define REG_COMBO_PHY1_P0_09_H (REG_COMBO_PHY1_P0_BASE + 0x13) 1775 #define REG_COMBO_PHY1_P0_0A_L (REG_COMBO_PHY1_P0_BASE + 0x14) 1776 #define REG_COMBO_PHY1_P0_0A_H (REG_COMBO_PHY1_P0_BASE + 0x15) 1777 #define REG_COMBO_PHY1_P0_0B_L (REG_COMBO_PHY1_P0_BASE + 0x16) 1778 #define REG_COMBO_PHY1_P0_0B_H (REG_COMBO_PHY1_P0_BASE + 0x17) 1779 #define REG_COMBO_PHY1_P0_0C_L (REG_COMBO_PHY1_P0_BASE + 0x18) 1780 #define REG_COMBO_PHY1_P0_0C_H (REG_COMBO_PHY1_P0_BASE + 0x19) 1781 #define REG_COMBO_PHY1_P0_0D_L (REG_COMBO_PHY1_P0_BASE + 0x1A) 1782 #define REG_COMBO_PHY1_P0_0D_H (REG_COMBO_PHY1_P0_BASE + 0x1B) 1783 #define REG_COMBO_PHY1_P0_0E_L (REG_COMBO_PHY1_P0_BASE + 0x1C) 1784 #define REG_COMBO_PHY1_P0_0E_H (REG_COMBO_PHY1_P0_BASE + 0x1D) 1785 #define REG_COMBO_PHY1_P0_0F_L (REG_COMBO_PHY1_P0_BASE + 0x1E) 1786 #define REG_COMBO_PHY1_P0_0F_H (REG_COMBO_PHY1_P0_BASE + 0x1F) 1787 #define REG_COMBO_PHY1_P0_10_L (REG_COMBO_PHY1_P0_BASE + 0x20) 1788 #define REG_COMBO_PHY1_P0_10_H (REG_COMBO_PHY1_P0_BASE + 0x21) 1789 #define REG_COMBO_PHY1_P0_11_L (REG_COMBO_PHY1_P0_BASE + 0x22) 1790 #define REG_COMBO_PHY1_P0_11_H (REG_COMBO_PHY1_P0_BASE + 0x23) 1791 #define REG_COMBO_PHY1_P0_12_L (REG_COMBO_PHY1_P0_BASE + 0x24) 1792 #define REG_COMBO_PHY1_P0_12_H (REG_COMBO_PHY1_P0_BASE + 0x25) 1793 #define REG_COMBO_PHY1_P0_13_L (REG_COMBO_PHY1_P0_BASE + 0x26) 1794 #define REG_COMBO_PHY1_P0_13_H (REG_COMBO_PHY1_P0_BASE + 0x27) 1795 #define REG_COMBO_PHY1_P0_14_L (REG_COMBO_PHY1_P0_BASE + 0x28) 1796 #define REG_COMBO_PHY1_P0_14_H (REG_COMBO_PHY1_P0_BASE + 0x29) 1797 #define REG_COMBO_PHY1_P0_15_L (REG_COMBO_PHY1_P0_BASE + 0x2A) 1798 #define REG_COMBO_PHY1_P0_15_H (REG_COMBO_PHY1_P0_BASE + 0x2B) 1799 #define REG_COMBO_PHY1_P0_16_L (REG_COMBO_PHY1_P0_BASE + 0x2C) 1800 #define REG_COMBO_PHY1_P0_16_H (REG_COMBO_PHY1_P0_BASE + 0x2D) 1801 #define REG_COMBO_PHY1_P0_17_L (REG_COMBO_PHY1_P0_BASE + 0x2E) 1802 #define REG_COMBO_PHY1_P0_17_H (REG_COMBO_PHY1_P0_BASE + 0x2F) 1803 #define REG_COMBO_PHY1_P0_18_L (REG_COMBO_PHY1_P0_BASE + 0x30) 1804 #define REG_COMBO_PHY1_P0_18_H (REG_COMBO_PHY1_P0_BASE + 0x31) 1805 #define REG_COMBO_PHY1_P0_19_L (REG_COMBO_PHY1_P0_BASE + 0x32) 1806 #define REG_COMBO_PHY1_P0_19_H (REG_COMBO_PHY1_P0_BASE + 0x33) 1807 #define REG_COMBO_PHY1_P0_1A_L (REG_COMBO_PHY1_P0_BASE + 0x34) 1808 #define REG_COMBO_PHY1_P0_1A_H (REG_COMBO_PHY1_P0_BASE + 0x35) 1809 #define REG_COMBO_PHY1_P0_1B_L (REG_COMBO_PHY1_P0_BASE + 0x36) 1810 #define REG_COMBO_PHY1_P0_1B_H (REG_COMBO_PHY1_P0_BASE + 0x37) 1811 #define REG_COMBO_PHY1_P0_1C_L (REG_COMBO_PHY1_P0_BASE + 0x38) 1812 #define REG_COMBO_PHY1_P0_1C_H (REG_COMBO_PHY1_P0_BASE + 0x39) 1813 #define REG_COMBO_PHY1_P0_1D_L (REG_COMBO_PHY1_P0_BASE + 0x3A) 1814 #define REG_COMBO_PHY1_P0_1D_H (REG_COMBO_PHY1_P0_BASE + 0x3B) 1815 #define REG_COMBO_PHY1_P0_1E_L (REG_COMBO_PHY1_P0_BASE + 0x3C) 1816 #define REG_COMBO_PHY1_P0_1E_H (REG_COMBO_PHY1_P0_BASE + 0x3D) 1817 #define REG_COMBO_PHY1_P0_1F_L (REG_COMBO_PHY1_P0_BASE + 0x3E) 1818 #define REG_COMBO_PHY1_P0_1F_H (REG_COMBO_PHY1_P0_BASE + 0x3F) 1819 #define REG_COMBO_PHY1_P0_20_L (REG_COMBO_PHY1_P0_BASE + 0x40) 1820 #define REG_COMBO_PHY1_P0_20_H (REG_COMBO_PHY1_P0_BASE + 0x41) 1821 #define REG_COMBO_PHY1_P0_21_L (REG_COMBO_PHY1_P0_BASE + 0x42) 1822 #define REG_COMBO_PHY1_P0_21_H (REG_COMBO_PHY1_P0_BASE + 0x43) 1823 #define REG_COMBO_PHY1_P0_22_L (REG_COMBO_PHY1_P0_BASE + 0x44) 1824 #define REG_COMBO_PHY1_P0_22_H (REG_COMBO_PHY1_P0_BASE + 0x45) 1825 #define REG_COMBO_PHY1_P0_23_L (REG_COMBO_PHY1_P0_BASE + 0x46) 1826 #define REG_COMBO_PHY1_P0_23_H (REG_COMBO_PHY1_P0_BASE + 0x47) 1827 #define REG_COMBO_PHY1_P0_24_L (REG_COMBO_PHY1_P0_BASE + 0x48) 1828 #define REG_COMBO_PHY1_P0_24_H (REG_COMBO_PHY1_P0_BASE + 0x49) 1829 #define REG_COMBO_PHY1_P0_25_L (REG_COMBO_PHY1_P0_BASE + 0x4A) 1830 #define REG_COMBO_PHY1_P0_25_H (REG_COMBO_PHY1_P0_BASE + 0x4B) 1831 #define REG_COMBO_PHY1_P0_26_L (REG_COMBO_PHY1_P0_BASE + 0x4C) 1832 #define REG_COMBO_PHY1_P0_26_H (REG_COMBO_PHY1_P0_BASE + 0x4D) 1833 #define REG_COMBO_PHY1_P0_27_L (REG_COMBO_PHY1_P0_BASE + 0x4E) 1834 #define REG_COMBO_PHY1_P0_27_H (REG_COMBO_PHY1_P0_BASE + 0x4F) 1835 #define REG_COMBO_PHY1_P0_28_L (REG_COMBO_PHY1_P0_BASE + 0x50) 1836 #define REG_COMBO_PHY1_P0_28_H (REG_COMBO_PHY1_P0_BASE + 0x51) 1837 #define REG_COMBO_PHY1_P0_29_L (REG_COMBO_PHY1_P0_BASE + 0x52) 1838 #define REG_COMBO_PHY1_P0_29_H (REG_COMBO_PHY1_P0_BASE + 0x53) 1839 #define REG_COMBO_PHY1_P0_2A_L (REG_COMBO_PHY1_P0_BASE + 0x54) 1840 #define REG_COMBO_PHY1_P0_2A_H (REG_COMBO_PHY1_P0_BASE + 0x55) 1841 #define REG_COMBO_PHY1_P0_2B_L (REG_COMBO_PHY1_P0_BASE + 0x56) 1842 #define REG_COMBO_PHY1_P0_2B_H (REG_COMBO_PHY1_P0_BASE + 0x57) 1843 #define REG_COMBO_PHY1_P0_2C_L (REG_COMBO_PHY1_P0_BASE + 0x58) 1844 #define REG_COMBO_PHY1_P0_2C_H (REG_COMBO_PHY1_P0_BASE + 0x59) 1845 #define REG_COMBO_PHY1_P0_2D_L (REG_COMBO_PHY1_P0_BASE + 0x5A) 1846 #define REG_COMBO_PHY1_P0_2D_H (REG_COMBO_PHY1_P0_BASE + 0x5B) 1847 #define REG_COMBO_PHY1_P0_2E_L (REG_COMBO_PHY1_P0_BASE + 0x5C) 1848 #define REG_COMBO_PHY1_P0_2E_H (REG_COMBO_PHY1_P0_BASE + 0x5D) 1849 #define REG_COMBO_PHY1_P0_2F_L (REG_COMBO_PHY1_P0_BASE + 0x5E) 1850 #define REG_COMBO_PHY1_P0_2F_H (REG_COMBO_PHY1_P0_BASE + 0x5F) 1851 #define REG_COMBO_PHY1_P0_30_L (REG_COMBO_PHY1_P0_BASE + 0x60) 1852 #define REG_COMBO_PHY1_P0_30_H (REG_COMBO_PHY1_P0_BASE + 0x61) 1853 #define REG_COMBO_PHY1_P0_31_L (REG_COMBO_PHY1_P0_BASE + 0x62) 1854 #define REG_COMBO_PHY1_P0_31_H (REG_COMBO_PHY1_P0_BASE + 0x63) 1855 #define REG_COMBO_PHY1_P0_32_L (REG_COMBO_PHY1_P0_BASE + 0x64) 1856 #define REG_COMBO_PHY1_P0_32_H (REG_COMBO_PHY1_P0_BASE + 0x65) 1857 #define REG_COMBO_PHY1_P0_33_L (REG_COMBO_PHY1_P0_BASE + 0x66) 1858 #define REG_COMBO_PHY1_P0_33_H (REG_COMBO_PHY1_P0_BASE + 0x67) 1859 #define REG_COMBO_PHY1_P0_34_L (REG_COMBO_PHY1_P0_BASE + 0x68) 1860 #define REG_COMBO_PHY1_P0_34_H (REG_COMBO_PHY1_P0_BASE + 0x69) 1861 #define REG_COMBO_PHY1_P0_35_L (REG_COMBO_PHY1_P0_BASE + 0x6A) 1862 #define REG_COMBO_PHY1_P0_35_H (REG_COMBO_PHY1_P0_BASE + 0x6B) 1863 #define REG_COMBO_PHY1_P0_36_L (REG_COMBO_PHY1_P0_BASE + 0x6C) 1864 #define REG_COMBO_PHY1_P0_36_H (REG_COMBO_PHY1_P0_BASE + 0x6D) 1865 #define REG_COMBO_PHY1_P0_37_L (REG_COMBO_PHY1_P0_BASE + 0x6E) 1866 #define REG_COMBO_PHY1_P0_37_H (REG_COMBO_PHY1_P0_BASE + 0x6F) 1867 #define REG_COMBO_PHY1_P0_38_L (REG_COMBO_PHY1_P0_BASE + 0x70) 1868 #define REG_COMBO_PHY1_P0_38_H (REG_COMBO_PHY1_P0_BASE + 0x71) 1869 #define REG_COMBO_PHY1_P0_39_L (REG_COMBO_PHY1_P0_BASE + 0x72) 1870 #define REG_COMBO_PHY1_P0_39_H (REG_COMBO_PHY1_P0_BASE + 0x73) 1871 #define REG_COMBO_PHY1_P0_3A_L (REG_COMBO_PHY1_P0_BASE + 0x74) 1872 #define REG_COMBO_PHY1_P0_3A_H (REG_COMBO_PHY1_P0_BASE + 0x75) 1873 #define REG_COMBO_PHY1_P0_3B_L (REG_COMBO_PHY1_P0_BASE + 0x76) 1874 #define REG_COMBO_PHY1_P0_3B_H (REG_COMBO_PHY1_P0_BASE + 0x77) 1875 #define REG_COMBO_PHY1_P0_3C_L (REG_COMBO_PHY1_P0_BASE + 0x78) 1876 #define REG_COMBO_PHY1_P0_3C_H (REG_COMBO_PHY1_P0_BASE + 0x79) 1877 #define REG_COMBO_PHY1_P0_3D_L (REG_COMBO_PHY1_P0_BASE + 0x7A) 1878 #define REG_COMBO_PHY1_P0_3D_H (REG_COMBO_PHY1_P0_BASE + 0x7B) 1879 #define REG_COMBO_PHY1_P0_3E_L (REG_COMBO_PHY1_P0_BASE + 0x7C) 1880 #define REG_COMBO_PHY1_P0_3E_H (REG_COMBO_PHY1_P0_BASE + 0x7D) 1881 #define REG_COMBO_PHY1_P0_3F_L (REG_COMBO_PHY1_P0_BASE + 0x7E) 1882 #define REG_COMBO_PHY1_P0_3F_H (REG_COMBO_PHY1_P0_BASE + 0x7F) 1883 #define REG_COMBO_PHY1_P0_40_L (REG_COMBO_PHY1_P0_BASE + 0x80) 1884 #define REG_COMBO_PHY1_P0_40_H (REG_COMBO_PHY1_P0_BASE + 0x81) 1885 #define REG_COMBO_PHY1_P0_41_L (REG_COMBO_PHY1_P0_BASE + 0x82) 1886 #define REG_COMBO_PHY1_P0_41_H (REG_COMBO_PHY1_P0_BASE + 0x83) 1887 #define REG_COMBO_PHY1_P0_42_L (REG_COMBO_PHY1_P0_BASE + 0x84) 1888 #define REG_COMBO_PHY1_P0_42_H (REG_COMBO_PHY1_P0_BASE + 0x85) 1889 #define REG_COMBO_PHY1_P0_43_L (REG_COMBO_PHY1_P0_BASE + 0x86) 1890 #define REG_COMBO_PHY1_P0_43_H (REG_COMBO_PHY1_P0_BASE + 0x87) 1891 #define REG_COMBO_PHY1_P0_44_L (REG_COMBO_PHY1_P0_BASE + 0x88) 1892 #define REG_COMBO_PHY1_P0_44_H (REG_COMBO_PHY1_P0_BASE + 0x89) 1893 #define REG_COMBO_PHY1_P0_45_L (REG_COMBO_PHY1_P0_BASE + 0x8A) 1894 #define REG_COMBO_PHY1_P0_45_H (REG_COMBO_PHY1_P0_BASE + 0x8B) 1895 #define REG_COMBO_PHY1_P0_46_L (REG_COMBO_PHY1_P0_BASE + 0x8C) 1896 #define REG_COMBO_PHY1_P0_46_H (REG_COMBO_PHY1_P0_BASE + 0x8D) 1897 #define REG_COMBO_PHY1_P0_47_L (REG_COMBO_PHY1_P0_BASE + 0x8E) 1898 #define REG_COMBO_PHY1_P0_47_H (REG_COMBO_PHY1_P0_BASE + 0x8F) 1899 #define REG_COMBO_PHY1_P0_48_L (REG_COMBO_PHY1_P0_BASE + 0x90) 1900 #define REG_COMBO_PHY1_P0_48_H (REG_COMBO_PHY1_P0_BASE + 0x91) 1901 #define REG_COMBO_PHY1_P0_49_L (REG_COMBO_PHY1_P0_BASE + 0x92) 1902 #define REG_COMBO_PHY1_P0_49_H (REG_COMBO_PHY1_P0_BASE + 0x93) 1903 #define REG_COMBO_PHY1_P0_4A_L (REG_COMBO_PHY1_P0_BASE + 0x94) 1904 #define REG_COMBO_PHY1_P0_4A_H (REG_COMBO_PHY1_P0_BASE + 0x95) 1905 #define REG_COMBO_PHY1_P0_4B_L (REG_COMBO_PHY1_P0_BASE + 0x96) 1906 #define REG_COMBO_PHY1_P0_4B_H (REG_COMBO_PHY1_P0_BASE + 0x97) 1907 #define REG_COMBO_PHY1_P0_4C_L (REG_COMBO_PHY1_P0_BASE + 0x98) 1908 #define REG_COMBO_PHY1_P0_4C_H (REG_COMBO_PHY1_P0_BASE + 0x99) 1909 #define REG_COMBO_PHY1_P0_4D_L (REG_COMBO_PHY1_P0_BASE + 0x9A) 1910 #define REG_COMBO_PHY1_P0_4D_H (REG_COMBO_PHY1_P0_BASE + 0x9B) 1911 #define REG_COMBO_PHY1_P0_4E_L (REG_COMBO_PHY1_P0_BASE + 0x9C) 1912 #define REG_COMBO_PHY1_P0_4E_H (REG_COMBO_PHY1_P0_BASE + 0x9D) 1913 #define REG_COMBO_PHY1_P0_4F_L (REG_COMBO_PHY1_P0_BASE + 0x9E) 1914 #define REG_COMBO_PHY1_P0_4F_H (REG_COMBO_PHY1_P0_BASE + 0x9F) 1915 #define REG_COMBO_PHY1_P0_50_L (REG_COMBO_PHY1_P0_BASE + 0xA0) 1916 #define REG_COMBO_PHY1_P0_50_H (REG_COMBO_PHY1_P0_BASE + 0xA1) 1917 #define REG_COMBO_PHY1_P0_51_L (REG_COMBO_PHY1_P0_BASE + 0xA2) 1918 #define REG_COMBO_PHY1_P0_51_H (REG_COMBO_PHY1_P0_BASE + 0xA3) 1919 #define REG_COMBO_PHY1_P0_52_L (REG_COMBO_PHY1_P0_BASE + 0xA4) 1920 #define REG_COMBO_PHY1_P0_52_H (REG_COMBO_PHY1_P0_BASE + 0xA5) 1921 #define REG_COMBO_PHY1_P0_53_L (REG_COMBO_PHY1_P0_BASE + 0xA6) 1922 #define REG_COMBO_PHY1_P0_53_H (REG_COMBO_PHY1_P0_BASE + 0xA7) 1923 #define REG_COMBO_PHY1_P0_54_L (REG_COMBO_PHY1_P0_BASE + 0xA8) 1924 #define REG_COMBO_PHY1_P0_54_H (REG_COMBO_PHY1_P0_BASE + 0xA9) 1925 #define REG_COMBO_PHY1_P0_55_L (REG_COMBO_PHY1_P0_BASE + 0xAA) 1926 #define REG_COMBO_PHY1_P0_55_H (REG_COMBO_PHY1_P0_BASE + 0xAB) 1927 #define REG_COMBO_PHY1_P0_56_L (REG_COMBO_PHY1_P0_BASE + 0xAC) 1928 #define REG_COMBO_PHY1_P0_56_H (REG_COMBO_PHY1_P0_BASE + 0xAD) 1929 #define REG_COMBO_PHY1_P0_57_L (REG_COMBO_PHY1_P0_BASE + 0xAE) 1930 #define REG_COMBO_PHY1_P0_57_H (REG_COMBO_PHY1_P0_BASE + 0xAF) 1931 #define REG_COMBO_PHY1_P0_58_L (REG_COMBO_PHY1_P0_BASE + 0xB0) 1932 #define REG_COMBO_PHY1_P0_58_H (REG_COMBO_PHY1_P0_BASE + 0xB1) 1933 #define REG_COMBO_PHY1_P0_59_L (REG_COMBO_PHY1_P0_BASE + 0xB2) 1934 #define REG_COMBO_PHY1_P0_59_H (REG_COMBO_PHY1_P0_BASE + 0xB3) 1935 #define REG_COMBO_PHY1_P0_5A_L (REG_COMBO_PHY1_P0_BASE + 0xB4) 1936 #define REG_COMBO_PHY1_P0_5A_H (REG_COMBO_PHY1_P0_BASE + 0xB5) 1937 #define REG_COMBO_PHY1_P0_5B_L (REG_COMBO_PHY1_P0_BASE + 0xB6) 1938 #define REG_COMBO_PHY1_P0_5B_H (REG_COMBO_PHY1_P0_BASE + 0xB7) 1939 #define REG_COMBO_PHY1_P0_5C_L (REG_COMBO_PHY1_P0_BASE + 0xB8) 1940 #define REG_COMBO_PHY1_P0_5C_H (REG_COMBO_PHY1_P0_BASE + 0xB9) 1941 #define REG_COMBO_PHY1_P0_5D_L (REG_COMBO_PHY1_P0_BASE + 0xBA) 1942 #define REG_COMBO_PHY1_P0_5D_H (REG_COMBO_PHY1_P0_BASE + 0xBB) 1943 #define REG_COMBO_PHY1_P0_5E_L (REG_COMBO_PHY1_P0_BASE + 0xBC) 1944 #define REG_COMBO_PHY1_P0_5E_H (REG_COMBO_PHY1_P0_BASE + 0xBD) 1945 #define REG_COMBO_PHY1_P0_5F_L (REG_COMBO_PHY1_P0_BASE + 0xBE) 1946 #define REG_COMBO_PHY1_P0_5F_H (REG_COMBO_PHY1_P0_BASE + 0xBF) 1947 #define REG_COMBO_PHY1_P0_60_L (REG_COMBO_PHY1_P0_BASE + 0xC0) 1948 #define REG_COMBO_PHY1_P0_60_H (REG_COMBO_PHY1_P0_BASE + 0xC1) 1949 #define REG_COMBO_PHY1_P0_61_L (REG_COMBO_PHY1_P0_BASE + 0xC2) 1950 #define REG_COMBO_PHY1_P0_61_H (REG_COMBO_PHY1_P0_BASE + 0xC3) 1951 #define REG_COMBO_PHY1_P0_62_L (REG_COMBO_PHY1_P0_BASE + 0xC4) 1952 #define REG_COMBO_PHY1_P0_62_H (REG_COMBO_PHY1_P0_BASE + 0xC5) 1953 #define REG_COMBO_PHY1_P0_63_L (REG_COMBO_PHY1_P0_BASE + 0xC6) 1954 #define REG_COMBO_PHY1_P0_63_H (REG_COMBO_PHY1_P0_BASE + 0xC7) 1955 #define REG_COMBO_PHY1_P0_64_L (REG_COMBO_PHY1_P0_BASE + 0xC8) 1956 #define REG_COMBO_PHY1_P0_64_H (REG_COMBO_PHY1_P0_BASE + 0xC9) 1957 #define REG_COMBO_PHY1_P0_65_L (REG_COMBO_PHY1_P0_BASE + 0xCA) 1958 #define REG_COMBO_PHY1_P0_65_H (REG_COMBO_PHY1_P0_BASE + 0xCB) 1959 #define REG_COMBO_PHY1_P0_66_L (REG_COMBO_PHY1_P0_BASE + 0xCC) 1960 #define REG_COMBO_PHY1_P0_66_H (REG_COMBO_PHY1_P0_BASE + 0xCD) 1961 #define REG_COMBO_PHY1_P0_67_L (REG_COMBO_PHY1_P0_BASE + 0xCE) 1962 #define REG_COMBO_PHY1_P0_67_H (REG_COMBO_PHY1_P0_BASE + 0xCF) 1963 #define REG_COMBO_PHY1_P0_68_L (REG_COMBO_PHY1_P0_BASE + 0xD0) 1964 #define REG_COMBO_PHY1_P0_68_H (REG_COMBO_PHY1_P0_BASE + 0xD1) 1965 #define REG_COMBO_PHY1_P0_69_L (REG_COMBO_PHY1_P0_BASE + 0xD2) 1966 #define REG_COMBO_PHY1_P0_69_H (REG_COMBO_PHY1_P0_BASE + 0xD3) 1967 #define REG_COMBO_PHY1_P0_6A_L (REG_COMBO_PHY1_P0_BASE + 0xD4) 1968 #define REG_COMBO_PHY1_P0_6A_H (REG_COMBO_PHY1_P0_BASE + 0xD5) 1969 #define REG_COMBO_PHY1_P0_6B_L (REG_COMBO_PHY1_P0_BASE + 0xD6) 1970 #define REG_COMBO_PHY1_P0_6B_H (REG_COMBO_PHY1_P0_BASE + 0xD7) 1971 #define REG_COMBO_PHY1_P0_6C_L (REG_COMBO_PHY1_P0_BASE + 0xD8) 1972 #define REG_COMBO_PHY1_P0_6C_H (REG_COMBO_PHY1_P0_BASE + 0xD9) 1973 #define REG_COMBO_PHY1_P0_6D_L (REG_COMBO_PHY1_P0_BASE + 0xDA) 1974 #define REG_COMBO_PHY1_P0_6D_H (REG_COMBO_PHY1_P0_BASE + 0xDB) 1975 #define REG_COMBO_PHY1_P0_6E_L (REG_COMBO_PHY1_P0_BASE + 0xDC) 1976 #define REG_COMBO_PHY1_P0_6E_H (REG_COMBO_PHY1_P0_BASE + 0xDD) 1977 #define REG_COMBO_PHY1_P0_6F_L (REG_COMBO_PHY1_P0_BASE + 0xDE) 1978 #define REG_COMBO_PHY1_P0_6F_H (REG_COMBO_PHY1_P0_BASE + 0xDF) 1979 #define REG_COMBO_PHY1_P0_70_L (REG_COMBO_PHY1_P0_BASE + 0xE0) 1980 #define REG_COMBO_PHY1_P0_70_H (REG_COMBO_PHY1_P0_BASE + 0xE1) 1981 #define REG_COMBO_PHY1_P0_71_L (REG_COMBO_PHY1_P0_BASE + 0xE2) 1982 #define REG_COMBO_PHY1_P0_71_H (REG_COMBO_PHY1_P0_BASE + 0xE3) 1983 #define REG_COMBO_PHY1_P0_72_L (REG_COMBO_PHY1_P0_BASE + 0xE4) 1984 #define REG_COMBO_PHY1_P0_72_H (REG_COMBO_PHY1_P0_BASE + 0xE5) 1985 #define REG_COMBO_PHY1_P0_73_L (REG_COMBO_PHY1_P0_BASE + 0xE6) 1986 #define REG_COMBO_PHY1_P0_73_H (REG_COMBO_PHY1_P0_BASE + 0xE7) 1987 #define REG_COMBO_PHY1_P0_74_L (REG_COMBO_PHY1_P0_BASE + 0xE8) 1988 #define REG_COMBO_PHY1_P0_74_H (REG_COMBO_PHY1_P0_BASE + 0xE9) 1989 #define REG_COMBO_PHY1_P0_75_L (REG_COMBO_PHY1_P0_BASE + 0xEA) 1990 #define REG_COMBO_PHY1_P0_75_H (REG_COMBO_PHY1_P0_BASE + 0xEB) 1991 #define REG_COMBO_PHY1_P0_76_L (REG_COMBO_PHY1_P0_BASE + 0xEC) 1992 #define REG_COMBO_PHY1_P0_76_H (REG_COMBO_PHY1_P0_BASE + 0xED) 1993 #define REG_COMBO_PHY1_P0_77_L (REG_COMBO_PHY1_P0_BASE + 0xEE) 1994 #define REG_COMBO_PHY1_P0_77_H (REG_COMBO_PHY1_P0_BASE + 0xEF) 1995 #define REG_COMBO_PHY1_P0_78_L (REG_COMBO_PHY1_P0_BASE + 0xF0) 1996 #define REG_COMBO_PHY1_P0_78_H (REG_COMBO_PHY1_P0_BASE + 0xF1) 1997 #define REG_COMBO_PHY1_P0_79_L (REG_COMBO_PHY1_P0_BASE + 0xF2) 1998 #define REG_COMBO_PHY1_P0_79_H (REG_COMBO_PHY1_P0_BASE + 0xF3) 1999 #define REG_COMBO_PHY1_P0_7A_L (REG_COMBO_PHY1_P0_BASE + 0xF4) 2000 #define REG_COMBO_PHY1_P0_7A_H (REG_COMBO_PHY1_P0_BASE + 0xF5) 2001 #define REG_COMBO_PHY1_P0_7B_L (REG_COMBO_PHY1_P0_BASE + 0xF6) 2002 #define REG_COMBO_PHY1_P0_7B_H (REG_COMBO_PHY1_P0_BASE + 0xF7) 2003 #define REG_COMBO_PHY1_P0_7C_L (REG_COMBO_PHY1_P0_BASE + 0xF8) 2004 #define REG_COMBO_PHY1_P0_7C_H (REG_COMBO_PHY1_P0_BASE + 0xF9) 2005 #define REG_COMBO_PHY1_P0_7D_L (REG_COMBO_PHY1_P0_BASE + 0xFA) 2006 #define REG_COMBO_PHY1_P0_7D_H (REG_COMBO_PHY1_P0_BASE + 0xFB) 2007 #define REG_COMBO_PHY1_P0_7E_L (REG_COMBO_PHY1_P0_BASE + 0xFC) 2008 #define REG_COMBO_PHY1_P0_7E_H (REG_COMBO_PHY1_P0_BASE + 0xFD) 2009 #define REG_COMBO_PHY1_P0_7F_L (REG_COMBO_PHY1_P0_BASE + 0xFE) 2010 #define REG_COMBO_PHY1_P0_7F_H (REG_COMBO_PHY1_P0_BASE + 0xFF) 2011 2012 // COMBO_PHY0_P1 2013 #define REG_COMBO_PHY0_P1_00_L (REG_COMBO_PHY0_P1_BASE + 0x00) 2014 #define REG_COMBO_PHY0_P1_00_H (REG_COMBO_PHY0_P1_BASE + 0x01) 2015 #define REG_COMBO_PHY0_P1_01_L (REG_COMBO_PHY0_P1_BASE + 0x02) 2016 #define REG_COMBO_PHY0_P1_01_H (REG_COMBO_PHY0_P1_BASE + 0x03) 2017 #define REG_COMBO_PHY0_P1_02_L (REG_COMBO_PHY0_P1_BASE + 0x04) 2018 #define REG_COMBO_PHY0_P1_02_H (REG_COMBO_PHY0_P1_BASE + 0x05) 2019 #define REG_COMBO_PHY0_P1_03_L (REG_COMBO_PHY0_P1_BASE + 0x06) 2020 #define REG_COMBO_PHY0_P1_03_H (REG_COMBO_PHY0_P1_BASE + 0x07) 2021 #define REG_COMBO_PHY0_P1_04_L (REG_COMBO_PHY0_P1_BASE + 0x08) 2022 #define REG_COMBO_PHY0_P1_04_H (REG_COMBO_PHY0_P1_BASE + 0x09) 2023 #define REG_COMBO_PHY0_P1_05_L (REG_COMBO_PHY0_P1_BASE + 0x0A) 2024 #define REG_COMBO_PHY0_P1_05_H (REG_COMBO_PHY0_P1_BASE + 0x0B) 2025 #define REG_COMBO_PHY0_P1_06_L (REG_COMBO_PHY0_P1_BASE + 0x0C) 2026 #define REG_COMBO_PHY0_P1_06_H (REG_COMBO_PHY0_P1_BASE + 0x0D) 2027 #define REG_COMBO_PHY0_P1_07_L (REG_COMBO_PHY0_P1_BASE + 0x0E) 2028 #define REG_COMBO_PHY0_P1_07_H (REG_COMBO_PHY0_P1_BASE + 0x0F) 2029 #define REG_COMBO_PHY0_P1_08_L (REG_COMBO_PHY0_P1_BASE + 0x10) 2030 #define REG_COMBO_PHY0_P1_08_H (REG_COMBO_PHY0_P1_BASE + 0x11) 2031 #define REG_COMBO_PHY0_P1_09_L (REG_COMBO_PHY0_P1_BASE + 0x12) 2032 #define REG_COMBO_PHY0_P1_09_H (REG_COMBO_PHY0_P1_BASE + 0x13) 2033 #define REG_COMBO_PHY0_P1_0A_L (REG_COMBO_PHY0_P1_BASE + 0x14) 2034 #define REG_COMBO_PHY0_P1_0A_H (REG_COMBO_PHY0_P1_BASE + 0x15) 2035 #define REG_COMBO_PHY0_P1_0B_L (REG_COMBO_PHY0_P1_BASE + 0x16) 2036 #define REG_COMBO_PHY0_P1_0B_H (REG_COMBO_PHY0_P1_BASE + 0x17) 2037 #define REG_COMBO_PHY0_P1_0C_L (REG_COMBO_PHY0_P1_BASE + 0x18) 2038 #define REG_COMBO_PHY0_P1_0C_H (REG_COMBO_PHY0_P1_BASE + 0x19) 2039 #define REG_COMBO_PHY0_P1_0D_L (REG_COMBO_PHY0_P1_BASE + 0x1A) 2040 #define REG_COMBO_PHY0_P1_0D_H (REG_COMBO_PHY0_P1_BASE + 0x1B) 2041 #define REG_COMBO_PHY0_P1_0E_L (REG_COMBO_PHY0_P1_BASE + 0x1C) 2042 #define REG_COMBO_PHY0_P1_0E_H (REG_COMBO_PHY0_P1_BASE + 0x1D) 2043 #define REG_COMBO_PHY0_P1_0F_L (REG_COMBO_PHY0_P1_BASE + 0x1E) 2044 #define REG_COMBO_PHY0_P1_0F_H (REG_COMBO_PHY0_P1_BASE + 0x1F) 2045 #define REG_COMBO_PHY0_P1_10_L (REG_COMBO_PHY0_P1_BASE + 0x20) 2046 #define REG_COMBO_PHY0_P1_10_H (REG_COMBO_PHY0_P1_BASE + 0x21) 2047 #define REG_COMBO_PHY0_P1_11_L (REG_COMBO_PHY0_P1_BASE + 0x22) 2048 #define REG_COMBO_PHY0_P1_11_H (REG_COMBO_PHY0_P1_BASE + 0x23) 2049 #define REG_COMBO_PHY0_P1_12_L (REG_COMBO_PHY0_P1_BASE + 0x24) 2050 #define REG_COMBO_PHY0_P1_12_H (REG_COMBO_PHY0_P1_BASE + 0x25) 2051 #define REG_COMBO_PHY0_P1_13_L (REG_COMBO_PHY0_P1_BASE + 0x26) 2052 #define REG_COMBO_PHY0_P1_13_H (REG_COMBO_PHY0_P1_BASE + 0x27) 2053 #define REG_COMBO_PHY0_P1_14_L (REG_COMBO_PHY0_P1_BASE + 0x28) 2054 #define REG_COMBO_PHY0_P1_14_H (REG_COMBO_PHY0_P1_BASE + 0x29) 2055 #define REG_COMBO_PHY0_P1_15_L (REG_COMBO_PHY0_P1_BASE + 0x2A) 2056 #define REG_COMBO_PHY0_P1_15_H (REG_COMBO_PHY0_P1_BASE + 0x2B) 2057 #define REG_COMBO_PHY0_P1_16_L (REG_COMBO_PHY0_P1_BASE + 0x2C) 2058 #define REG_COMBO_PHY0_P1_16_H (REG_COMBO_PHY0_P1_BASE + 0x2D) 2059 #define REG_COMBO_PHY0_P1_17_L (REG_COMBO_PHY0_P1_BASE + 0x2E) 2060 #define REG_COMBO_PHY0_P1_17_H (REG_COMBO_PHY0_P1_BASE + 0x2F) 2061 #define REG_COMBO_PHY0_P1_18_L (REG_COMBO_PHY0_P1_BASE + 0x30) 2062 #define REG_COMBO_PHY0_P1_18_H (REG_COMBO_PHY0_P1_BASE + 0x31) 2063 #define REG_COMBO_PHY0_P1_19_L (REG_COMBO_PHY0_P1_BASE + 0x32) 2064 #define REG_COMBO_PHY0_P1_19_H (REG_COMBO_PHY0_P1_BASE + 0x33) 2065 #define REG_COMBO_PHY0_P1_1A_L (REG_COMBO_PHY0_P1_BASE + 0x34) 2066 #define REG_COMBO_PHY0_P1_1A_H (REG_COMBO_PHY0_P1_BASE + 0x35) 2067 #define REG_COMBO_PHY0_P1_1B_L (REG_COMBO_PHY0_P1_BASE + 0x36) 2068 #define REG_COMBO_PHY0_P1_1B_H (REG_COMBO_PHY0_P1_BASE + 0x37) 2069 #define REG_COMBO_PHY0_P1_1C_L (REG_COMBO_PHY0_P1_BASE + 0x38) 2070 #define REG_COMBO_PHY0_P1_1C_H (REG_COMBO_PHY0_P1_BASE + 0x39) 2071 #define REG_COMBO_PHY0_P1_1D_L (REG_COMBO_PHY0_P1_BASE + 0x3A) 2072 #define REG_COMBO_PHY0_P1_1D_H (REG_COMBO_PHY0_P1_BASE + 0x3B) 2073 #define REG_COMBO_PHY0_P1_1E_L (REG_COMBO_PHY0_P1_BASE + 0x3C) 2074 #define REG_COMBO_PHY0_P1_1E_H (REG_COMBO_PHY0_P1_BASE + 0x3D) 2075 #define REG_COMBO_PHY0_P1_1F_L (REG_COMBO_PHY0_P1_BASE + 0x3E) 2076 #define REG_COMBO_PHY0_P1_1F_H (REG_COMBO_PHY0_P1_BASE + 0x3F) 2077 #define REG_COMBO_PHY0_P1_20_L (REG_COMBO_PHY0_P1_BASE + 0x40) 2078 #define REG_COMBO_PHY0_P1_20_H (REG_COMBO_PHY0_P1_BASE + 0x41) 2079 #define REG_COMBO_PHY0_P1_21_L (REG_COMBO_PHY0_P1_BASE + 0x42) 2080 #define REG_COMBO_PHY0_P1_21_H (REG_COMBO_PHY0_P1_BASE + 0x43) 2081 #define REG_COMBO_PHY0_P1_22_L (REG_COMBO_PHY0_P1_BASE + 0x44) 2082 #define REG_COMBO_PHY0_P1_22_H (REG_COMBO_PHY0_P1_BASE + 0x45) 2083 #define REG_COMBO_PHY0_P1_23_L (REG_COMBO_PHY0_P1_BASE + 0x46) 2084 #define REG_COMBO_PHY0_P1_23_H (REG_COMBO_PHY0_P1_BASE + 0x47) 2085 #define REG_COMBO_PHY0_P1_24_L (REG_COMBO_PHY0_P1_BASE + 0x48) 2086 #define REG_COMBO_PHY0_P1_24_H (REG_COMBO_PHY0_P1_BASE + 0x49) 2087 #define REG_COMBO_PHY0_P1_25_L (REG_COMBO_PHY0_P1_BASE + 0x4A) 2088 #define REG_COMBO_PHY0_P1_25_H (REG_COMBO_PHY0_P1_BASE + 0x4B) 2089 #define REG_COMBO_PHY0_P1_26_L (REG_COMBO_PHY0_P1_BASE + 0x4C) 2090 #define REG_COMBO_PHY0_P1_26_H (REG_COMBO_PHY0_P1_BASE + 0x4D) 2091 #define REG_COMBO_PHY0_P1_27_L (REG_COMBO_PHY0_P1_BASE + 0x4E) 2092 #define REG_COMBO_PHY0_P1_27_H (REG_COMBO_PHY0_P1_BASE + 0x4F) 2093 #define REG_COMBO_PHY0_P1_28_L (REG_COMBO_PHY0_P1_BASE + 0x50) 2094 #define REG_COMBO_PHY0_P1_28_H (REG_COMBO_PHY0_P1_BASE + 0x51) 2095 #define REG_COMBO_PHY0_P1_29_L (REG_COMBO_PHY0_P1_BASE + 0x52) 2096 #define REG_COMBO_PHY0_P1_29_H (REG_COMBO_PHY0_P1_BASE + 0x53) 2097 #define REG_COMBO_PHY0_P1_2A_L (REG_COMBO_PHY0_P1_BASE + 0x54) 2098 #define REG_COMBO_PHY0_P1_2A_H (REG_COMBO_PHY0_P1_BASE + 0x55) 2099 #define REG_COMBO_PHY0_P1_2B_L (REG_COMBO_PHY0_P1_BASE + 0x56) 2100 #define REG_COMBO_PHY0_P1_2B_H (REG_COMBO_PHY0_P1_BASE + 0x57) 2101 #define REG_COMBO_PHY0_P1_2C_L (REG_COMBO_PHY0_P1_BASE + 0x58) 2102 #define REG_COMBO_PHY0_P1_2C_H (REG_COMBO_PHY0_P1_BASE + 0x59) 2103 #define REG_COMBO_PHY0_P1_2D_L (REG_COMBO_PHY0_P1_BASE + 0x5A) 2104 #define REG_COMBO_PHY0_P1_2D_H (REG_COMBO_PHY0_P1_BASE + 0x5B) 2105 #define REG_COMBO_PHY0_P1_2E_L (REG_COMBO_PHY0_P1_BASE + 0x5C) 2106 #define REG_COMBO_PHY0_P1_2E_H (REG_COMBO_PHY0_P1_BASE + 0x5D) 2107 #define REG_COMBO_PHY0_P1_2F_L (REG_COMBO_PHY0_P1_BASE + 0x5E) 2108 #define REG_COMBO_PHY0_P1_2F_H (REG_COMBO_PHY0_P1_BASE + 0x5F) 2109 #define REG_COMBO_PHY0_P1_30_L (REG_COMBO_PHY0_P1_BASE + 0x60) 2110 #define REG_COMBO_PHY0_P1_30_H (REG_COMBO_PHY0_P1_BASE + 0x61) 2111 #define REG_COMBO_PHY0_P1_31_L (REG_COMBO_PHY0_P1_BASE + 0x62) 2112 #define REG_COMBO_PHY0_P1_31_H (REG_COMBO_PHY0_P1_BASE + 0x63) 2113 #define REG_COMBO_PHY0_P1_32_L (REG_COMBO_PHY0_P1_BASE + 0x64) 2114 #define REG_COMBO_PHY0_P1_32_H (REG_COMBO_PHY0_P1_BASE + 0x65) 2115 #define REG_COMBO_PHY0_P1_33_L (REG_COMBO_PHY0_P1_BASE + 0x66) 2116 #define REG_COMBO_PHY0_P1_33_H (REG_COMBO_PHY0_P1_BASE + 0x67) 2117 #define REG_COMBO_PHY0_P1_34_L (REG_COMBO_PHY0_P1_BASE + 0x68) 2118 #define REG_COMBO_PHY0_P1_34_H (REG_COMBO_PHY0_P1_BASE + 0x69) 2119 #define REG_COMBO_PHY0_P1_35_L (REG_COMBO_PHY0_P1_BASE + 0x6A) 2120 #define REG_COMBO_PHY0_P1_35_H (REG_COMBO_PHY0_P1_BASE + 0x6B) 2121 #define REG_COMBO_PHY0_P1_36_L (REG_COMBO_PHY0_P1_BASE + 0x6C) 2122 #define REG_COMBO_PHY0_P1_36_H (REG_COMBO_PHY0_P1_BASE + 0x6D) 2123 #define REG_COMBO_PHY0_P1_37_L (REG_COMBO_PHY0_P1_BASE + 0x6E) 2124 #define REG_COMBO_PHY0_P1_37_H (REG_COMBO_PHY0_P1_BASE + 0x6F) 2125 #define REG_COMBO_PHY0_P1_38_L (REG_COMBO_PHY0_P1_BASE + 0x70) 2126 #define REG_COMBO_PHY0_P1_38_H (REG_COMBO_PHY0_P1_BASE + 0x71) 2127 #define REG_COMBO_PHY0_P1_39_L (REG_COMBO_PHY0_P1_BASE + 0x72) 2128 #define REG_COMBO_PHY0_P1_39_H (REG_COMBO_PHY0_P1_BASE + 0x73) 2129 #define REG_COMBO_PHY0_P1_3A_L (REG_COMBO_PHY0_P1_BASE + 0x74) 2130 #define REG_COMBO_PHY0_P1_3A_H (REG_COMBO_PHY0_P1_BASE + 0x75) 2131 #define REG_COMBO_PHY0_P1_3B_L (REG_COMBO_PHY0_P1_BASE + 0x76) 2132 #define REG_COMBO_PHY0_P1_3B_H (REG_COMBO_PHY0_P1_BASE + 0x77) 2133 #define REG_COMBO_PHY0_P1_3C_L (REG_COMBO_PHY0_P1_BASE + 0x78) 2134 #define REG_COMBO_PHY0_P1_3C_H (REG_COMBO_PHY0_P1_BASE + 0x79) 2135 #define REG_COMBO_PHY0_P1_3D_L (REG_COMBO_PHY0_P1_BASE + 0x7A) 2136 #define REG_COMBO_PHY0_P1_3D_H (REG_COMBO_PHY0_P1_BASE + 0x7B) 2137 #define REG_COMBO_PHY0_P1_3E_L (REG_COMBO_PHY0_P1_BASE + 0x7C) 2138 #define REG_COMBO_PHY0_P1_3E_H (REG_COMBO_PHY0_P1_BASE + 0x7D) 2139 #define REG_COMBO_PHY0_P1_3F_L (REG_COMBO_PHY0_P1_BASE + 0x7E) 2140 #define REG_COMBO_PHY0_P1_3F_H (REG_COMBO_PHY0_P1_BASE + 0x7F) 2141 #define REG_COMBO_PHY0_P1_40_L (REG_COMBO_PHY0_P1_BASE + 0x80) 2142 #define REG_COMBO_PHY0_P1_40_H (REG_COMBO_PHY0_P1_BASE + 0x81) 2143 #define REG_COMBO_PHY0_P1_41_L (REG_COMBO_PHY0_P1_BASE + 0x82) 2144 #define REG_COMBO_PHY0_P1_41_H (REG_COMBO_PHY0_P1_BASE + 0x83) 2145 #define REG_COMBO_PHY0_P1_42_L (REG_COMBO_PHY0_P1_BASE + 0x84) 2146 #define REG_COMBO_PHY0_P1_42_H (REG_COMBO_PHY0_P1_BASE + 0x85) 2147 #define REG_COMBO_PHY0_P1_43_L (REG_COMBO_PHY0_P1_BASE + 0x86) 2148 #define REG_COMBO_PHY0_P1_43_H (REG_COMBO_PHY0_P1_BASE + 0x87) 2149 #define REG_COMBO_PHY0_P1_44_L (REG_COMBO_PHY0_P1_BASE + 0x88) 2150 #define REG_COMBO_PHY0_P1_44_H (REG_COMBO_PHY0_P1_BASE + 0x89) 2151 #define REG_COMBO_PHY0_P1_45_L (REG_COMBO_PHY0_P1_BASE + 0x8A) 2152 #define REG_COMBO_PHY0_P1_45_H (REG_COMBO_PHY0_P1_BASE + 0x8B) 2153 #define REG_COMBO_PHY0_P1_46_L (REG_COMBO_PHY0_P1_BASE + 0x8C) 2154 #define REG_COMBO_PHY0_P1_46_H (REG_COMBO_PHY0_P1_BASE + 0x8D) 2155 #define REG_COMBO_PHY0_P1_47_L (REG_COMBO_PHY0_P1_BASE + 0x8E) 2156 #define REG_COMBO_PHY0_P1_47_H (REG_COMBO_PHY0_P1_BASE + 0x8F) 2157 #define REG_COMBO_PHY0_P1_48_L (REG_COMBO_PHY0_P1_BASE + 0x90) 2158 #define REG_COMBO_PHY0_P1_48_H (REG_COMBO_PHY0_P1_BASE + 0x91) 2159 #define REG_COMBO_PHY0_P1_49_L (REG_COMBO_PHY0_P1_BASE + 0x92) 2160 #define REG_COMBO_PHY0_P1_49_H (REG_COMBO_PHY0_P1_BASE + 0x93) 2161 #define REG_COMBO_PHY0_P1_4A_L (REG_COMBO_PHY0_P1_BASE + 0x94) 2162 #define REG_COMBO_PHY0_P1_4A_H (REG_COMBO_PHY0_P1_BASE + 0x95) 2163 #define REG_COMBO_PHY0_P1_4B_L (REG_COMBO_PHY0_P1_BASE + 0x96) 2164 #define REG_COMBO_PHY0_P1_4B_H (REG_COMBO_PHY0_P1_BASE + 0x97) 2165 #define REG_COMBO_PHY0_P1_4C_L (REG_COMBO_PHY0_P1_BASE + 0x98) 2166 #define REG_COMBO_PHY0_P1_4C_H (REG_COMBO_PHY0_P1_BASE + 0x99) 2167 #define REG_COMBO_PHY0_P1_4D_L (REG_COMBO_PHY0_P1_BASE + 0x9A) 2168 #define REG_COMBO_PHY0_P1_4D_H (REG_COMBO_PHY0_P1_BASE + 0x9B) 2169 #define REG_COMBO_PHY0_P1_4E_L (REG_COMBO_PHY0_P1_BASE + 0x9C) 2170 #define REG_COMBO_PHY0_P1_4E_H (REG_COMBO_PHY0_P1_BASE + 0x9D) 2171 #define REG_COMBO_PHY0_P1_4F_L (REG_COMBO_PHY0_P1_BASE + 0x9E) 2172 #define REG_COMBO_PHY0_P1_4F_H (REG_COMBO_PHY0_P1_BASE + 0x9F) 2173 #define REG_COMBO_PHY0_P1_50_L (REG_COMBO_PHY0_P1_BASE + 0xA0) 2174 #define REG_COMBO_PHY0_P1_50_H (REG_COMBO_PHY0_P1_BASE + 0xA1) 2175 #define REG_COMBO_PHY0_P1_51_L (REG_COMBO_PHY0_P1_BASE + 0xA2) 2176 #define REG_COMBO_PHY0_P1_51_H (REG_COMBO_PHY0_P1_BASE + 0xA3) 2177 #define REG_COMBO_PHY0_P1_52_L (REG_COMBO_PHY0_P1_BASE + 0xA4) 2178 #define REG_COMBO_PHY0_P1_52_H (REG_COMBO_PHY0_P1_BASE + 0xA5) 2179 #define REG_COMBO_PHY0_P1_53_L (REG_COMBO_PHY0_P1_BASE + 0xA6) 2180 #define REG_COMBO_PHY0_P1_53_H (REG_COMBO_PHY0_P1_BASE + 0xA7) 2181 #define REG_COMBO_PHY0_P1_54_L (REG_COMBO_PHY0_P1_BASE + 0xA8) 2182 #define REG_COMBO_PHY0_P1_54_H (REG_COMBO_PHY0_P1_BASE + 0xA9) 2183 #define REG_COMBO_PHY0_P1_55_L (REG_COMBO_PHY0_P1_BASE + 0xAA) 2184 #define REG_COMBO_PHY0_P1_55_H (REG_COMBO_PHY0_P1_BASE + 0xAB) 2185 #define REG_COMBO_PHY0_P1_56_L (REG_COMBO_PHY0_P1_BASE + 0xAC) 2186 #define REG_COMBO_PHY0_P1_56_H (REG_COMBO_PHY0_P1_BASE + 0xAD) 2187 #define REG_COMBO_PHY0_P1_57_L (REG_COMBO_PHY0_P1_BASE + 0xAE) 2188 #define REG_COMBO_PHY0_P1_57_H (REG_COMBO_PHY0_P1_BASE + 0xAF) 2189 #define REG_COMBO_PHY0_P1_58_L (REG_COMBO_PHY0_P1_BASE + 0xB0) 2190 #define REG_COMBO_PHY0_P1_58_H (REG_COMBO_PHY0_P1_BASE + 0xB1) 2191 #define REG_COMBO_PHY0_P1_59_L (REG_COMBO_PHY0_P1_BASE + 0xB2) 2192 #define REG_COMBO_PHY0_P1_59_H (REG_COMBO_PHY0_P1_BASE + 0xB3) 2193 #define REG_COMBO_PHY0_P1_5A_L (REG_COMBO_PHY0_P1_BASE + 0xB4) 2194 #define REG_COMBO_PHY0_P1_5A_H (REG_COMBO_PHY0_P1_BASE + 0xB5) 2195 #define REG_COMBO_PHY0_P1_5B_L (REG_COMBO_PHY0_P1_BASE + 0xB6) 2196 #define REG_COMBO_PHY0_P1_5B_H (REG_COMBO_PHY0_P1_BASE + 0xB7) 2197 #define REG_COMBO_PHY0_P1_5C_L (REG_COMBO_PHY0_P1_BASE + 0xB8) 2198 #define REG_COMBO_PHY0_P1_5C_H (REG_COMBO_PHY0_P1_BASE + 0xB9) 2199 #define REG_COMBO_PHY0_P1_5D_L (REG_COMBO_PHY0_P1_BASE + 0xBA) 2200 #define REG_COMBO_PHY0_P1_5D_H (REG_COMBO_PHY0_P1_BASE + 0xBB) 2201 #define REG_COMBO_PHY0_P1_5E_L (REG_COMBO_PHY0_P1_BASE + 0xBC) 2202 #define REG_COMBO_PHY0_P1_5E_H (REG_COMBO_PHY0_P1_BASE + 0xBD) 2203 #define REG_COMBO_PHY0_P1_5F_L (REG_COMBO_PHY0_P1_BASE + 0xBE) 2204 #define REG_COMBO_PHY0_P1_5F_H (REG_COMBO_PHY0_P1_BASE + 0xBF) 2205 #define REG_COMBO_PHY0_P1_60_L (REG_COMBO_PHY0_P1_BASE + 0xC0) 2206 #define REG_COMBO_PHY0_P1_60_H (REG_COMBO_PHY0_P1_BASE + 0xC1) 2207 #define REG_COMBO_PHY0_P1_61_L (REG_COMBO_PHY0_P1_BASE + 0xC2) 2208 #define REG_COMBO_PHY0_P1_61_H (REG_COMBO_PHY0_P1_BASE + 0xC3) 2209 #define REG_COMBO_PHY0_P1_62_L (REG_COMBO_PHY0_P1_BASE + 0xC4) 2210 #define REG_COMBO_PHY0_P1_62_H (REG_COMBO_PHY0_P1_BASE + 0xC5) 2211 #define REG_COMBO_PHY0_P1_63_L (REG_COMBO_PHY0_P1_BASE + 0xC6) 2212 #define REG_COMBO_PHY0_P1_63_H (REG_COMBO_PHY0_P1_BASE + 0xC7) 2213 #define REG_COMBO_PHY0_P1_64_L (REG_COMBO_PHY0_P1_BASE + 0xC8) 2214 #define REG_COMBO_PHY0_P1_64_H (REG_COMBO_PHY0_P1_BASE + 0xC9) 2215 #define REG_COMBO_PHY0_P1_65_L (REG_COMBO_PHY0_P1_BASE + 0xCA) 2216 #define REG_COMBO_PHY0_P1_65_H (REG_COMBO_PHY0_P1_BASE + 0xCB) 2217 #define REG_COMBO_PHY0_P1_66_L (REG_COMBO_PHY0_P1_BASE + 0xCC) 2218 #define REG_COMBO_PHY0_P1_66_H (REG_COMBO_PHY0_P1_BASE + 0xCD) 2219 #define REG_COMBO_PHY0_P1_67_L (REG_COMBO_PHY0_P1_BASE + 0xCE) 2220 #define REG_COMBO_PHY0_P1_67_H (REG_COMBO_PHY0_P1_BASE + 0xCF) 2221 #define REG_COMBO_PHY0_P1_68_L (REG_COMBO_PHY0_P1_BASE + 0xD0) 2222 #define REG_COMBO_PHY0_P1_68_H (REG_COMBO_PHY0_P1_BASE + 0xD1) 2223 #define REG_COMBO_PHY0_P1_69_L (REG_COMBO_PHY0_P1_BASE + 0xD2) 2224 #define REG_COMBO_PHY0_P1_69_H (REG_COMBO_PHY0_P1_BASE + 0xD3) 2225 #define REG_COMBO_PHY0_P1_6A_L (REG_COMBO_PHY0_P1_BASE + 0xD4) 2226 #define REG_COMBO_PHY0_P1_6A_H (REG_COMBO_PHY0_P1_BASE + 0xD5) 2227 #define REG_COMBO_PHY0_P1_6B_L (REG_COMBO_PHY0_P1_BASE + 0xD6) 2228 #define REG_COMBO_PHY0_P1_6B_H (REG_COMBO_PHY0_P1_BASE + 0xD7) 2229 #define REG_COMBO_PHY0_P1_6C_L (REG_COMBO_PHY0_P1_BASE + 0xD8) 2230 #define REG_COMBO_PHY0_P1_6C_H (REG_COMBO_PHY0_P1_BASE + 0xD9) 2231 #define REG_COMBO_PHY0_P1_6D_L (REG_COMBO_PHY0_P1_BASE + 0xDA) 2232 #define REG_COMBO_PHY0_P1_6D_H (REG_COMBO_PHY0_P1_BASE + 0xDB) 2233 #define REG_COMBO_PHY0_P1_6E_L (REG_COMBO_PHY0_P1_BASE + 0xDC) 2234 #define REG_COMBO_PHY0_P1_6E_H (REG_COMBO_PHY0_P1_BASE + 0xDD) 2235 #define REG_COMBO_PHY0_P1_6F_L (REG_COMBO_PHY0_P1_BASE + 0xDE) 2236 #define REG_COMBO_PHY0_P1_6F_H (REG_COMBO_PHY0_P1_BASE + 0xDF) 2237 #define REG_COMBO_PHY0_P1_70_L (REG_COMBO_PHY0_P1_BASE + 0xE0) 2238 #define REG_COMBO_PHY0_P1_70_H (REG_COMBO_PHY0_P1_BASE + 0xE1) 2239 #define REG_COMBO_PHY0_P1_71_L (REG_COMBO_PHY0_P1_BASE + 0xE2) 2240 #define REG_COMBO_PHY0_P1_71_H (REG_COMBO_PHY0_P1_BASE + 0xE3) 2241 #define REG_COMBO_PHY0_P1_72_L (REG_COMBO_PHY0_P1_BASE + 0xE4) 2242 #define REG_COMBO_PHY0_P1_72_H (REG_COMBO_PHY0_P1_BASE + 0xE5) 2243 #define REG_COMBO_PHY0_P1_73_L (REG_COMBO_PHY0_P1_BASE + 0xE6) 2244 #define REG_COMBO_PHY0_P1_73_H (REG_COMBO_PHY0_P1_BASE + 0xE7) 2245 #define REG_COMBO_PHY0_P1_74_L (REG_COMBO_PHY0_P1_BASE + 0xE8) 2246 #define REG_COMBO_PHY0_P1_74_H (REG_COMBO_PHY0_P1_BASE + 0xE9) 2247 #define REG_COMBO_PHY0_P1_75_L (REG_COMBO_PHY0_P1_BASE + 0xEA) 2248 #define REG_COMBO_PHY0_P1_75_H (REG_COMBO_PHY0_P1_BASE + 0xEB) 2249 #define REG_COMBO_PHY0_P1_76_L (REG_COMBO_PHY0_P1_BASE + 0xEC) 2250 #define REG_COMBO_PHY0_P1_76_H (REG_COMBO_PHY0_P1_BASE + 0xED) 2251 #define REG_COMBO_PHY0_P1_77_L (REG_COMBO_PHY0_P1_BASE + 0xEE) 2252 #define REG_COMBO_PHY0_P1_77_H (REG_COMBO_PHY0_P1_BASE + 0xEF) 2253 #define REG_COMBO_PHY0_P1_78_L (REG_COMBO_PHY0_P1_BASE + 0xF0) 2254 #define REG_COMBO_PHY0_P1_78_H (REG_COMBO_PHY0_P1_BASE + 0xF1) 2255 #define REG_COMBO_PHY0_P1_79_L (REG_COMBO_PHY0_P1_BASE + 0xF2) 2256 #define REG_COMBO_PHY0_P1_79_H (REG_COMBO_PHY0_P1_BASE + 0xF3) 2257 #define REG_COMBO_PHY0_P1_7A_L (REG_COMBO_PHY0_P1_BASE + 0xF4) 2258 #define REG_COMBO_PHY0_P1_7A_H (REG_COMBO_PHY0_P1_BASE + 0xF5) 2259 #define REG_COMBO_PHY0_P1_7B_L (REG_COMBO_PHY0_P1_BASE + 0xF6) 2260 #define REG_COMBO_PHY0_P1_7B_H (REG_COMBO_PHY0_P1_BASE + 0xF7) 2261 #define REG_COMBO_PHY0_P1_7C_L (REG_COMBO_PHY0_P1_BASE + 0xF8) 2262 #define REG_COMBO_PHY0_P1_7C_H (REG_COMBO_PHY0_P1_BASE + 0xF9) 2263 #define REG_COMBO_PHY0_P1_7D_L (REG_COMBO_PHY0_P1_BASE + 0xFA) 2264 #define REG_COMBO_PHY0_P1_7D_H (REG_COMBO_PHY0_P1_BASE + 0xFB) 2265 #define REG_COMBO_PHY0_P1_7E_L (REG_COMBO_PHY0_P1_BASE + 0xFC) 2266 #define REG_COMBO_PHY0_P1_7E_H (REG_COMBO_PHY0_P1_BASE + 0xFD) 2267 #define REG_COMBO_PHY0_P1_7F_L (REG_COMBO_PHY0_P1_BASE + 0xFE) 2268 #define REG_COMBO_PHY0_P1_7F_H (REG_COMBO_PHY0_P1_BASE + 0xFF) 2269 2270 // COMBO_PHY1_P1 2271 #define REG_COMBO_PHY1_P1_00_L (REG_COMBO_PHY1_P1_BASE + 0x00) 2272 #define REG_COMBO_PHY1_P1_00_H (REG_COMBO_PHY1_P1_BASE + 0x01) 2273 #define REG_COMBO_PHY1_P1_01_L (REG_COMBO_PHY1_P1_BASE + 0x02) 2274 #define REG_COMBO_PHY1_P1_01_H (REG_COMBO_PHY1_P1_BASE + 0x03) 2275 #define REG_COMBO_PHY1_P1_02_L (REG_COMBO_PHY1_P1_BASE + 0x04) 2276 #define REG_COMBO_PHY1_P1_02_H (REG_COMBO_PHY1_P1_BASE + 0x05) 2277 #define REG_COMBO_PHY1_P1_03_L (REG_COMBO_PHY1_P1_BASE + 0x06) 2278 #define REG_COMBO_PHY1_P1_03_H (REG_COMBO_PHY1_P1_BASE + 0x07) 2279 #define REG_COMBO_PHY1_P1_04_L (REG_COMBO_PHY1_P1_BASE + 0x08) 2280 #define REG_COMBO_PHY1_P1_04_H (REG_COMBO_PHY1_P1_BASE + 0x09) 2281 #define REG_COMBO_PHY1_P1_05_L (REG_COMBO_PHY1_P1_BASE + 0x0A) 2282 #define REG_COMBO_PHY1_P1_05_H (REG_COMBO_PHY1_P1_BASE + 0x0B) 2283 #define REG_COMBO_PHY1_P1_06_L (REG_COMBO_PHY1_P1_BASE + 0x0C) 2284 #define REG_COMBO_PHY1_P1_06_H (REG_COMBO_PHY1_P1_BASE + 0x0D) 2285 #define REG_COMBO_PHY1_P1_07_L (REG_COMBO_PHY1_P1_BASE + 0x0E) 2286 #define REG_COMBO_PHY1_P1_07_H (REG_COMBO_PHY1_P1_BASE + 0x0F) 2287 #define REG_COMBO_PHY1_P1_08_L (REG_COMBO_PHY1_P1_BASE + 0x10) 2288 #define REG_COMBO_PHY1_P1_08_H (REG_COMBO_PHY1_P1_BASE + 0x11) 2289 #define REG_COMBO_PHY1_P1_09_L (REG_COMBO_PHY1_P1_BASE + 0x12) 2290 #define REG_COMBO_PHY1_P1_09_H (REG_COMBO_PHY1_P1_BASE + 0x13) 2291 #define REG_COMBO_PHY1_P1_0A_L (REG_COMBO_PHY1_P1_BASE + 0x14) 2292 #define REG_COMBO_PHY1_P1_0A_H (REG_COMBO_PHY1_P1_BASE + 0x15) 2293 #define REG_COMBO_PHY1_P1_0B_L (REG_COMBO_PHY1_P1_BASE + 0x16) 2294 #define REG_COMBO_PHY1_P1_0B_H (REG_COMBO_PHY1_P1_BASE + 0x17) 2295 #define REG_COMBO_PHY1_P1_0C_L (REG_COMBO_PHY1_P1_BASE + 0x18) 2296 #define REG_COMBO_PHY1_P1_0C_H (REG_COMBO_PHY1_P1_BASE + 0x19) 2297 #define REG_COMBO_PHY1_P1_0D_L (REG_COMBO_PHY1_P1_BASE + 0x1A) 2298 #define REG_COMBO_PHY1_P1_0D_H (REG_COMBO_PHY1_P1_BASE + 0x1B) 2299 #define REG_COMBO_PHY1_P1_0E_L (REG_COMBO_PHY1_P1_BASE + 0x1C) 2300 #define REG_COMBO_PHY1_P1_0E_H (REG_COMBO_PHY1_P1_BASE + 0x1D) 2301 #define REG_COMBO_PHY1_P1_0F_L (REG_COMBO_PHY1_P1_BASE + 0x1E) 2302 #define REG_COMBO_PHY1_P1_0F_H (REG_COMBO_PHY1_P1_BASE + 0x1F) 2303 #define REG_COMBO_PHY1_P1_10_L (REG_COMBO_PHY1_P1_BASE + 0x20) 2304 #define REG_COMBO_PHY1_P1_10_H (REG_COMBO_PHY1_P1_BASE + 0x21) 2305 #define REG_COMBO_PHY1_P1_11_L (REG_COMBO_PHY1_P1_BASE + 0x22) 2306 #define REG_COMBO_PHY1_P1_11_H (REG_COMBO_PHY1_P1_BASE + 0x23) 2307 #define REG_COMBO_PHY1_P1_12_L (REG_COMBO_PHY1_P1_BASE + 0x24) 2308 #define REG_COMBO_PHY1_P1_12_H (REG_COMBO_PHY1_P1_BASE + 0x25) 2309 #define REG_COMBO_PHY1_P1_13_L (REG_COMBO_PHY1_P1_BASE + 0x26) 2310 #define REG_COMBO_PHY1_P1_13_H (REG_COMBO_PHY1_P1_BASE + 0x27) 2311 #define REG_COMBO_PHY1_P1_14_L (REG_COMBO_PHY1_P1_BASE + 0x28) 2312 #define REG_COMBO_PHY1_P1_14_H (REG_COMBO_PHY1_P1_BASE + 0x29) 2313 #define REG_COMBO_PHY1_P1_15_L (REG_COMBO_PHY1_P1_BASE + 0x2A) 2314 #define REG_COMBO_PHY1_P1_15_H (REG_COMBO_PHY1_P1_BASE + 0x2B) 2315 #define REG_COMBO_PHY1_P1_16_L (REG_COMBO_PHY1_P1_BASE + 0x2C) 2316 #define REG_COMBO_PHY1_P1_16_H (REG_COMBO_PHY1_P1_BASE + 0x2D) 2317 #define REG_COMBO_PHY1_P1_17_L (REG_COMBO_PHY1_P1_BASE + 0x2E) 2318 #define REG_COMBO_PHY1_P1_17_H (REG_COMBO_PHY1_P1_BASE + 0x2F) 2319 #define REG_COMBO_PHY1_P1_18_L (REG_COMBO_PHY1_P1_BASE + 0x30) 2320 #define REG_COMBO_PHY1_P1_18_H (REG_COMBO_PHY1_P1_BASE + 0x31) 2321 #define REG_COMBO_PHY1_P1_19_L (REG_COMBO_PHY1_P1_BASE + 0x32) 2322 #define REG_COMBO_PHY1_P1_19_H (REG_COMBO_PHY1_P1_BASE + 0x33) 2323 #define REG_COMBO_PHY1_P1_1A_L (REG_COMBO_PHY1_P1_BASE + 0x34) 2324 #define REG_COMBO_PHY1_P1_1A_H (REG_COMBO_PHY1_P1_BASE + 0x35) 2325 #define REG_COMBO_PHY1_P1_1B_L (REG_COMBO_PHY1_P1_BASE + 0x36) 2326 #define REG_COMBO_PHY1_P1_1B_H (REG_COMBO_PHY1_P1_BASE + 0x37) 2327 #define REG_COMBO_PHY1_P1_1C_L (REG_COMBO_PHY1_P1_BASE + 0x38) 2328 #define REG_COMBO_PHY1_P1_1C_H (REG_COMBO_PHY1_P1_BASE + 0x39) 2329 #define REG_COMBO_PHY1_P1_1D_L (REG_COMBO_PHY1_P1_BASE + 0x3A) 2330 #define REG_COMBO_PHY1_P1_1D_H (REG_COMBO_PHY1_P1_BASE + 0x3B) 2331 #define REG_COMBO_PHY1_P1_1E_L (REG_COMBO_PHY1_P1_BASE + 0x3C) 2332 #define REG_COMBO_PHY1_P1_1E_H (REG_COMBO_PHY1_P1_BASE + 0x3D) 2333 #define REG_COMBO_PHY1_P1_1F_L (REG_COMBO_PHY1_P1_BASE + 0x3E) 2334 #define REG_COMBO_PHY1_P1_1F_H (REG_COMBO_PHY1_P1_BASE + 0x3F) 2335 #define REG_COMBO_PHY1_P1_20_L (REG_COMBO_PHY1_P1_BASE + 0x40) 2336 #define REG_COMBO_PHY1_P1_20_H (REG_COMBO_PHY1_P1_BASE + 0x41) 2337 #define REG_COMBO_PHY1_P1_21_L (REG_COMBO_PHY1_P1_BASE + 0x42) 2338 #define REG_COMBO_PHY1_P1_21_H (REG_COMBO_PHY1_P1_BASE + 0x43) 2339 #define REG_COMBO_PHY1_P1_22_L (REG_COMBO_PHY1_P1_BASE + 0x44) 2340 #define REG_COMBO_PHY1_P1_22_H (REG_COMBO_PHY1_P1_BASE + 0x45) 2341 #define REG_COMBO_PHY1_P1_23_L (REG_COMBO_PHY1_P1_BASE + 0x46) 2342 #define REG_COMBO_PHY1_P1_23_H (REG_COMBO_PHY1_P1_BASE + 0x47) 2343 #define REG_COMBO_PHY1_P1_24_L (REG_COMBO_PHY1_P1_BASE + 0x48) 2344 #define REG_COMBO_PHY1_P1_24_H (REG_COMBO_PHY1_P1_BASE + 0x49) 2345 #define REG_COMBO_PHY1_P1_25_L (REG_COMBO_PHY1_P1_BASE + 0x4A) 2346 #define REG_COMBO_PHY1_P1_25_H (REG_COMBO_PHY1_P1_BASE + 0x4B) 2347 #define REG_COMBO_PHY1_P1_26_L (REG_COMBO_PHY1_P1_BASE + 0x4C) 2348 #define REG_COMBO_PHY1_P1_26_H (REG_COMBO_PHY1_P1_BASE + 0x4D) 2349 #define REG_COMBO_PHY1_P1_27_L (REG_COMBO_PHY1_P1_BASE + 0x4E) 2350 #define REG_COMBO_PHY1_P1_27_H (REG_COMBO_PHY1_P1_BASE + 0x4F) 2351 #define REG_COMBO_PHY1_P1_28_L (REG_COMBO_PHY1_P1_BASE + 0x50) 2352 #define REG_COMBO_PHY1_P1_28_H (REG_COMBO_PHY1_P1_BASE + 0x51) 2353 #define REG_COMBO_PHY1_P1_29_L (REG_COMBO_PHY1_P1_BASE + 0x52) 2354 #define REG_COMBO_PHY1_P1_29_H (REG_COMBO_PHY1_P1_BASE + 0x53) 2355 #define REG_COMBO_PHY1_P1_2A_L (REG_COMBO_PHY1_P1_BASE + 0x54) 2356 #define REG_COMBO_PHY1_P1_2A_H (REG_COMBO_PHY1_P1_BASE + 0x55) 2357 #define REG_COMBO_PHY1_P1_2B_L (REG_COMBO_PHY1_P1_BASE + 0x56) 2358 #define REG_COMBO_PHY1_P1_2B_H (REG_COMBO_PHY1_P1_BASE + 0x57) 2359 #define REG_COMBO_PHY1_P1_2C_L (REG_COMBO_PHY1_P1_BASE + 0x58) 2360 #define REG_COMBO_PHY1_P1_2C_H (REG_COMBO_PHY1_P1_BASE + 0x59) 2361 #define REG_COMBO_PHY1_P1_2D_L (REG_COMBO_PHY1_P1_BASE + 0x5A) 2362 #define REG_COMBO_PHY1_P1_2D_H (REG_COMBO_PHY1_P1_BASE + 0x5B) 2363 #define REG_COMBO_PHY1_P1_2E_L (REG_COMBO_PHY1_P1_BASE + 0x5C) 2364 #define REG_COMBO_PHY1_P1_2E_H (REG_COMBO_PHY1_P1_BASE + 0x5D) 2365 #define REG_COMBO_PHY1_P1_2F_L (REG_COMBO_PHY1_P1_BASE + 0x5E) 2366 #define REG_COMBO_PHY1_P1_2F_H (REG_COMBO_PHY1_P1_BASE + 0x5F) 2367 #define REG_COMBO_PHY1_P1_30_L (REG_COMBO_PHY1_P1_BASE + 0x60) 2368 #define REG_COMBO_PHY1_P1_30_H (REG_COMBO_PHY1_P1_BASE + 0x61) 2369 #define REG_COMBO_PHY1_P1_31_L (REG_COMBO_PHY1_P1_BASE + 0x62) 2370 #define REG_COMBO_PHY1_P1_31_H (REG_COMBO_PHY1_P1_BASE + 0x63) 2371 #define REG_COMBO_PHY1_P1_32_L (REG_COMBO_PHY1_P1_BASE + 0x64) 2372 #define REG_COMBO_PHY1_P1_32_H (REG_COMBO_PHY1_P1_BASE + 0x65) 2373 #define REG_COMBO_PHY1_P1_33_L (REG_COMBO_PHY1_P1_BASE + 0x66) 2374 #define REG_COMBO_PHY1_P1_33_H (REG_COMBO_PHY1_P1_BASE + 0x67) 2375 #define REG_COMBO_PHY1_P1_34_L (REG_COMBO_PHY1_P1_BASE + 0x68) 2376 #define REG_COMBO_PHY1_P1_34_H (REG_COMBO_PHY1_P1_BASE + 0x69) 2377 #define REG_COMBO_PHY1_P1_35_L (REG_COMBO_PHY1_P1_BASE + 0x6A) 2378 #define REG_COMBO_PHY1_P1_35_H (REG_COMBO_PHY1_P1_BASE + 0x6B) 2379 #define REG_COMBO_PHY1_P1_36_L (REG_COMBO_PHY1_P1_BASE + 0x6C) 2380 #define REG_COMBO_PHY1_P1_36_H (REG_COMBO_PHY1_P1_BASE + 0x6D) 2381 #define REG_COMBO_PHY1_P1_37_L (REG_COMBO_PHY1_P1_BASE + 0x6E) 2382 #define REG_COMBO_PHY1_P1_37_H (REG_COMBO_PHY1_P1_BASE + 0x6F) 2383 #define REG_COMBO_PHY1_P1_38_L (REG_COMBO_PHY1_P1_BASE + 0x70) 2384 #define REG_COMBO_PHY1_P1_38_H (REG_COMBO_PHY1_P1_BASE + 0x71) 2385 #define REG_COMBO_PHY1_P1_39_L (REG_COMBO_PHY1_P1_BASE + 0x72) 2386 #define REG_COMBO_PHY1_P1_39_H (REG_COMBO_PHY1_P1_BASE + 0x73) 2387 #define REG_COMBO_PHY1_P1_3A_L (REG_COMBO_PHY1_P1_BASE + 0x74) 2388 #define REG_COMBO_PHY1_P1_3A_H (REG_COMBO_PHY1_P1_BASE + 0x75) 2389 #define REG_COMBO_PHY1_P1_3B_L (REG_COMBO_PHY1_P1_BASE + 0x76) 2390 #define REG_COMBO_PHY1_P1_3B_H (REG_COMBO_PHY1_P1_BASE + 0x77) 2391 #define REG_COMBO_PHY1_P1_3C_L (REG_COMBO_PHY1_P1_BASE + 0x78) 2392 #define REG_COMBO_PHY1_P1_3C_H (REG_COMBO_PHY1_P1_BASE + 0x79) 2393 #define REG_COMBO_PHY1_P1_3D_L (REG_COMBO_PHY1_P1_BASE + 0x7A) 2394 #define REG_COMBO_PHY1_P1_3D_H (REG_COMBO_PHY1_P1_BASE + 0x7B) 2395 #define REG_COMBO_PHY1_P1_3E_L (REG_COMBO_PHY1_P1_BASE + 0x7C) 2396 #define REG_COMBO_PHY1_P1_3E_H (REG_COMBO_PHY1_P1_BASE + 0x7D) 2397 #define REG_COMBO_PHY1_P1_3F_L (REG_COMBO_PHY1_P1_BASE + 0x7E) 2398 #define REG_COMBO_PHY1_P1_3F_H (REG_COMBO_PHY1_P1_BASE + 0x7F) 2399 #define REG_COMBO_PHY1_P1_40_L (REG_COMBO_PHY1_P1_BASE + 0x80) 2400 #define REG_COMBO_PHY1_P1_40_H (REG_COMBO_PHY1_P1_BASE + 0x81) 2401 #define REG_COMBO_PHY1_P1_41_L (REG_COMBO_PHY1_P1_BASE + 0x82) 2402 #define REG_COMBO_PHY1_P1_41_H (REG_COMBO_PHY1_P1_BASE + 0x83) 2403 #define REG_COMBO_PHY1_P1_42_L (REG_COMBO_PHY1_P1_BASE + 0x84) 2404 #define REG_COMBO_PHY1_P1_42_H (REG_COMBO_PHY1_P1_BASE + 0x85) 2405 #define REG_COMBO_PHY1_P1_43_L (REG_COMBO_PHY1_P1_BASE + 0x86) 2406 #define REG_COMBO_PHY1_P1_43_H (REG_COMBO_PHY1_P1_BASE + 0x87) 2407 #define REG_COMBO_PHY1_P1_44_L (REG_COMBO_PHY1_P1_BASE + 0x88) 2408 #define REG_COMBO_PHY1_P1_44_H (REG_COMBO_PHY1_P1_BASE + 0x89) 2409 #define REG_COMBO_PHY1_P1_45_L (REG_COMBO_PHY1_P1_BASE + 0x8A) 2410 #define REG_COMBO_PHY1_P1_45_H (REG_COMBO_PHY1_P1_BASE + 0x8B) 2411 #define REG_COMBO_PHY1_P1_46_L (REG_COMBO_PHY1_P1_BASE + 0x8C) 2412 #define REG_COMBO_PHY1_P1_46_H (REG_COMBO_PHY1_P1_BASE + 0x8D) 2413 #define REG_COMBO_PHY1_P1_47_L (REG_COMBO_PHY1_P1_BASE + 0x8E) 2414 #define REG_COMBO_PHY1_P1_47_H (REG_COMBO_PHY1_P1_BASE + 0x8F) 2415 #define REG_COMBO_PHY1_P1_48_L (REG_COMBO_PHY1_P1_BASE + 0x90) 2416 #define REG_COMBO_PHY1_P1_48_H (REG_COMBO_PHY1_P1_BASE + 0x91) 2417 #define REG_COMBO_PHY1_P1_49_L (REG_COMBO_PHY1_P1_BASE + 0x92) 2418 #define REG_COMBO_PHY1_P1_49_H (REG_COMBO_PHY1_P1_BASE + 0x93) 2419 #define REG_COMBO_PHY1_P1_4A_L (REG_COMBO_PHY1_P1_BASE + 0x94) 2420 #define REG_COMBO_PHY1_P1_4A_H (REG_COMBO_PHY1_P1_BASE + 0x95) 2421 #define REG_COMBO_PHY1_P1_4B_L (REG_COMBO_PHY1_P1_BASE + 0x96) 2422 #define REG_COMBO_PHY1_P1_4B_H (REG_COMBO_PHY1_P1_BASE + 0x97) 2423 #define REG_COMBO_PHY1_P1_4C_L (REG_COMBO_PHY1_P1_BASE + 0x98) 2424 #define REG_COMBO_PHY1_P1_4C_H (REG_COMBO_PHY1_P1_BASE + 0x99) 2425 #define REG_COMBO_PHY1_P1_4D_L (REG_COMBO_PHY1_P1_BASE + 0x9A) 2426 #define REG_COMBO_PHY1_P1_4D_H (REG_COMBO_PHY1_P1_BASE + 0x9B) 2427 #define REG_COMBO_PHY1_P1_4E_L (REG_COMBO_PHY1_P1_BASE + 0x9C) 2428 #define REG_COMBO_PHY1_P1_4E_H (REG_COMBO_PHY1_P1_BASE + 0x9D) 2429 #define REG_COMBO_PHY1_P1_4F_L (REG_COMBO_PHY1_P1_BASE + 0x9E) 2430 #define REG_COMBO_PHY1_P1_4F_H (REG_COMBO_PHY1_P1_BASE + 0x9F) 2431 #define REG_COMBO_PHY1_P1_50_L (REG_COMBO_PHY1_P1_BASE + 0xA0) 2432 #define REG_COMBO_PHY1_P1_50_H (REG_COMBO_PHY1_P1_BASE + 0xA1) 2433 #define REG_COMBO_PHY1_P1_51_L (REG_COMBO_PHY1_P1_BASE + 0xA2) 2434 #define REG_COMBO_PHY1_P1_51_H (REG_COMBO_PHY1_P1_BASE + 0xA3) 2435 #define REG_COMBO_PHY1_P1_52_L (REG_COMBO_PHY1_P1_BASE + 0xA4) 2436 #define REG_COMBO_PHY1_P1_52_H (REG_COMBO_PHY1_P1_BASE + 0xA5) 2437 #define REG_COMBO_PHY1_P1_53_L (REG_COMBO_PHY1_P1_BASE + 0xA6) 2438 #define REG_COMBO_PHY1_P1_53_H (REG_COMBO_PHY1_P1_BASE + 0xA7) 2439 #define REG_COMBO_PHY1_P1_54_L (REG_COMBO_PHY1_P1_BASE + 0xA8) 2440 #define REG_COMBO_PHY1_P1_54_H (REG_COMBO_PHY1_P1_BASE + 0xA9) 2441 #define REG_COMBO_PHY1_P1_55_L (REG_COMBO_PHY1_P1_BASE + 0xAA) 2442 #define REG_COMBO_PHY1_P1_55_H (REG_COMBO_PHY1_P1_BASE + 0xAB) 2443 #define REG_COMBO_PHY1_P1_56_L (REG_COMBO_PHY1_P1_BASE + 0xAC) 2444 #define REG_COMBO_PHY1_P1_56_H (REG_COMBO_PHY1_P1_BASE + 0xAD) 2445 #define REG_COMBO_PHY1_P1_57_L (REG_COMBO_PHY1_P1_BASE + 0xAE) 2446 #define REG_COMBO_PHY1_P1_57_H (REG_COMBO_PHY1_P1_BASE + 0xAF) 2447 #define REG_COMBO_PHY1_P1_58_L (REG_COMBO_PHY1_P1_BASE + 0xB0) 2448 #define REG_COMBO_PHY1_P1_58_H (REG_COMBO_PHY1_P1_BASE + 0xB1) 2449 #define REG_COMBO_PHY1_P1_59_L (REG_COMBO_PHY1_P1_BASE + 0xB2) 2450 #define REG_COMBO_PHY1_P1_59_H (REG_COMBO_PHY1_P1_BASE + 0xB3) 2451 #define REG_COMBO_PHY1_P1_5A_L (REG_COMBO_PHY1_P1_BASE + 0xB4) 2452 #define REG_COMBO_PHY1_P1_5A_H (REG_COMBO_PHY1_P1_BASE + 0xB5) 2453 #define REG_COMBO_PHY1_P1_5B_L (REG_COMBO_PHY1_P1_BASE + 0xB6) 2454 #define REG_COMBO_PHY1_P1_5B_H (REG_COMBO_PHY1_P1_BASE + 0xB7) 2455 #define REG_COMBO_PHY1_P1_5C_L (REG_COMBO_PHY1_P1_BASE + 0xB8) 2456 #define REG_COMBO_PHY1_P1_5C_H (REG_COMBO_PHY1_P1_BASE + 0xB9) 2457 #define REG_COMBO_PHY1_P1_5D_L (REG_COMBO_PHY1_P1_BASE + 0xBA) 2458 #define REG_COMBO_PHY1_P1_5D_H (REG_COMBO_PHY1_P1_BASE + 0xBB) 2459 #define REG_COMBO_PHY1_P1_5E_L (REG_COMBO_PHY1_P1_BASE + 0xBC) 2460 #define REG_COMBO_PHY1_P1_5E_H (REG_COMBO_PHY1_P1_BASE + 0xBD) 2461 #define REG_COMBO_PHY1_P1_5F_L (REG_COMBO_PHY1_P1_BASE + 0xBE) 2462 #define REG_COMBO_PHY1_P1_5F_H (REG_COMBO_PHY1_P1_BASE + 0xBF) 2463 #define REG_COMBO_PHY1_P1_60_L (REG_COMBO_PHY1_P1_BASE + 0xC0) 2464 #define REG_COMBO_PHY1_P1_60_H (REG_COMBO_PHY1_P1_BASE + 0xC1) 2465 #define REG_COMBO_PHY1_P1_61_L (REG_COMBO_PHY1_P1_BASE + 0xC2) 2466 #define REG_COMBO_PHY1_P1_61_H (REG_COMBO_PHY1_P1_BASE + 0xC3) 2467 #define REG_COMBO_PHY1_P1_62_L (REG_COMBO_PHY1_P1_BASE + 0xC4) 2468 #define REG_COMBO_PHY1_P1_62_H (REG_COMBO_PHY1_P1_BASE + 0xC5) 2469 #define REG_COMBO_PHY1_P1_63_L (REG_COMBO_PHY1_P1_BASE + 0xC6) 2470 #define REG_COMBO_PHY1_P1_63_H (REG_COMBO_PHY1_P1_BASE + 0xC7) 2471 #define REG_COMBO_PHY1_P1_64_L (REG_COMBO_PHY1_P1_BASE + 0xC8) 2472 #define REG_COMBO_PHY1_P1_64_H (REG_COMBO_PHY1_P1_BASE + 0xC9) 2473 #define REG_COMBO_PHY1_P1_65_L (REG_COMBO_PHY1_P1_BASE + 0xCA) 2474 #define REG_COMBO_PHY1_P1_65_H (REG_COMBO_PHY1_P1_BASE + 0xCB) 2475 #define REG_COMBO_PHY1_P1_66_L (REG_COMBO_PHY1_P1_BASE + 0xCC) 2476 #define REG_COMBO_PHY1_P1_66_H (REG_COMBO_PHY1_P1_BASE + 0xCD) 2477 #define REG_COMBO_PHY1_P1_67_L (REG_COMBO_PHY1_P1_BASE + 0xCE) 2478 #define REG_COMBO_PHY1_P1_67_H (REG_COMBO_PHY1_P1_BASE + 0xCF) 2479 #define REG_COMBO_PHY1_P1_68_L (REG_COMBO_PHY1_P1_BASE + 0xD0) 2480 #define REG_COMBO_PHY1_P1_68_H (REG_COMBO_PHY1_P1_BASE + 0xD1) 2481 #define REG_COMBO_PHY1_P1_69_L (REG_COMBO_PHY1_P1_BASE + 0xD2) 2482 #define REG_COMBO_PHY1_P1_69_H (REG_COMBO_PHY1_P1_BASE + 0xD3) 2483 #define REG_COMBO_PHY1_P1_6A_L (REG_COMBO_PHY1_P1_BASE + 0xD4) 2484 #define REG_COMBO_PHY1_P1_6A_H (REG_COMBO_PHY1_P1_BASE + 0xD5) 2485 #define REG_COMBO_PHY1_P1_6B_L (REG_COMBO_PHY1_P1_BASE + 0xD6) 2486 #define REG_COMBO_PHY1_P1_6B_H (REG_COMBO_PHY1_P1_BASE + 0xD7) 2487 #define REG_COMBO_PHY1_P1_6C_L (REG_COMBO_PHY1_P1_BASE + 0xD8) 2488 #define REG_COMBO_PHY1_P1_6C_H (REG_COMBO_PHY1_P1_BASE + 0xD9) 2489 #define REG_COMBO_PHY1_P1_6D_L (REG_COMBO_PHY1_P1_BASE + 0xDA) 2490 #define REG_COMBO_PHY1_P1_6D_H (REG_COMBO_PHY1_P1_BASE + 0xDB) 2491 #define REG_COMBO_PHY1_P1_6E_L (REG_COMBO_PHY1_P1_BASE + 0xDC) 2492 #define REG_COMBO_PHY1_P1_6E_H (REG_COMBO_PHY1_P1_BASE + 0xDD) 2493 #define REG_COMBO_PHY1_P1_6F_L (REG_COMBO_PHY1_P1_BASE + 0xDE) 2494 #define REG_COMBO_PHY1_P1_6F_H (REG_COMBO_PHY1_P1_BASE + 0xDF) 2495 #define REG_COMBO_PHY1_P1_70_L (REG_COMBO_PHY1_P1_BASE + 0xE0) 2496 #define REG_COMBO_PHY1_P1_70_H (REG_COMBO_PHY1_P1_BASE + 0xE1) 2497 #define REG_COMBO_PHY1_P1_71_L (REG_COMBO_PHY1_P1_BASE + 0xE2) 2498 #define REG_COMBO_PHY1_P1_71_H (REG_COMBO_PHY1_P1_BASE + 0xE3) 2499 #define REG_COMBO_PHY1_P1_72_L (REG_COMBO_PHY1_P1_BASE + 0xE4) 2500 #define REG_COMBO_PHY1_P1_72_H (REG_COMBO_PHY1_P1_BASE + 0xE5) 2501 #define REG_COMBO_PHY1_P1_73_L (REG_COMBO_PHY1_P1_BASE + 0xE6) 2502 #define REG_COMBO_PHY1_P1_73_H (REG_COMBO_PHY1_P1_BASE + 0xE7) 2503 #define REG_COMBO_PHY1_P1_74_L (REG_COMBO_PHY1_P1_BASE + 0xE8) 2504 #define REG_COMBO_PHY1_P1_74_H (REG_COMBO_PHY1_P1_BASE + 0xE9) 2505 #define REG_COMBO_PHY1_P1_75_L (REG_COMBO_PHY1_P1_BASE + 0xEA) 2506 #define REG_COMBO_PHY1_P1_75_H (REG_COMBO_PHY1_P1_BASE + 0xEB) 2507 #define REG_COMBO_PHY1_P1_76_L (REG_COMBO_PHY1_P1_BASE + 0xEC) 2508 #define REG_COMBO_PHY1_P1_76_H (REG_COMBO_PHY1_P1_BASE + 0xED) 2509 #define REG_COMBO_PHY1_P1_77_L (REG_COMBO_PHY1_P1_BASE + 0xEE) 2510 #define REG_COMBO_PHY1_P1_77_H (REG_COMBO_PHY1_P1_BASE + 0xEF) 2511 #define REG_COMBO_PHY1_P1_78_L (REG_COMBO_PHY1_P1_BASE + 0xF0) 2512 #define REG_COMBO_PHY1_P1_78_H (REG_COMBO_PHY1_P1_BASE + 0xF1) 2513 #define REG_COMBO_PHY1_P1_79_L (REG_COMBO_PHY1_P1_BASE + 0xF2) 2514 #define REG_COMBO_PHY1_P1_79_H (REG_COMBO_PHY1_P1_BASE + 0xF3) 2515 #define REG_COMBO_PHY1_P1_7A_L (REG_COMBO_PHY1_P1_BASE + 0xF4) 2516 #define REG_COMBO_PHY1_P1_7A_H (REG_COMBO_PHY1_P1_BASE + 0xF5) 2517 #define REG_COMBO_PHY1_P1_7B_L (REG_COMBO_PHY1_P1_BASE + 0xF6) 2518 #define REG_COMBO_PHY1_P1_7B_H (REG_COMBO_PHY1_P1_BASE + 0xF7) 2519 #define REG_COMBO_PHY1_P1_7C_L (REG_COMBO_PHY1_P1_BASE + 0xF8) 2520 #define REG_COMBO_PHY1_P1_7C_H (REG_COMBO_PHY1_P1_BASE + 0xF9) 2521 #define REG_COMBO_PHY1_P1_7D_L (REG_COMBO_PHY1_P1_BASE + 0xFA) 2522 #define REG_COMBO_PHY1_P1_7D_H (REG_COMBO_PHY1_P1_BASE + 0xFB) 2523 #define REG_COMBO_PHY1_P1_7E_L (REG_COMBO_PHY1_P1_BASE + 0xFC) 2524 #define REG_COMBO_PHY1_P1_7E_H (REG_COMBO_PHY1_P1_BASE + 0xFD) 2525 #define REG_COMBO_PHY1_P1_7F_L (REG_COMBO_PHY1_P1_BASE + 0xFE) 2526 #define REG_COMBO_PHY1_P1_7F_H (REG_COMBO_PHY1_P1_BASE + 0xFF) 2527 2528 // COMBO_PHY0_P2 2529 #define REG_COMBO_PHY0_P2_00_L (REG_COMBO_PHY0_P2_BASE + 0x00) 2530 #define REG_COMBO_PHY0_P2_00_H (REG_COMBO_PHY0_P2_BASE + 0x01) 2531 #define REG_COMBO_PHY0_P2_01_L (REG_COMBO_PHY0_P2_BASE + 0x02) 2532 #define REG_COMBO_PHY0_P2_01_H (REG_COMBO_PHY0_P2_BASE + 0x03) 2533 #define REG_COMBO_PHY0_P2_02_L (REG_COMBO_PHY0_P2_BASE + 0x04) 2534 #define REG_COMBO_PHY0_P2_02_H (REG_COMBO_PHY0_P2_BASE + 0x05) 2535 #define REG_COMBO_PHY0_P2_03_L (REG_COMBO_PHY0_P2_BASE + 0x06) 2536 #define REG_COMBO_PHY0_P2_03_H (REG_COMBO_PHY0_P2_BASE + 0x07) 2537 #define REG_COMBO_PHY0_P2_04_L (REG_COMBO_PHY0_P2_BASE + 0x08) 2538 #define REG_COMBO_PHY0_P2_04_H (REG_COMBO_PHY0_P2_BASE + 0x09) 2539 #define REG_COMBO_PHY0_P2_05_L (REG_COMBO_PHY0_P2_BASE + 0x0A) 2540 #define REG_COMBO_PHY0_P2_05_H (REG_COMBO_PHY0_P2_BASE + 0x0B) 2541 #define REG_COMBO_PHY0_P2_06_L (REG_COMBO_PHY0_P2_BASE + 0x0C) 2542 #define REG_COMBO_PHY0_P2_06_H (REG_COMBO_PHY0_P2_BASE + 0x0D) 2543 #define REG_COMBO_PHY0_P2_07_L (REG_COMBO_PHY0_P2_BASE + 0x0E) 2544 #define REG_COMBO_PHY0_P2_07_H (REG_COMBO_PHY0_P2_BASE + 0x0F) 2545 #define REG_COMBO_PHY0_P2_08_L (REG_COMBO_PHY0_P2_BASE + 0x10) 2546 #define REG_COMBO_PHY0_P2_08_H (REG_COMBO_PHY0_P2_BASE + 0x11) 2547 #define REG_COMBO_PHY0_P2_09_L (REG_COMBO_PHY0_P2_BASE + 0x12) 2548 #define REG_COMBO_PHY0_P2_09_H (REG_COMBO_PHY0_P2_BASE + 0x13) 2549 #define REG_COMBO_PHY0_P2_0A_L (REG_COMBO_PHY0_P2_BASE + 0x14) 2550 #define REG_COMBO_PHY0_P2_0A_H (REG_COMBO_PHY0_P2_BASE + 0x15) 2551 #define REG_COMBO_PHY0_P2_0B_L (REG_COMBO_PHY0_P2_BASE + 0x16) 2552 #define REG_COMBO_PHY0_P2_0B_H (REG_COMBO_PHY0_P2_BASE + 0x17) 2553 #define REG_COMBO_PHY0_P2_0C_L (REG_COMBO_PHY0_P2_BASE + 0x18) 2554 #define REG_COMBO_PHY0_P2_0C_H (REG_COMBO_PHY0_P2_BASE + 0x19) 2555 #define REG_COMBO_PHY0_P2_0D_L (REG_COMBO_PHY0_P2_BASE + 0x1A) 2556 #define REG_COMBO_PHY0_P2_0D_H (REG_COMBO_PHY0_P2_BASE + 0x1B) 2557 #define REG_COMBO_PHY0_P2_0E_L (REG_COMBO_PHY0_P2_BASE + 0x1C) 2558 #define REG_COMBO_PHY0_P2_0E_H (REG_COMBO_PHY0_P2_BASE + 0x1D) 2559 #define REG_COMBO_PHY0_P2_0F_L (REG_COMBO_PHY0_P2_BASE + 0x1E) 2560 #define REG_COMBO_PHY0_P2_0F_H (REG_COMBO_PHY0_P2_BASE + 0x1F) 2561 #define REG_COMBO_PHY0_P2_10_L (REG_COMBO_PHY0_P2_BASE + 0x20) 2562 #define REG_COMBO_PHY0_P2_10_H (REG_COMBO_PHY0_P2_BASE + 0x21) 2563 #define REG_COMBO_PHY0_P2_11_L (REG_COMBO_PHY0_P2_BASE + 0x22) 2564 #define REG_COMBO_PHY0_P2_11_H (REG_COMBO_PHY0_P2_BASE + 0x23) 2565 #define REG_COMBO_PHY0_P2_12_L (REG_COMBO_PHY0_P2_BASE + 0x24) 2566 #define REG_COMBO_PHY0_P2_12_H (REG_COMBO_PHY0_P2_BASE + 0x25) 2567 #define REG_COMBO_PHY0_P2_13_L (REG_COMBO_PHY0_P2_BASE + 0x26) 2568 #define REG_COMBO_PHY0_P2_13_H (REG_COMBO_PHY0_P2_BASE + 0x27) 2569 #define REG_COMBO_PHY0_P2_14_L (REG_COMBO_PHY0_P2_BASE + 0x28) 2570 #define REG_COMBO_PHY0_P2_14_H (REG_COMBO_PHY0_P2_BASE + 0x29) 2571 #define REG_COMBO_PHY0_P2_15_L (REG_COMBO_PHY0_P2_BASE + 0x2A) 2572 #define REG_COMBO_PHY0_P2_15_H (REG_COMBO_PHY0_P2_BASE + 0x2B) 2573 #define REG_COMBO_PHY0_P2_16_L (REG_COMBO_PHY0_P2_BASE + 0x2C) 2574 #define REG_COMBO_PHY0_P2_16_H (REG_COMBO_PHY0_P2_BASE + 0x2D) 2575 #define REG_COMBO_PHY0_P2_17_L (REG_COMBO_PHY0_P2_BASE + 0x2E) 2576 #define REG_COMBO_PHY0_P2_17_H (REG_COMBO_PHY0_P2_BASE + 0x2F) 2577 #define REG_COMBO_PHY0_P2_18_L (REG_COMBO_PHY0_P2_BASE + 0x30) 2578 #define REG_COMBO_PHY0_P2_18_H (REG_COMBO_PHY0_P2_BASE + 0x31) 2579 #define REG_COMBO_PHY0_P2_19_L (REG_COMBO_PHY0_P2_BASE + 0x32) 2580 #define REG_COMBO_PHY0_P2_19_H (REG_COMBO_PHY0_P2_BASE + 0x33) 2581 #define REG_COMBO_PHY0_P2_1A_L (REG_COMBO_PHY0_P2_BASE + 0x34) 2582 #define REG_COMBO_PHY0_P2_1A_H (REG_COMBO_PHY0_P2_BASE + 0x35) 2583 #define REG_COMBO_PHY0_P2_1B_L (REG_COMBO_PHY0_P2_BASE + 0x36) 2584 #define REG_COMBO_PHY0_P2_1B_H (REG_COMBO_PHY0_P2_BASE + 0x37) 2585 #define REG_COMBO_PHY0_P2_1C_L (REG_COMBO_PHY0_P2_BASE + 0x38) 2586 #define REG_COMBO_PHY0_P2_1C_H (REG_COMBO_PHY0_P2_BASE + 0x39) 2587 #define REG_COMBO_PHY0_P2_1D_L (REG_COMBO_PHY0_P2_BASE + 0x3A) 2588 #define REG_COMBO_PHY0_P2_1D_H (REG_COMBO_PHY0_P2_BASE + 0x3B) 2589 #define REG_COMBO_PHY0_P2_1E_L (REG_COMBO_PHY0_P2_BASE + 0x3C) 2590 #define REG_COMBO_PHY0_P2_1E_H (REG_COMBO_PHY0_P2_BASE + 0x3D) 2591 #define REG_COMBO_PHY0_P2_1F_L (REG_COMBO_PHY0_P2_BASE + 0x3E) 2592 #define REG_COMBO_PHY0_P2_1F_H (REG_COMBO_PHY0_P2_BASE + 0x3F) 2593 #define REG_COMBO_PHY0_P2_20_L (REG_COMBO_PHY0_P2_BASE + 0x40) 2594 #define REG_COMBO_PHY0_P2_20_H (REG_COMBO_PHY0_P2_BASE + 0x41) 2595 #define REG_COMBO_PHY0_P2_21_L (REG_COMBO_PHY0_P2_BASE + 0x42) 2596 #define REG_COMBO_PHY0_P2_21_H (REG_COMBO_PHY0_P2_BASE + 0x43) 2597 #define REG_COMBO_PHY0_P2_22_L (REG_COMBO_PHY0_P2_BASE + 0x44) 2598 #define REG_COMBO_PHY0_P2_22_H (REG_COMBO_PHY0_P2_BASE + 0x45) 2599 #define REG_COMBO_PHY0_P2_23_L (REG_COMBO_PHY0_P2_BASE + 0x46) 2600 #define REG_COMBO_PHY0_P2_23_H (REG_COMBO_PHY0_P2_BASE + 0x47) 2601 #define REG_COMBO_PHY0_P2_24_L (REG_COMBO_PHY0_P2_BASE + 0x48) 2602 #define REG_COMBO_PHY0_P2_24_H (REG_COMBO_PHY0_P2_BASE + 0x49) 2603 #define REG_COMBO_PHY0_P2_25_L (REG_COMBO_PHY0_P2_BASE + 0x4A) 2604 #define REG_COMBO_PHY0_P2_25_H (REG_COMBO_PHY0_P2_BASE + 0x4B) 2605 #define REG_COMBO_PHY0_P2_26_L (REG_COMBO_PHY0_P2_BASE + 0x4C) 2606 #define REG_COMBO_PHY0_P2_26_H (REG_COMBO_PHY0_P2_BASE + 0x4D) 2607 #define REG_COMBO_PHY0_P2_27_L (REG_COMBO_PHY0_P2_BASE + 0x4E) 2608 #define REG_COMBO_PHY0_P2_27_H (REG_COMBO_PHY0_P2_BASE + 0x4F) 2609 #define REG_COMBO_PHY0_P2_28_L (REG_COMBO_PHY0_P2_BASE + 0x50) 2610 #define REG_COMBO_PHY0_P2_28_H (REG_COMBO_PHY0_P2_BASE + 0x51) 2611 #define REG_COMBO_PHY0_P2_29_L (REG_COMBO_PHY0_P2_BASE + 0x52) 2612 #define REG_COMBO_PHY0_P2_29_H (REG_COMBO_PHY0_P2_BASE + 0x53) 2613 #define REG_COMBO_PHY0_P2_2A_L (REG_COMBO_PHY0_P2_BASE + 0x54) 2614 #define REG_COMBO_PHY0_P2_2A_H (REG_COMBO_PHY0_P2_BASE + 0x55) 2615 #define REG_COMBO_PHY0_P2_2B_L (REG_COMBO_PHY0_P2_BASE + 0x56) 2616 #define REG_COMBO_PHY0_P2_2B_H (REG_COMBO_PHY0_P2_BASE + 0x57) 2617 #define REG_COMBO_PHY0_P2_2C_L (REG_COMBO_PHY0_P2_BASE + 0x58) 2618 #define REG_COMBO_PHY0_P2_2C_H (REG_COMBO_PHY0_P2_BASE + 0x59) 2619 #define REG_COMBO_PHY0_P2_2D_L (REG_COMBO_PHY0_P2_BASE + 0x5A) 2620 #define REG_COMBO_PHY0_P2_2D_H (REG_COMBO_PHY0_P2_BASE + 0x5B) 2621 #define REG_COMBO_PHY0_P2_2E_L (REG_COMBO_PHY0_P2_BASE + 0x5C) 2622 #define REG_COMBO_PHY0_P2_2E_H (REG_COMBO_PHY0_P2_BASE + 0x5D) 2623 #define REG_COMBO_PHY0_P2_2F_L (REG_COMBO_PHY0_P2_BASE + 0x5E) 2624 #define REG_COMBO_PHY0_P2_2F_H (REG_COMBO_PHY0_P2_BASE + 0x5F) 2625 #define REG_COMBO_PHY0_P2_30_L (REG_COMBO_PHY0_P2_BASE + 0x60) 2626 #define REG_COMBO_PHY0_P2_30_H (REG_COMBO_PHY0_P2_BASE + 0x61) 2627 #define REG_COMBO_PHY0_P2_31_L (REG_COMBO_PHY0_P2_BASE + 0x62) 2628 #define REG_COMBO_PHY0_P2_31_H (REG_COMBO_PHY0_P2_BASE + 0x63) 2629 #define REG_COMBO_PHY0_P2_32_L (REG_COMBO_PHY0_P2_BASE + 0x64) 2630 #define REG_COMBO_PHY0_P2_32_H (REG_COMBO_PHY0_P2_BASE + 0x65) 2631 #define REG_COMBO_PHY0_P2_33_L (REG_COMBO_PHY0_P2_BASE + 0x66) 2632 #define REG_COMBO_PHY0_P2_33_H (REG_COMBO_PHY0_P2_BASE + 0x67) 2633 #define REG_COMBO_PHY0_P2_34_L (REG_COMBO_PHY0_P2_BASE + 0x68) 2634 #define REG_COMBO_PHY0_P2_34_H (REG_COMBO_PHY0_P2_BASE + 0x69) 2635 #define REG_COMBO_PHY0_P2_35_L (REG_COMBO_PHY0_P2_BASE + 0x6A) 2636 #define REG_COMBO_PHY0_P2_35_H (REG_COMBO_PHY0_P2_BASE + 0x6B) 2637 #define REG_COMBO_PHY0_P2_36_L (REG_COMBO_PHY0_P2_BASE + 0x6C) 2638 #define REG_COMBO_PHY0_P2_36_H (REG_COMBO_PHY0_P2_BASE + 0x6D) 2639 #define REG_COMBO_PHY0_P2_37_L (REG_COMBO_PHY0_P2_BASE + 0x6E) 2640 #define REG_COMBO_PHY0_P2_37_H (REG_COMBO_PHY0_P2_BASE + 0x6F) 2641 #define REG_COMBO_PHY0_P2_38_L (REG_COMBO_PHY0_P2_BASE + 0x70) 2642 #define REG_COMBO_PHY0_P2_38_H (REG_COMBO_PHY0_P2_BASE + 0x71) 2643 #define REG_COMBO_PHY0_P2_39_L (REG_COMBO_PHY0_P2_BASE + 0x72) 2644 #define REG_COMBO_PHY0_P2_39_H (REG_COMBO_PHY0_P2_BASE + 0x73) 2645 #define REG_COMBO_PHY0_P2_3A_L (REG_COMBO_PHY0_P2_BASE + 0x74) 2646 #define REG_COMBO_PHY0_P2_3A_H (REG_COMBO_PHY0_P2_BASE + 0x75) 2647 #define REG_COMBO_PHY0_P2_3B_L (REG_COMBO_PHY0_P2_BASE + 0x76) 2648 #define REG_COMBO_PHY0_P2_3B_H (REG_COMBO_PHY0_P2_BASE + 0x77) 2649 #define REG_COMBO_PHY0_P2_3C_L (REG_COMBO_PHY0_P2_BASE + 0x78) 2650 #define REG_COMBO_PHY0_P2_3C_H (REG_COMBO_PHY0_P2_BASE + 0x79) 2651 #define REG_COMBO_PHY0_P2_3D_L (REG_COMBO_PHY0_P2_BASE + 0x7A) 2652 #define REG_COMBO_PHY0_P2_3D_H (REG_COMBO_PHY0_P2_BASE + 0x7B) 2653 #define REG_COMBO_PHY0_P2_3E_L (REG_COMBO_PHY0_P2_BASE + 0x7C) 2654 #define REG_COMBO_PHY0_P2_3E_H (REG_COMBO_PHY0_P2_BASE + 0x7D) 2655 #define REG_COMBO_PHY0_P2_3F_L (REG_COMBO_PHY0_P2_BASE + 0x7E) 2656 #define REG_COMBO_PHY0_P2_3F_H (REG_COMBO_PHY0_P2_BASE + 0x7F) 2657 #define REG_COMBO_PHY0_P2_40_L (REG_COMBO_PHY0_P2_BASE + 0x80) 2658 #define REG_COMBO_PHY0_P2_40_H (REG_COMBO_PHY0_P2_BASE + 0x81) 2659 #define REG_COMBO_PHY0_P2_41_L (REG_COMBO_PHY0_P2_BASE + 0x82) 2660 #define REG_COMBO_PHY0_P2_41_H (REG_COMBO_PHY0_P2_BASE + 0x83) 2661 #define REG_COMBO_PHY0_P2_42_L (REG_COMBO_PHY0_P2_BASE + 0x84) 2662 #define REG_COMBO_PHY0_P2_42_H (REG_COMBO_PHY0_P2_BASE + 0x85) 2663 #define REG_COMBO_PHY0_P2_43_L (REG_COMBO_PHY0_P2_BASE + 0x86) 2664 #define REG_COMBO_PHY0_P2_43_H (REG_COMBO_PHY0_P2_BASE + 0x87) 2665 #define REG_COMBO_PHY0_P2_44_L (REG_COMBO_PHY0_P2_BASE + 0x88) 2666 #define REG_COMBO_PHY0_P2_44_H (REG_COMBO_PHY0_P2_BASE + 0x89) 2667 #define REG_COMBO_PHY0_P2_45_L (REG_COMBO_PHY0_P2_BASE + 0x8A) 2668 #define REG_COMBO_PHY0_P2_45_H (REG_COMBO_PHY0_P2_BASE + 0x8B) 2669 #define REG_COMBO_PHY0_P2_46_L (REG_COMBO_PHY0_P2_BASE + 0x8C) 2670 #define REG_COMBO_PHY0_P2_46_H (REG_COMBO_PHY0_P2_BASE + 0x8D) 2671 #define REG_COMBO_PHY0_P2_47_L (REG_COMBO_PHY0_P2_BASE + 0x8E) 2672 #define REG_COMBO_PHY0_P2_47_H (REG_COMBO_PHY0_P2_BASE + 0x8F) 2673 #define REG_COMBO_PHY0_P2_48_L (REG_COMBO_PHY0_P2_BASE + 0x90) 2674 #define REG_COMBO_PHY0_P2_48_H (REG_COMBO_PHY0_P2_BASE + 0x91) 2675 #define REG_COMBO_PHY0_P2_49_L (REG_COMBO_PHY0_P2_BASE + 0x92) 2676 #define REG_COMBO_PHY0_P2_49_H (REG_COMBO_PHY0_P2_BASE + 0x93) 2677 #define REG_COMBO_PHY0_P2_4A_L (REG_COMBO_PHY0_P2_BASE + 0x94) 2678 #define REG_COMBO_PHY0_P2_4A_H (REG_COMBO_PHY0_P2_BASE + 0x95) 2679 #define REG_COMBO_PHY0_P2_4B_L (REG_COMBO_PHY0_P2_BASE + 0x96) 2680 #define REG_COMBO_PHY0_P2_4B_H (REG_COMBO_PHY0_P2_BASE + 0x97) 2681 #define REG_COMBO_PHY0_P2_4C_L (REG_COMBO_PHY0_P2_BASE + 0x98) 2682 #define REG_COMBO_PHY0_P2_4C_H (REG_COMBO_PHY0_P2_BASE + 0x99) 2683 #define REG_COMBO_PHY0_P2_4D_L (REG_COMBO_PHY0_P2_BASE + 0x9A) 2684 #define REG_COMBO_PHY0_P2_4D_H (REG_COMBO_PHY0_P2_BASE + 0x9B) 2685 #define REG_COMBO_PHY0_P2_4E_L (REG_COMBO_PHY0_P2_BASE + 0x9C) 2686 #define REG_COMBO_PHY0_P2_4E_H (REG_COMBO_PHY0_P2_BASE + 0x9D) 2687 #define REG_COMBO_PHY0_P2_4F_L (REG_COMBO_PHY0_P2_BASE + 0x9E) 2688 #define REG_COMBO_PHY0_P2_4F_H (REG_COMBO_PHY0_P2_BASE + 0x9F) 2689 #define REG_COMBO_PHY0_P2_50_L (REG_COMBO_PHY0_P2_BASE + 0xA0) 2690 #define REG_COMBO_PHY0_P2_50_H (REG_COMBO_PHY0_P2_BASE + 0xA1) 2691 #define REG_COMBO_PHY0_P2_51_L (REG_COMBO_PHY0_P2_BASE + 0xA2) 2692 #define REG_COMBO_PHY0_P2_51_H (REG_COMBO_PHY0_P2_BASE + 0xA3) 2693 #define REG_COMBO_PHY0_P2_52_L (REG_COMBO_PHY0_P2_BASE + 0xA4) 2694 #define REG_COMBO_PHY0_P2_52_H (REG_COMBO_PHY0_P2_BASE + 0xA5) 2695 #define REG_COMBO_PHY0_P2_53_L (REG_COMBO_PHY0_P2_BASE + 0xA6) 2696 #define REG_COMBO_PHY0_P2_53_H (REG_COMBO_PHY0_P2_BASE + 0xA7) 2697 #define REG_COMBO_PHY0_P2_54_L (REG_COMBO_PHY0_P2_BASE + 0xA8) 2698 #define REG_COMBO_PHY0_P2_54_H (REG_COMBO_PHY0_P2_BASE + 0xA9) 2699 #define REG_COMBO_PHY0_P2_55_L (REG_COMBO_PHY0_P2_BASE + 0xAA) 2700 #define REG_COMBO_PHY0_P2_55_H (REG_COMBO_PHY0_P2_BASE + 0xAB) 2701 #define REG_COMBO_PHY0_P2_56_L (REG_COMBO_PHY0_P2_BASE + 0xAC) 2702 #define REG_COMBO_PHY0_P2_56_H (REG_COMBO_PHY0_P2_BASE + 0xAD) 2703 #define REG_COMBO_PHY0_P2_57_L (REG_COMBO_PHY0_P2_BASE + 0xAE) 2704 #define REG_COMBO_PHY0_P2_57_H (REG_COMBO_PHY0_P2_BASE + 0xAF) 2705 #define REG_COMBO_PHY0_P2_58_L (REG_COMBO_PHY0_P2_BASE + 0xB0) 2706 #define REG_COMBO_PHY0_P2_58_H (REG_COMBO_PHY0_P2_BASE + 0xB1) 2707 #define REG_COMBO_PHY0_P2_59_L (REG_COMBO_PHY0_P2_BASE + 0xB2) 2708 #define REG_COMBO_PHY0_P2_59_H (REG_COMBO_PHY0_P2_BASE + 0xB3) 2709 #define REG_COMBO_PHY0_P2_5A_L (REG_COMBO_PHY0_P2_BASE + 0xB4) 2710 #define REG_COMBO_PHY0_P2_5A_H (REG_COMBO_PHY0_P2_BASE + 0xB5) 2711 #define REG_COMBO_PHY0_P2_5B_L (REG_COMBO_PHY0_P2_BASE + 0xB6) 2712 #define REG_COMBO_PHY0_P2_5B_H (REG_COMBO_PHY0_P2_BASE + 0xB7) 2713 #define REG_COMBO_PHY0_P2_5C_L (REG_COMBO_PHY0_P2_BASE + 0xB8) 2714 #define REG_COMBO_PHY0_P2_5C_H (REG_COMBO_PHY0_P2_BASE + 0xB9) 2715 #define REG_COMBO_PHY0_P2_5D_L (REG_COMBO_PHY0_P2_BASE + 0xBA) 2716 #define REG_COMBO_PHY0_P2_5D_H (REG_COMBO_PHY0_P2_BASE + 0xBB) 2717 #define REG_COMBO_PHY0_P2_5E_L (REG_COMBO_PHY0_P2_BASE + 0xBC) 2718 #define REG_COMBO_PHY0_P2_5E_H (REG_COMBO_PHY0_P2_BASE + 0xBD) 2719 #define REG_COMBO_PHY0_P2_5F_L (REG_COMBO_PHY0_P2_BASE + 0xBE) 2720 #define REG_COMBO_PHY0_P2_5F_H (REG_COMBO_PHY0_P2_BASE + 0xBF) 2721 #define REG_COMBO_PHY0_P2_60_L (REG_COMBO_PHY0_P2_BASE + 0xC0) 2722 #define REG_COMBO_PHY0_P2_60_H (REG_COMBO_PHY0_P2_BASE + 0xC1) 2723 #define REG_COMBO_PHY0_P2_61_L (REG_COMBO_PHY0_P2_BASE + 0xC2) 2724 #define REG_COMBO_PHY0_P2_61_H (REG_COMBO_PHY0_P2_BASE + 0xC3) 2725 #define REG_COMBO_PHY0_P2_62_L (REG_COMBO_PHY0_P2_BASE + 0xC4) 2726 #define REG_COMBO_PHY0_P2_62_H (REG_COMBO_PHY0_P2_BASE + 0xC5) 2727 #define REG_COMBO_PHY0_P2_63_L (REG_COMBO_PHY0_P2_BASE + 0xC6) 2728 #define REG_COMBO_PHY0_P2_63_H (REG_COMBO_PHY0_P2_BASE + 0xC7) 2729 #define REG_COMBO_PHY0_P2_64_L (REG_COMBO_PHY0_P2_BASE + 0xC8) 2730 #define REG_COMBO_PHY0_P2_64_H (REG_COMBO_PHY0_P2_BASE + 0xC9) 2731 #define REG_COMBO_PHY0_P2_65_L (REG_COMBO_PHY0_P2_BASE + 0xCA) 2732 #define REG_COMBO_PHY0_P2_65_H (REG_COMBO_PHY0_P2_BASE + 0xCB) 2733 #define REG_COMBO_PHY0_P2_66_L (REG_COMBO_PHY0_P2_BASE + 0xCC) 2734 #define REG_COMBO_PHY0_P2_66_H (REG_COMBO_PHY0_P2_BASE + 0xCD) 2735 #define REG_COMBO_PHY0_P2_67_L (REG_COMBO_PHY0_P2_BASE + 0xCE) 2736 #define REG_COMBO_PHY0_P2_67_H (REG_COMBO_PHY0_P2_BASE + 0xCF) 2737 #define REG_COMBO_PHY0_P2_68_L (REG_COMBO_PHY0_P2_BASE + 0xD0) 2738 #define REG_COMBO_PHY0_P2_68_H (REG_COMBO_PHY0_P2_BASE + 0xD1) 2739 #define REG_COMBO_PHY0_P2_69_L (REG_COMBO_PHY0_P2_BASE + 0xD2) 2740 #define REG_COMBO_PHY0_P2_69_H (REG_COMBO_PHY0_P2_BASE + 0xD3) 2741 #define REG_COMBO_PHY0_P2_6A_L (REG_COMBO_PHY0_P2_BASE + 0xD4) 2742 #define REG_COMBO_PHY0_P2_6A_H (REG_COMBO_PHY0_P2_BASE + 0xD5) 2743 #define REG_COMBO_PHY0_P2_6B_L (REG_COMBO_PHY0_P2_BASE + 0xD6) 2744 #define REG_COMBO_PHY0_P2_6B_H (REG_COMBO_PHY0_P2_BASE + 0xD7) 2745 #define REG_COMBO_PHY0_P2_6C_L (REG_COMBO_PHY0_P2_BASE + 0xD8) 2746 #define REG_COMBO_PHY0_P2_6C_H (REG_COMBO_PHY0_P2_BASE + 0xD9) 2747 #define REG_COMBO_PHY0_P2_6D_L (REG_COMBO_PHY0_P2_BASE + 0xDA) 2748 #define REG_COMBO_PHY0_P2_6D_H (REG_COMBO_PHY0_P2_BASE + 0xDB) 2749 #define REG_COMBO_PHY0_P2_6E_L (REG_COMBO_PHY0_P2_BASE + 0xDC) 2750 #define REG_COMBO_PHY0_P2_6E_H (REG_COMBO_PHY0_P2_BASE + 0xDD) 2751 #define REG_COMBO_PHY0_P2_6F_L (REG_COMBO_PHY0_P2_BASE + 0xDE) 2752 #define REG_COMBO_PHY0_P2_6F_H (REG_COMBO_PHY0_P2_BASE + 0xDF) 2753 #define REG_COMBO_PHY0_P2_70_L (REG_COMBO_PHY0_P2_BASE + 0xE0) 2754 #define REG_COMBO_PHY0_P2_70_H (REG_COMBO_PHY0_P2_BASE + 0xE1) 2755 #define REG_COMBO_PHY0_P2_71_L (REG_COMBO_PHY0_P2_BASE + 0xE2) 2756 #define REG_COMBO_PHY0_P2_71_H (REG_COMBO_PHY0_P2_BASE + 0xE3) 2757 #define REG_COMBO_PHY0_P2_72_L (REG_COMBO_PHY0_P2_BASE + 0xE4) 2758 #define REG_COMBO_PHY0_P2_72_H (REG_COMBO_PHY0_P2_BASE + 0xE5) 2759 #define REG_COMBO_PHY0_P2_73_L (REG_COMBO_PHY0_P2_BASE + 0xE6) 2760 #define REG_COMBO_PHY0_P2_73_H (REG_COMBO_PHY0_P2_BASE + 0xE7) 2761 #define REG_COMBO_PHY0_P2_74_L (REG_COMBO_PHY0_P2_BASE + 0xE8) 2762 #define REG_COMBO_PHY0_P2_74_H (REG_COMBO_PHY0_P2_BASE + 0xE9) 2763 #define REG_COMBO_PHY0_P2_75_L (REG_COMBO_PHY0_P2_BASE + 0xEA) 2764 #define REG_COMBO_PHY0_P2_75_H (REG_COMBO_PHY0_P2_BASE + 0xEB) 2765 #define REG_COMBO_PHY0_P2_76_L (REG_COMBO_PHY0_P2_BASE + 0xEC) 2766 #define REG_COMBO_PHY0_P2_76_H (REG_COMBO_PHY0_P2_BASE + 0xED) 2767 #define REG_COMBO_PHY0_P2_77_L (REG_COMBO_PHY0_P2_BASE + 0xEE) 2768 #define REG_COMBO_PHY0_P2_77_H (REG_COMBO_PHY0_P2_BASE + 0xEF) 2769 #define REG_COMBO_PHY0_P2_78_L (REG_COMBO_PHY0_P2_BASE + 0xF0) 2770 #define REG_COMBO_PHY0_P2_78_H (REG_COMBO_PHY0_P2_BASE + 0xF1) 2771 #define REG_COMBO_PHY0_P2_79_L (REG_COMBO_PHY0_P2_BASE + 0xF2) 2772 #define REG_COMBO_PHY0_P2_79_H (REG_COMBO_PHY0_P2_BASE + 0xF3) 2773 #define REG_COMBO_PHY0_P2_7A_L (REG_COMBO_PHY0_P2_BASE + 0xF4) 2774 #define REG_COMBO_PHY0_P2_7A_H (REG_COMBO_PHY0_P2_BASE + 0xF5) 2775 #define REG_COMBO_PHY0_P2_7B_L (REG_COMBO_PHY0_P2_BASE + 0xF6) 2776 #define REG_COMBO_PHY0_P2_7B_H (REG_COMBO_PHY0_P2_BASE + 0xF7) 2777 #define REG_COMBO_PHY0_P2_7C_L (REG_COMBO_PHY0_P2_BASE + 0xF8) 2778 #define REG_COMBO_PHY0_P2_7C_H (REG_COMBO_PHY0_P2_BASE + 0xF9) 2779 #define REG_COMBO_PHY0_P2_7D_L (REG_COMBO_PHY0_P2_BASE + 0xFA) 2780 #define REG_COMBO_PHY0_P2_7D_H (REG_COMBO_PHY0_P2_BASE + 0xFB) 2781 #define REG_COMBO_PHY0_P2_7E_L (REG_COMBO_PHY0_P2_BASE + 0xFC) 2782 #define REG_COMBO_PHY0_P2_7E_H (REG_COMBO_PHY0_P2_BASE + 0xFD) 2783 #define REG_COMBO_PHY0_P2_7F_L (REG_COMBO_PHY0_P2_BASE + 0xFE) 2784 #define REG_COMBO_PHY0_P2_7F_H (REG_COMBO_PHY0_P2_BASE + 0xFF) 2785 2786 // COMBO_PHY1_P2 2787 #define REG_COMBO_PHY1_P2_00_L (REG_COMBO_PHY1_P2_BASE + 0x00) 2788 #define REG_COMBO_PHY1_P2_00_H (REG_COMBO_PHY1_P2_BASE + 0x01) 2789 #define REG_COMBO_PHY1_P2_01_L (REG_COMBO_PHY1_P2_BASE + 0x02) 2790 #define REG_COMBO_PHY1_P2_01_H (REG_COMBO_PHY1_P2_BASE + 0x03) 2791 #define REG_COMBO_PHY1_P2_02_L (REG_COMBO_PHY1_P2_BASE + 0x04) 2792 #define REG_COMBO_PHY1_P2_02_H (REG_COMBO_PHY1_P2_BASE + 0x05) 2793 #define REG_COMBO_PHY1_P2_03_L (REG_COMBO_PHY1_P2_BASE + 0x06) 2794 #define REG_COMBO_PHY1_P2_03_H (REG_COMBO_PHY1_P2_BASE + 0x07) 2795 #define REG_COMBO_PHY1_P2_04_L (REG_COMBO_PHY1_P2_BASE + 0x08) 2796 #define REG_COMBO_PHY1_P2_04_H (REG_COMBO_PHY1_P2_BASE + 0x09) 2797 #define REG_COMBO_PHY1_P2_05_L (REG_COMBO_PHY1_P2_BASE + 0x0A) 2798 #define REG_COMBO_PHY1_P2_05_H (REG_COMBO_PHY1_P2_BASE + 0x0B) 2799 #define REG_COMBO_PHY1_P2_06_L (REG_COMBO_PHY1_P2_BASE + 0x0C) 2800 #define REG_COMBO_PHY1_P2_06_H (REG_COMBO_PHY1_P2_BASE + 0x0D) 2801 #define REG_COMBO_PHY1_P2_07_L (REG_COMBO_PHY1_P2_BASE + 0x0E) 2802 #define REG_COMBO_PHY1_P2_07_H (REG_COMBO_PHY1_P2_BASE + 0x0F) 2803 #define REG_COMBO_PHY1_P2_08_L (REG_COMBO_PHY1_P2_BASE + 0x10) 2804 #define REG_COMBO_PHY1_P2_08_H (REG_COMBO_PHY1_P2_BASE + 0x11) 2805 #define REG_COMBO_PHY1_P2_09_L (REG_COMBO_PHY1_P2_BASE + 0x12) 2806 #define REG_COMBO_PHY1_P2_09_H (REG_COMBO_PHY1_P2_BASE + 0x13) 2807 #define REG_COMBO_PHY1_P2_0A_L (REG_COMBO_PHY1_P2_BASE + 0x14) 2808 #define REG_COMBO_PHY1_P2_0A_H (REG_COMBO_PHY1_P2_BASE + 0x15) 2809 #define REG_COMBO_PHY1_P2_0B_L (REG_COMBO_PHY1_P2_BASE + 0x16) 2810 #define REG_COMBO_PHY1_P2_0B_H (REG_COMBO_PHY1_P2_BASE + 0x17) 2811 #define REG_COMBO_PHY1_P2_0C_L (REG_COMBO_PHY1_P2_BASE + 0x18) 2812 #define REG_COMBO_PHY1_P2_0C_H (REG_COMBO_PHY1_P2_BASE + 0x19) 2813 #define REG_COMBO_PHY1_P2_0D_L (REG_COMBO_PHY1_P2_BASE + 0x1A) 2814 #define REG_COMBO_PHY1_P2_0D_H (REG_COMBO_PHY1_P2_BASE + 0x1B) 2815 #define REG_COMBO_PHY1_P2_0E_L (REG_COMBO_PHY1_P2_BASE + 0x1C) 2816 #define REG_COMBO_PHY1_P2_0E_H (REG_COMBO_PHY1_P2_BASE + 0x1D) 2817 #define REG_COMBO_PHY1_P2_0F_L (REG_COMBO_PHY1_P2_BASE + 0x1E) 2818 #define REG_COMBO_PHY1_P2_0F_H (REG_COMBO_PHY1_P2_BASE + 0x1F) 2819 #define REG_COMBO_PHY1_P2_10_L (REG_COMBO_PHY1_P2_BASE + 0x20) 2820 #define REG_COMBO_PHY1_P2_10_H (REG_COMBO_PHY1_P2_BASE + 0x21) 2821 #define REG_COMBO_PHY1_P2_11_L (REG_COMBO_PHY1_P2_BASE + 0x22) 2822 #define REG_COMBO_PHY1_P2_11_H (REG_COMBO_PHY1_P2_BASE + 0x23) 2823 #define REG_COMBO_PHY1_P2_12_L (REG_COMBO_PHY1_P2_BASE + 0x24) 2824 #define REG_COMBO_PHY1_P2_12_H (REG_COMBO_PHY1_P2_BASE + 0x25) 2825 #define REG_COMBO_PHY1_P2_13_L (REG_COMBO_PHY1_P2_BASE + 0x26) 2826 #define REG_COMBO_PHY1_P2_13_H (REG_COMBO_PHY1_P2_BASE + 0x27) 2827 #define REG_COMBO_PHY1_P2_14_L (REG_COMBO_PHY1_P2_BASE + 0x28) 2828 #define REG_COMBO_PHY1_P2_14_H (REG_COMBO_PHY1_P2_BASE + 0x29) 2829 #define REG_COMBO_PHY1_P2_15_L (REG_COMBO_PHY1_P2_BASE + 0x2A) 2830 #define REG_COMBO_PHY1_P2_15_H (REG_COMBO_PHY1_P2_BASE + 0x2B) 2831 #define REG_COMBO_PHY1_P2_16_L (REG_COMBO_PHY1_P2_BASE + 0x2C) 2832 #define REG_COMBO_PHY1_P2_16_H (REG_COMBO_PHY1_P2_BASE + 0x2D) 2833 #define REG_COMBO_PHY1_P2_17_L (REG_COMBO_PHY1_P2_BASE + 0x2E) 2834 #define REG_COMBO_PHY1_P2_17_H (REG_COMBO_PHY1_P2_BASE + 0x2F) 2835 #define REG_COMBO_PHY1_P2_18_L (REG_COMBO_PHY1_P2_BASE + 0x30) 2836 #define REG_COMBO_PHY1_P2_18_H (REG_COMBO_PHY1_P2_BASE + 0x31) 2837 #define REG_COMBO_PHY1_P2_19_L (REG_COMBO_PHY1_P2_BASE + 0x32) 2838 #define REG_COMBO_PHY1_P2_19_H (REG_COMBO_PHY1_P2_BASE + 0x33) 2839 #define REG_COMBO_PHY1_P2_1A_L (REG_COMBO_PHY1_P2_BASE + 0x34) 2840 #define REG_COMBO_PHY1_P2_1A_H (REG_COMBO_PHY1_P2_BASE + 0x35) 2841 #define REG_COMBO_PHY1_P2_1B_L (REG_COMBO_PHY1_P2_BASE + 0x36) 2842 #define REG_COMBO_PHY1_P2_1B_H (REG_COMBO_PHY1_P2_BASE + 0x37) 2843 #define REG_COMBO_PHY1_P2_1C_L (REG_COMBO_PHY1_P2_BASE + 0x38) 2844 #define REG_COMBO_PHY1_P2_1C_H (REG_COMBO_PHY1_P2_BASE + 0x39) 2845 #define REG_COMBO_PHY1_P2_1D_L (REG_COMBO_PHY1_P2_BASE + 0x3A) 2846 #define REG_COMBO_PHY1_P2_1D_H (REG_COMBO_PHY1_P2_BASE + 0x3B) 2847 #define REG_COMBO_PHY1_P2_1E_L (REG_COMBO_PHY1_P2_BASE + 0x3C) 2848 #define REG_COMBO_PHY1_P2_1E_H (REG_COMBO_PHY1_P2_BASE + 0x3D) 2849 #define REG_COMBO_PHY1_P2_1F_L (REG_COMBO_PHY1_P2_BASE + 0x3E) 2850 #define REG_COMBO_PHY1_P2_1F_H (REG_COMBO_PHY1_P2_BASE + 0x3F) 2851 #define REG_COMBO_PHY1_P2_20_L (REG_COMBO_PHY1_P2_BASE + 0x40) 2852 #define REG_COMBO_PHY1_P2_20_H (REG_COMBO_PHY1_P2_BASE + 0x41) 2853 #define REG_COMBO_PHY1_P2_21_L (REG_COMBO_PHY1_P2_BASE + 0x42) 2854 #define REG_COMBO_PHY1_P2_21_H (REG_COMBO_PHY1_P2_BASE + 0x43) 2855 #define REG_COMBO_PHY1_P2_22_L (REG_COMBO_PHY1_P2_BASE + 0x44) 2856 #define REG_COMBO_PHY1_P2_22_H (REG_COMBO_PHY1_P2_BASE + 0x45) 2857 #define REG_COMBO_PHY1_P2_23_L (REG_COMBO_PHY1_P2_BASE + 0x46) 2858 #define REG_COMBO_PHY1_P2_23_H (REG_COMBO_PHY1_P2_BASE + 0x47) 2859 #define REG_COMBO_PHY1_P2_24_L (REG_COMBO_PHY1_P2_BASE + 0x48) 2860 #define REG_COMBO_PHY1_P2_24_H (REG_COMBO_PHY1_P2_BASE + 0x49) 2861 #define REG_COMBO_PHY1_P2_25_L (REG_COMBO_PHY1_P2_BASE + 0x4A) 2862 #define REG_COMBO_PHY1_P2_25_H (REG_COMBO_PHY1_P2_BASE + 0x4B) 2863 #define REG_COMBO_PHY1_P2_26_L (REG_COMBO_PHY1_P2_BASE + 0x4C) 2864 #define REG_COMBO_PHY1_P2_26_H (REG_COMBO_PHY1_P2_BASE + 0x4D) 2865 #define REG_COMBO_PHY1_P2_27_L (REG_COMBO_PHY1_P2_BASE + 0x4E) 2866 #define REG_COMBO_PHY1_P2_27_H (REG_COMBO_PHY1_P2_BASE + 0x4F) 2867 #define REG_COMBO_PHY1_P2_28_L (REG_COMBO_PHY1_P2_BASE + 0x50) 2868 #define REG_COMBO_PHY1_P2_28_H (REG_COMBO_PHY1_P2_BASE + 0x51) 2869 #define REG_COMBO_PHY1_P2_29_L (REG_COMBO_PHY1_P2_BASE + 0x52) 2870 #define REG_COMBO_PHY1_P2_29_H (REG_COMBO_PHY1_P2_BASE + 0x53) 2871 #define REG_COMBO_PHY1_P2_2A_L (REG_COMBO_PHY1_P2_BASE + 0x54) 2872 #define REG_COMBO_PHY1_P2_2A_H (REG_COMBO_PHY1_P2_BASE + 0x55) 2873 #define REG_COMBO_PHY1_P2_2B_L (REG_COMBO_PHY1_P2_BASE + 0x56) 2874 #define REG_COMBO_PHY1_P2_2B_H (REG_COMBO_PHY1_P2_BASE + 0x57) 2875 #define REG_COMBO_PHY1_P2_2C_L (REG_COMBO_PHY1_P2_BASE + 0x58) 2876 #define REG_COMBO_PHY1_P2_2C_H (REG_COMBO_PHY1_P2_BASE + 0x59) 2877 #define REG_COMBO_PHY1_P2_2D_L (REG_COMBO_PHY1_P2_BASE + 0x5A) 2878 #define REG_COMBO_PHY1_P2_2D_H (REG_COMBO_PHY1_P2_BASE + 0x5B) 2879 #define REG_COMBO_PHY1_P2_2E_L (REG_COMBO_PHY1_P2_BASE + 0x5C) 2880 #define REG_COMBO_PHY1_P2_2E_H (REG_COMBO_PHY1_P2_BASE + 0x5D) 2881 #define REG_COMBO_PHY1_P2_2F_L (REG_COMBO_PHY1_P2_BASE + 0x5E) 2882 #define REG_COMBO_PHY1_P2_2F_H (REG_COMBO_PHY1_P2_BASE + 0x5F) 2883 #define REG_COMBO_PHY1_P2_30_L (REG_COMBO_PHY1_P2_BASE + 0x60) 2884 #define REG_COMBO_PHY1_P2_30_H (REG_COMBO_PHY1_P2_BASE + 0x61) 2885 #define REG_COMBO_PHY1_P2_31_L (REG_COMBO_PHY1_P2_BASE + 0x62) 2886 #define REG_COMBO_PHY1_P2_31_H (REG_COMBO_PHY1_P2_BASE + 0x63) 2887 #define REG_COMBO_PHY1_P2_32_L (REG_COMBO_PHY1_P2_BASE + 0x64) 2888 #define REG_COMBO_PHY1_P2_32_H (REG_COMBO_PHY1_P2_BASE + 0x65) 2889 #define REG_COMBO_PHY1_P2_33_L (REG_COMBO_PHY1_P2_BASE + 0x66) 2890 #define REG_COMBO_PHY1_P2_33_H (REG_COMBO_PHY1_P2_BASE + 0x67) 2891 #define REG_COMBO_PHY1_P2_34_L (REG_COMBO_PHY1_P2_BASE + 0x68) 2892 #define REG_COMBO_PHY1_P2_34_H (REG_COMBO_PHY1_P2_BASE + 0x69) 2893 #define REG_COMBO_PHY1_P2_35_L (REG_COMBO_PHY1_P2_BASE + 0x6A) 2894 #define REG_COMBO_PHY1_P2_35_H (REG_COMBO_PHY1_P2_BASE + 0x6B) 2895 #define REG_COMBO_PHY1_P2_36_L (REG_COMBO_PHY1_P2_BASE + 0x6C) 2896 #define REG_COMBO_PHY1_P2_36_H (REG_COMBO_PHY1_P2_BASE + 0x6D) 2897 #define REG_COMBO_PHY1_P2_37_L (REG_COMBO_PHY1_P2_BASE + 0x6E) 2898 #define REG_COMBO_PHY1_P2_37_H (REG_COMBO_PHY1_P2_BASE + 0x6F) 2899 #define REG_COMBO_PHY1_P2_38_L (REG_COMBO_PHY1_P2_BASE + 0x70) 2900 #define REG_COMBO_PHY1_P2_38_H (REG_COMBO_PHY1_P2_BASE + 0x71) 2901 #define REG_COMBO_PHY1_P2_39_L (REG_COMBO_PHY1_P2_BASE + 0x72) 2902 #define REG_COMBO_PHY1_P2_39_H (REG_COMBO_PHY1_P2_BASE + 0x73) 2903 #define REG_COMBO_PHY1_P2_3A_L (REG_COMBO_PHY1_P2_BASE + 0x74) 2904 #define REG_COMBO_PHY1_P2_3A_H (REG_COMBO_PHY1_P2_BASE + 0x75) 2905 #define REG_COMBO_PHY1_P2_3B_L (REG_COMBO_PHY1_P2_BASE + 0x76) 2906 #define REG_COMBO_PHY1_P2_3B_H (REG_COMBO_PHY1_P2_BASE + 0x77) 2907 #define REG_COMBO_PHY1_P2_3C_L (REG_COMBO_PHY1_P2_BASE + 0x78) 2908 #define REG_COMBO_PHY1_P2_3C_H (REG_COMBO_PHY1_P2_BASE + 0x79) 2909 #define REG_COMBO_PHY1_P2_3D_L (REG_COMBO_PHY1_P2_BASE + 0x7A) 2910 #define REG_COMBO_PHY1_P2_3D_H (REG_COMBO_PHY1_P2_BASE + 0x7B) 2911 #define REG_COMBO_PHY1_P2_3E_L (REG_COMBO_PHY1_P2_BASE + 0x7C) 2912 #define REG_COMBO_PHY1_P2_3E_H (REG_COMBO_PHY1_P2_BASE + 0x7D) 2913 #define REG_COMBO_PHY1_P2_3F_L (REG_COMBO_PHY1_P2_BASE + 0x7E) 2914 #define REG_COMBO_PHY1_P2_3F_H (REG_COMBO_PHY1_P2_BASE + 0x7F) 2915 #define REG_COMBO_PHY1_P2_40_L (REG_COMBO_PHY1_P2_BASE + 0x80) 2916 #define REG_COMBO_PHY1_P2_40_H (REG_COMBO_PHY1_P2_BASE + 0x81) 2917 #define REG_COMBO_PHY1_P2_41_L (REG_COMBO_PHY1_P2_BASE + 0x82) 2918 #define REG_COMBO_PHY1_P2_41_H (REG_COMBO_PHY1_P2_BASE + 0x83) 2919 #define REG_COMBO_PHY1_P2_42_L (REG_COMBO_PHY1_P2_BASE + 0x84) 2920 #define REG_COMBO_PHY1_P2_42_H (REG_COMBO_PHY1_P2_BASE + 0x85) 2921 #define REG_COMBO_PHY1_P2_43_L (REG_COMBO_PHY1_P2_BASE + 0x86) 2922 #define REG_COMBO_PHY1_P2_43_H (REG_COMBO_PHY1_P2_BASE + 0x87) 2923 #define REG_COMBO_PHY1_P2_44_L (REG_COMBO_PHY1_P2_BASE + 0x88) 2924 #define REG_COMBO_PHY1_P2_44_H (REG_COMBO_PHY1_P2_BASE + 0x89) 2925 #define REG_COMBO_PHY1_P2_45_L (REG_COMBO_PHY1_P2_BASE + 0x8A) 2926 #define REG_COMBO_PHY1_P2_45_H (REG_COMBO_PHY1_P2_BASE + 0x8B) 2927 #define REG_COMBO_PHY1_P2_46_L (REG_COMBO_PHY1_P2_BASE + 0x8C) 2928 #define REG_COMBO_PHY1_P2_46_H (REG_COMBO_PHY1_P2_BASE + 0x8D) 2929 #define REG_COMBO_PHY1_P2_47_L (REG_COMBO_PHY1_P2_BASE + 0x8E) 2930 #define REG_COMBO_PHY1_P2_47_H (REG_COMBO_PHY1_P2_BASE + 0x8F) 2931 #define REG_COMBO_PHY1_P2_48_L (REG_COMBO_PHY1_P2_BASE + 0x90) 2932 #define REG_COMBO_PHY1_P2_48_H (REG_COMBO_PHY1_P2_BASE + 0x91) 2933 #define REG_COMBO_PHY1_P2_49_L (REG_COMBO_PHY1_P2_BASE + 0x92) 2934 #define REG_COMBO_PHY1_P2_49_H (REG_COMBO_PHY1_P2_BASE + 0x93) 2935 #define REG_COMBO_PHY1_P2_4A_L (REG_COMBO_PHY1_P2_BASE + 0x94) 2936 #define REG_COMBO_PHY1_P2_4A_H (REG_COMBO_PHY1_P2_BASE + 0x95) 2937 #define REG_COMBO_PHY1_P2_4B_L (REG_COMBO_PHY1_P2_BASE + 0x96) 2938 #define REG_COMBO_PHY1_P2_4B_H (REG_COMBO_PHY1_P2_BASE + 0x97) 2939 #define REG_COMBO_PHY1_P2_4C_L (REG_COMBO_PHY1_P2_BASE + 0x98) 2940 #define REG_COMBO_PHY1_P2_4C_H (REG_COMBO_PHY1_P2_BASE + 0x99) 2941 #define REG_COMBO_PHY1_P2_4D_L (REG_COMBO_PHY1_P2_BASE + 0x9A) 2942 #define REG_COMBO_PHY1_P2_4D_H (REG_COMBO_PHY1_P2_BASE + 0x9B) 2943 #define REG_COMBO_PHY1_P2_4E_L (REG_COMBO_PHY1_P2_BASE + 0x9C) 2944 #define REG_COMBO_PHY1_P2_4E_H (REG_COMBO_PHY1_P2_BASE + 0x9D) 2945 #define REG_COMBO_PHY1_P2_4F_L (REG_COMBO_PHY1_P2_BASE + 0x9E) 2946 #define REG_COMBO_PHY1_P2_4F_H (REG_COMBO_PHY1_P2_BASE + 0x9F) 2947 #define REG_COMBO_PHY1_P2_50_L (REG_COMBO_PHY1_P2_BASE + 0xA0) 2948 #define REG_COMBO_PHY1_P2_50_H (REG_COMBO_PHY1_P2_BASE + 0xA1) 2949 #define REG_COMBO_PHY1_P2_51_L (REG_COMBO_PHY1_P2_BASE + 0xA2) 2950 #define REG_COMBO_PHY1_P2_51_H (REG_COMBO_PHY1_P2_BASE + 0xA3) 2951 #define REG_COMBO_PHY1_P2_52_L (REG_COMBO_PHY1_P2_BASE + 0xA4) 2952 #define REG_COMBO_PHY1_P2_52_H (REG_COMBO_PHY1_P2_BASE + 0xA5) 2953 #define REG_COMBO_PHY1_P2_53_L (REG_COMBO_PHY1_P2_BASE + 0xA6) 2954 #define REG_COMBO_PHY1_P2_53_H (REG_COMBO_PHY1_P2_BASE + 0xA7) 2955 #define REG_COMBO_PHY1_P2_54_L (REG_COMBO_PHY1_P2_BASE + 0xA8) 2956 #define REG_COMBO_PHY1_P2_54_H (REG_COMBO_PHY1_P2_BASE + 0xA9) 2957 #define REG_COMBO_PHY1_P2_55_L (REG_COMBO_PHY1_P2_BASE + 0xAA) 2958 #define REG_COMBO_PHY1_P2_55_H (REG_COMBO_PHY1_P2_BASE + 0xAB) 2959 #define REG_COMBO_PHY1_P2_56_L (REG_COMBO_PHY1_P2_BASE + 0xAC) 2960 #define REG_COMBO_PHY1_P2_56_H (REG_COMBO_PHY1_P2_BASE + 0xAD) 2961 #define REG_COMBO_PHY1_P2_57_L (REG_COMBO_PHY1_P2_BASE + 0xAE) 2962 #define REG_COMBO_PHY1_P2_57_H (REG_COMBO_PHY1_P2_BASE + 0xAF) 2963 #define REG_COMBO_PHY1_P2_58_L (REG_COMBO_PHY1_P2_BASE + 0xB0) 2964 #define REG_COMBO_PHY1_P2_58_H (REG_COMBO_PHY1_P2_BASE + 0xB1) 2965 #define REG_COMBO_PHY1_P2_59_L (REG_COMBO_PHY1_P2_BASE + 0xB2) 2966 #define REG_COMBO_PHY1_P2_59_H (REG_COMBO_PHY1_P2_BASE + 0xB3) 2967 #define REG_COMBO_PHY1_P2_5A_L (REG_COMBO_PHY1_P2_BASE + 0xB4) 2968 #define REG_COMBO_PHY1_P2_5A_H (REG_COMBO_PHY1_P2_BASE + 0xB5) 2969 #define REG_COMBO_PHY1_P2_5B_L (REG_COMBO_PHY1_P2_BASE + 0xB6) 2970 #define REG_COMBO_PHY1_P2_5B_H (REG_COMBO_PHY1_P2_BASE + 0xB7) 2971 #define REG_COMBO_PHY1_P2_5C_L (REG_COMBO_PHY1_P2_BASE + 0xB8) 2972 #define REG_COMBO_PHY1_P2_5C_H (REG_COMBO_PHY1_P2_BASE + 0xB9) 2973 #define REG_COMBO_PHY1_P2_5D_L (REG_COMBO_PHY1_P2_BASE + 0xBA) 2974 #define REG_COMBO_PHY1_P2_5D_H (REG_COMBO_PHY1_P2_BASE + 0xBB) 2975 #define REG_COMBO_PHY1_P2_5E_L (REG_COMBO_PHY1_P2_BASE + 0xBC) 2976 #define REG_COMBO_PHY1_P2_5E_H (REG_COMBO_PHY1_P2_BASE + 0xBD) 2977 #define REG_COMBO_PHY1_P2_5F_L (REG_COMBO_PHY1_P2_BASE + 0xBE) 2978 #define REG_COMBO_PHY1_P2_5F_H (REG_COMBO_PHY1_P2_BASE + 0xBF) 2979 #define REG_COMBO_PHY1_P2_60_L (REG_COMBO_PHY1_P2_BASE + 0xC0) 2980 #define REG_COMBO_PHY1_P2_60_H (REG_COMBO_PHY1_P2_BASE + 0xC1) 2981 #define REG_COMBO_PHY1_P2_61_L (REG_COMBO_PHY1_P2_BASE + 0xC2) 2982 #define REG_COMBO_PHY1_P2_61_H (REG_COMBO_PHY1_P2_BASE + 0xC3) 2983 #define REG_COMBO_PHY1_P2_62_L (REG_COMBO_PHY1_P2_BASE + 0xC4) 2984 #define REG_COMBO_PHY1_P2_62_H (REG_COMBO_PHY1_P2_BASE + 0xC5) 2985 #define REG_COMBO_PHY1_P2_63_L (REG_COMBO_PHY1_P2_BASE + 0xC6) 2986 #define REG_COMBO_PHY1_P2_63_H (REG_COMBO_PHY1_P2_BASE + 0xC7) 2987 #define REG_COMBO_PHY1_P2_64_L (REG_COMBO_PHY1_P2_BASE + 0xC8) 2988 #define REG_COMBO_PHY1_P2_64_H (REG_COMBO_PHY1_P2_BASE + 0xC9) 2989 #define REG_COMBO_PHY1_P2_65_L (REG_COMBO_PHY1_P2_BASE + 0xCA) 2990 #define REG_COMBO_PHY1_P2_65_H (REG_COMBO_PHY1_P2_BASE + 0xCB) 2991 #define REG_COMBO_PHY1_P2_66_L (REG_COMBO_PHY1_P2_BASE + 0xCC) 2992 #define REG_COMBO_PHY1_P2_66_H (REG_COMBO_PHY1_P2_BASE + 0xCD) 2993 #define REG_COMBO_PHY1_P2_67_L (REG_COMBO_PHY1_P2_BASE + 0xCE) 2994 #define REG_COMBO_PHY1_P2_67_H (REG_COMBO_PHY1_P2_BASE + 0xCF) 2995 #define REG_COMBO_PHY1_P2_68_L (REG_COMBO_PHY1_P2_BASE + 0xD0) 2996 #define REG_COMBO_PHY1_P2_68_H (REG_COMBO_PHY1_P2_BASE + 0xD1) 2997 #define REG_COMBO_PHY1_P2_69_L (REG_COMBO_PHY1_P2_BASE + 0xD2) 2998 #define REG_COMBO_PHY1_P2_69_H (REG_COMBO_PHY1_P2_BASE + 0xD3) 2999 #define REG_COMBO_PHY1_P2_6A_L (REG_COMBO_PHY1_P2_BASE + 0xD4) 3000 #define REG_COMBO_PHY1_P2_6A_H (REG_COMBO_PHY1_P2_BASE + 0xD5) 3001 #define REG_COMBO_PHY1_P2_6B_L (REG_COMBO_PHY1_P2_BASE + 0xD6) 3002 #define REG_COMBO_PHY1_P2_6B_H (REG_COMBO_PHY1_P2_BASE + 0xD7) 3003 #define REG_COMBO_PHY1_P2_6C_L (REG_COMBO_PHY1_P2_BASE + 0xD8) 3004 #define REG_COMBO_PHY1_P2_6C_H (REG_COMBO_PHY1_P2_BASE + 0xD9) 3005 #define REG_COMBO_PHY1_P2_6D_L (REG_COMBO_PHY1_P2_BASE + 0xDA) 3006 #define REG_COMBO_PHY1_P2_6D_H (REG_COMBO_PHY1_P2_BASE + 0xDB) 3007 #define REG_COMBO_PHY1_P2_6E_L (REG_COMBO_PHY1_P2_BASE + 0xDC) 3008 #define REG_COMBO_PHY1_P2_6E_H (REG_COMBO_PHY1_P2_BASE + 0xDD) 3009 #define REG_COMBO_PHY1_P2_6F_L (REG_COMBO_PHY1_P2_BASE + 0xDE) 3010 #define REG_COMBO_PHY1_P2_6F_H (REG_COMBO_PHY1_P2_BASE + 0xDF) 3011 #define REG_COMBO_PHY1_P2_70_L (REG_COMBO_PHY1_P2_BASE + 0xE0) 3012 #define REG_COMBO_PHY1_P2_70_H (REG_COMBO_PHY1_P2_BASE + 0xE1) 3013 #define REG_COMBO_PHY1_P2_71_L (REG_COMBO_PHY1_P2_BASE + 0xE2) 3014 #define REG_COMBO_PHY1_P2_71_H (REG_COMBO_PHY1_P2_BASE + 0xE3) 3015 #define REG_COMBO_PHY1_P2_72_L (REG_COMBO_PHY1_P2_BASE + 0xE4) 3016 #define REG_COMBO_PHY1_P2_72_H (REG_COMBO_PHY1_P2_BASE + 0xE5) 3017 #define REG_COMBO_PHY1_P2_73_L (REG_COMBO_PHY1_P2_BASE + 0xE6) 3018 #define REG_COMBO_PHY1_P2_73_H (REG_COMBO_PHY1_P2_BASE + 0xE7) 3019 #define REG_COMBO_PHY1_P2_74_L (REG_COMBO_PHY1_P2_BASE + 0xE8) 3020 #define REG_COMBO_PHY1_P2_74_H (REG_COMBO_PHY1_P2_BASE + 0xE9) 3021 #define REG_COMBO_PHY1_P2_75_L (REG_COMBO_PHY1_P2_BASE + 0xEA) 3022 #define REG_COMBO_PHY1_P2_75_H (REG_COMBO_PHY1_P2_BASE + 0xEB) 3023 #define REG_COMBO_PHY1_P2_76_L (REG_COMBO_PHY1_P2_BASE + 0xEC) 3024 #define REG_COMBO_PHY1_P2_76_H (REG_COMBO_PHY1_P2_BASE + 0xED) 3025 #define REG_COMBO_PHY1_P2_77_L (REG_COMBO_PHY1_P2_BASE + 0xEE) 3026 #define REG_COMBO_PHY1_P2_77_H (REG_COMBO_PHY1_P2_BASE + 0xEF) 3027 #define REG_COMBO_PHY1_P2_78_L (REG_COMBO_PHY1_P2_BASE + 0xF0) 3028 #define REG_COMBO_PHY1_P2_78_H (REG_COMBO_PHY1_P2_BASE + 0xF1) 3029 #define REG_COMBO_PHY1_P2_79_L (REG_COMBO_PHY1_P2_BASE + 0xF2) 3030 #define REG_COMBO_PHY1_P2_79_H (REG_COMBO_PHY1_P2_BASE + 0xF3) 3031 #define REG_COMBO_PHY1_P2_7A_L (REG_COMBO_PHY1_P2_BASE + 0xF4) 3032 #define REG_COMBO_PHY1_P2_7A_H (REG_COMBO_PHY1_P2_BASE + 0xF5) 3033 #define REG_COMBO_PHY1_P2_7B_L (REG_COMBO_PHY1_P2_BASE + 0xF6) 3034 #define REG_COMBO_PHY1_P2_7B_H (REG_COMBO_PHY1_P2_BASE + 0xF7) 3035 #define REG_COMBO_PHY1_P2_7C_L (REG_COMBO_PHY1_P2_BASE + 0xF8) 3036 #define REG_COMBO_PHY1_P2_7C_H (REG_COMBO_PHY1_P2_BASE + 0xF9) 3037 #define REG_COMBO_PHY1_P2_7D_L (REG_COMBO_PHY1_P2_BASE + 0xFA) 3038 #define REG_COMBO_PHY1_P2_7D_H (REG_COMBO_PHY1_P2_BASE + 0xFB) 3039 #define REG_COMBO_PHY1_P2_7E_L (REG_COMBO_PHY1_P2_BASE + 0xFC) 3040 #define REG_COMBO_PHY1_P2_7E_H (REG_COMBO_PHY1_P2_BASE + 0xFD) 3041 #define REG_COMBO_PHY1_P2_7F_L (REG_COMBO_PHY1_P2_BASE + 0xFE) 3042 #define REG_COMBO_PHY1_P2_7F_H (REG_COMBO_PHY1_P2_BASE + 0xFF) 3043 3044 // COMBO_PHY0_P3 3045 #define REG_COMBO_PHY0_P3_00_L (REG_COMBO_PHY0_P3_BASE + 0x00) 3046 #define REG_COMBO_PHY0_P3_00_H (REG_COMBO_PHY0_P3_BASE + 0x01) 3047 #define REG_COMBO_PHY0_P3_01_L (REG_COMBO_PHY0_P3_BASE + 0x02) 3048 #define REG_COMBO_PHY0_P3_01_H (REG_COMBO_PHY0_P3_BASE + 0x03) 3049 #define REG_COMBO_PHY0_P3_02_L (REG_COMBO_PHY0_P3_BASE + 0x04) 3050 #define REG_COMBO_PHY0_P3_02_H (REG_COMBO_PHY0_P3_BASE + 0x05) 3051 #define REG_COMBO_PHY0_P3_03_L (REG_COMBO_PHY0_P3_BASE + 0x06) 3052 #define REG_COMBO_PHY0_P3_03_H (REG_COMBO_PHY0_P3_BASE + 0x07) 3053 #define REG_COMBO_PHY0_P3_04_L (REG_COMBO_PHY0_P3_BASE + 0x08) 3054 #define REG_COMBO_PHY0_P3_04_H (REG_COMBO_PHY0_P3_BASE + 0x09) 3055 #define REG_COMBO_PHY0_P3_05_L (REG_COMBO_PHY0_P3_BASE + 0x0A) 3056 #define REG_COMBO_PHY0_P3_05_H (REG_COMBO_PHY0_P3_BASE + 0x0B) 3057 #define REG_COMBO_PHY0_P3_06_L (REG_COMBO_PHY0_P3_BASE + 0x0C) 3058 #define REG_COMBO_PHY0_P3_06_H (REG_COMBO_PHY0_P3_BASE + 0x0D) 3059 #define REG_COMBO_PHY0_P3_07_L (REG_COMBO_PHY0_P3_BASE + 0x0E) 3060 #define REG_COMBO_PHY0_P3_07_H (REG_COMBO_PHY0_P3_BASE + 0x0F) 3061 #define REG_COMBO_PHY0_P3_08_L (REG_COMBO_PHY0_P3_BASE + 0x10) 3062 #define REG_COMBO_PHY0_P3_08_H (REG_COMBO_PHY0_P3_BASE + 0x11) 3063 #define REG_COMBO_PHY0_P3_09_L (REG_COMBO_PHY0_P3_BASE + 0x12) 3064 #define REG_COMBO_PHY0_P3_09_H (REG_COMBO_PHY0_P3_BASE + 0x13) 3065 #define REG_COMBO_PHY0_P3_0A_L (REG_COMBO_PHY0_P3_BASE + 0x14) 3066 #define REG_COMBO_PHY0_P3_0A_H (REG_COMBO_PHY0_P3_BASE + 0x15) 3067 #define REG_COMBO_PHY0_P3_0B_L (REG_COMBO_PHY0_P3_BASE + 0x16) 3068 #define REG_COMBO_PHY0_P3_0B_H (REG_COMBO_PHY0_P3_BASE + 0x17) 3069 #define REG_COMBO_PHY0_P3_0C_L (REG_COMBO_PHY0_P3_BASE + 0x18) 3070 #define REG_COMBO_PHY0_P3_0C_H (REG_COMBO_PHY0_P3_BASE + 0x19) 3071 #define REG_COMBO_PHY0_P3_0D_L (REG_COMBO_PHY0_P3_BASE + 0x1A) 3072 #define REG_COMBO_PHY0_P3_0D_H (REG_COMBO_PHY0_P3_BASE + 0x1B) 3073 #define REG_COMBO_PHY0_P3_0E_L (REG_COMBO_PHY0_P3_BASE + 0x1C) 3074 #define REG_COMBO_PHY0_P3_0E_H (REG_COMBO_PHY0_P3_BASE + 0x1D) 3075 #define REG_COMBO_PHY0_P3_0F_L (REG_COMBO_PHY0_P3_BASE + 0x1E) 3076 #define REG_COMBO_PHY0_P3_0F_H (REG_COMBO_PHY0_P3_BASE + 0x1F) 3077 #define REG_COMBO_PHY0_P3_10_L (REG_COMBO_PHY0_P3_BASE + 0x20) 3078 #define REG_COMBO_PHY0_P3_10_H (REG_COMBO_PHY0_P3_BASE + 0x21) 3079 #define REG_COMBO_PHY0_P3_11_L (REG_COMBO_PHY0_P3_BASE + 0x22) 3080 #define REG_COMBO_PHY0_P3_11_H (REG_COMBO_PHY0_P3_BASE + 0x23) 3081 #define REG_COMBO_PHY0_P3_12_L (REG_COMBO_PHY0_P3_BASE + 0x24) 3082 #define REG_COMBO_PHY0_P3_12_H (REG_COMBO_PHY0_P3_BASE + 0x25) 3083 #define REG_COMBO_PHY0_P3_13_L (REG_COMBO_PHY0_P3_BASE + 0x26) 3084 #define REG_COMBO_PHY0_P3_13_H (REG_COMBO_PHY0_P3_BASE + 0x27) 3085 #define REG_COMBO_PHY0_P3_14_L (REG_COMBO_PHY0_P3_BASE + 0x28) 3086 #define REG_COMBO_PHY0_P3_14_H (REG_COMBO_PHY0_P3_BASE + 0x29) 3087 #define REG_COMBO_PHY0_P3_15_L (REG_COMBO_PHY0_P3_BASE + 0x2A) 3088 #define REG_COMBO_PHY0_P3_15_H (REG_COMBO_PHY0_P3_BASE + 0x2B) 3089 #define REG_COMBO_PHY0_P3_16_L (REG_COMBO_PHY0_P3_BASE + 0x2C) 3090 #define REG_COMBO_PHY0_P3_16_H (REG_COMBO_PHY0_P3_BASE + 0x2D) 3091 #define REG_COMBO_PHY0_P3_17_L (REG_COMBO_PHY0_P3_BASE + 0x2E) 3092 #define REG_COMBO_PHY0_P3_17_H (REG_COMBO_PHY0_P3_BASE + 0x2F) 3093 #define REG_COMBO_PHY0_P3_18_L (REG_COMBO_PHY0_P3_BASE + 0x30) 3094 #define REG_COMBO_PHY0_P3_18_H (REG_COMBO_PHY0_P3_BASE + 0x31) 3095 #define REG_COMBO_PHY0_P3_19_L (REG_COMBO_PHY0_P3_BASE + 0x32) 3096 #define REG_COMBO_PHY0_P3_19_H (REG_COMBO_PHY0_P3_BASE + 0x33) 3097 #define REG_COMBO_PHY0_P3_1A_L (REG_COMBO_PHY0_P3_BASE + 0x34) 3098 #define REG_COMBO_PHY0_P3_1A_H (REG_COMBO_PHY0_P3_BASE + 0x35) 3099 #define REG_COMBO_PHY0_P3_1B_L (REG_COMBO_PHY0_P3_BASE + 0x36) 3100 #define REG_COMBO_PHY0_P3_1B_H (REG_COMBO_PHY0_P3_BASE + 0x37) 3101 #define REG_COMBO_PHY0_P3_1C_L (REG_COMBO_PHY0_P3_BASE + 0x38) 3102 #define REG_COMBO_PHY0_P3_1C_H (REG_COMBO_PHY0_P3_BASE + 0x39) 3103 #define REG_COMBO_PHY0_P3_1D_L (REG_COMBO_PHY0_P3_BASE + 0x3A) 3104 #define REG_COMBO_PHY0_P3_1D_H (REG_COMBO_PHY0_P3_BASE + 0x3B) 3105 #define REG_COMBO_PHY0_P3_1E_L (REG_COMBO_PHY0_P3_BASE + 0x3C) 3106 #define REG_COMBO_PHY0_P3_1E_H (REG_COMBO_PHY0_P3_BASE + 0x3D) 3107 #define REG_COMBO_PHY0_P3_1F_L (REG_COMBO_PHY0_P3_BASE + 0x3E) 3108 #define REG_COMBO_PHY0_P3_1F_H (REG_COMBO_PHY0_P3_BASE + 0x3F) 3109 #define REG_COMBO_PHY0_P3_20_L (REG_COMBO_PHY0_P3_BASE + 0x40) 3110 #define REG_COMBO_PHY0_P3_20_H (REG_COMBO_PHY0_P3_BASE + 0x41) 3111 #define REG_COMBO_PHY0_P3_21_L (REG_COMBO_PHY0_P3_BASE + 0x42) 3112 #define REG_COMBO_PHY0_P3_21_H (REG_COMBO_PHY0_P3_BASE + 0x43) 3113 #define REG_COMBO_PHY0_P3_22_L (REG_COMBO_PHY0_P3_BASE + 0x44) 3114 #define REG_COMBO_PHY0_P3_22_H (REG_COMBO_PHY0_P3_BASE + 0x45) 3115 #define REG_COMBO_PHY0_P3_23_L (REG_COMBO_PHY0_P3_BASE + 0x46) 3116 #define REG_COMBO_PHY0_P3_23_H (REG_COMBO_PHY0_P3_BASE + 0x47) 3117 #define REG_COMBO_PHY0_P3_24_L (REG_COMBO_PHY0_P3_BASE + 0x48) 3118 #define REG_COMBO_PHY0_P3_24_H (REG_COMBO_PHY0_P3_BASE + 0x49) 3119 #define REG_COMBO_PHY0_P3_25_L (REG_COMBO_PHY0_P3_BASE + 0x4A) 3120 #define REG_COMBO_PHY0_P3_25_H (REG_COMBO_PHY0_P3_BASE + 0x4B) 3121 #define REG_COMBO_PHY0_P3_26_L (REG_COMBO_PHY0_P3_BASE + 0x4C) 3122 #define REG_COMBO_PHY0_P3_26_H (REG_COMBO_PHY0_P3_BASE + 0x4D) 3123 #define REG_COMBO_PHY0_P3_27_L (REG_COMBO_PHY0_P3_BASE + 0x4E) 3124 #define REG_COMBO_PHY0_P3_27_H (REG_COMBO_PHY0_P3_BASE + 0x4F) 3125 #define REG_COMBO_PHY0_P3_28_L (REG_COMBO_PHY0_P3_BASE + 0x50) 3126 #define REG_COMBO_PHY0_P3_28_H (REG_COMBO_PHY0_P3_BASE + 0x51) 3127 #define REG_COMBO_PHY0_P3_29_L (REG_COMBO_PHY0_P3_BASE + 0x52) 3128 #define REG_COMBO_PHY0_P3_29_H (REG_COMBO_PHY0_P3_BASE + 0x53) 3129 #define REG_COMBO_PHY0_P3_2A_L (REG_COMBO_PHY0_P3_BASE + 0x54) 3130 #define REG_COMBO_PHY0_P3_2A_H (REG_COMBO_PHY0_P3_BASE + 0x55) 3131 #define REG_COMBO_PHY0_P3_2B_L (REG_COMBO_PHY0_P3_BASE + 0x56) 3132 #define REG_COMBO_PHY0_P3_2B_H (REG_COMBO_PHY0_P3_BASE + 0x57) 3133 #define REG_COMBO_PHY0_P3_2C_L (REG_COMBO_PHY0_P3_BASE + 0x58) 3134 #define REG_COMBO_PHY0_P3_2C_H (REG_COMBO_PHY0_P3_BASE + 0x59) 3135 #define REG_COMBO_PHY0_P3_2D_L (REG_COMBO_PHY0_P3_BASE + 0x5A) 3136 #define REG_COMBO_PHY0_P3_2D_H (REG_COMBO_PHY0_P3_BASE + 0x5B) 3137 #define REG_COMBO_PHY0_P3_2E_L (REG_COMBO_PHY0_P3_BASE + 0x5C) 3138 #define REG_COMBO_PHY0_P3_2E_H (REG_COMBO_PHY0_P3_BASE + 0x5D) 3139 #define REG_COMBO_PHY0_P3_2F_L (REG_COMBO_PHY0_P3_BASE + 0x5E) 3140 #define REG_COMBO_PHY0_P3_2F_H (REG_COMBO_PHY0_P3_BASE + 0x5F) 3141 #define REG_COMBO_PHY0_P3_30_L (REG_COMBO_PHY0_P3_BASE + 0x60) 3142 #define REG_COMBO_PHY0_P3_30_H (REG_COMBO_PHY0_P3_BASE + 0x61) 3143 #define REG_COMBO_PHY0_P3_31_L (REG_COMBO_PHY0_P3_BASE + 0x62) 3144 #define REG_COMBO_PHY0_P3_31_H (REG_COMBO_PHY0_P3_BASE + 0x63) 3145 #define REG_COMBO_PHY0_P3_32_L (REG_COMBO_PHY0_P3_BASE + 0x64) 3146 #define REG_COMBO_PHY0_P3_32_H (REG_COMBO_PHY0_P3_BASE + 0x65) 3147 #define REG_COMBO_PHY0_P3_33_L (REG_COMBO_PHY0_P3_BASE + 0x66) 3148 #define REG_COMBO_PHY0_P3_33_H (REG_COMBO_PHY0_P3_BASE + 0x67) 3149 #define REG_COMBO_PHY0_P3_34_L (REG_COMBO_PHY0_P3_BASE + 0x68) 3150 #define REG_COMBO_PHY0_P3_34_H (REG_COMBO_PHY0_P3_BASE + 0x69) 3151 #define REG_COMBO_PHY0_P3_35_L (REG_COMBO_PHY0_P3_BASE + 0x6A) 3152 #define REG_COMBO_PHY0_P3_35_H (REG_COMBO_PHY0_P3_BASE + 0x6B) 3153 #define REG_COMBO_PHY0_P3_36_L (REG_COMBO_PHY0_P3_BASE + 0x6C) 3154 #define REG_COMBO_PHY0_P3_36_H (REG_COMBO_PHY0_P3_BASE + 0x6D) 3155 #define REG_COMBO_PHY0_P3_37_L (REG_COMBO_PHY0_P3_BASE + 0x6E) 3156 #define REG_COMBO_PHY0_P3_37_H (REG_COMBO_PHY0_P3_BASE + 0x6F) 3157 #define REG_COMBO_PHY0_P3_38_L (REG_COMBO_PHY0_P3_BASE + 0x70) 3158 #define REG_COMBO_PHY0_P3_38_H (REG_COMBO_PHY0_P3_BASE + 0x71) 3159 #define REG_COMBO_PHY0_P3_39_L (REG_COMBO_PHY0_P3_BASE + 0x72) 3160 #define REG_COMBO_PHY0_P3_39_H (REG_COMBO_PHY0_P3_BASE + 0x73) 3161 #define REG_COMBO_PHY0_P3_3A_L (REG_COMBO_PHY0_P3_BASE + 0x74) 3162 #define REG_COMBO_PHY0_P3_3A_H (REG_COMBO_PHY0_P3_BASE + 0x75) 3163 #define REG_COMBO_PHY0_P3_3B_L (REG_COMBO_PHY0_P3_BASE + 0x76) 3164 #define REG_COMBO_PHY0_P3_3B_H (REG_COMBO_PHY0_P3_BASE + 0x77) 3165 #define REG_COMBO_PHY0_P3_3C_L (REG_COMBO_PHY0_P3_BASE + 0x78) 3166 #define REG_COMBO_PHY0_P3_3C_H (REG_COMBO_PHY0_P3_BASE + 0x79) 3167 #define REG_COMBO_PHY0_P3_3D_L (REG_COMBO_PHY0_P3_BASE + 0x7A) 3168 #define REG_COMBO_PHY0_P3_3D_H (REG_COMBO_PHY0_P3_BASE + 0x7B) 3169 #define REG_COMBO_PHY0_P3_3E_L (REG_COMBO_PHY0_P3_BASE + 0x7C) 3170 #define REG_COMBO_PHY0_P3_3E_H (REG_COMBO_PHY0_P3_BASE + 0x7D) 3171 #define REG_COMBO_PHY0_P3_3F_L (REG_COMBO_PHY0_P3_BASE + 0x7E) 3172 #define REG_COMBO_PHY0_P3_3F_H (REG_COMBO_PHY0_P3_BASE + 0x7F) 3173 #define REG_COMBO_PHY0_P3_40_L (REG_COMBO_PHY0_P3_BASE + 0x80) 3174 #define REG_COMBO_PHY0_P3_40_H (REG_COMBO_PHY0_P3_BASE + 0x81) 3175 #define REG_COMBO_PHY0_P3_41_L (REG_COMBO_PHY0_P3_BASE + 0x82) 3176 #define REG_COMBO_PHY0_P3_41_H (REG_COMBO_PHY0_P3_BASE + 0x83) 3177 #define REG_COMBO_PHY0_P3_42_L (REG_COMBO_PHY0_P3_BASE + 0x84) 3178 #define REG_COMBO_PHY0_P3_42_H (REG_COMBO_PHY0_P3_BASE + 0x85) 3179 #define REG_COMBO_PHY0_P3_43_L (REG_COMBO_PHY0_P3_BASE + 0x86) 3180 #define REG_COMBO_PHY0_P3_43_H (REG_COMBO_PHY0_P3_BASE + 0x87) 3181 #define REG_COMBO_PHY0_P3_44_L (REG_COMBO_PHY0_P3_BASE + 0x88) 3182 #define REG_COMBO_PHY0_P3_44_H (REG_COMBO_PHY0_P3_BASE + 0x89) 3183 #define REG_COMBO_PHY0_P3_45_L (REG_COMBO_PHY0_P3_BASE + 0x8A) 3184 #define REG_COMBO_PHY0_P3_45_H (REG_COMBO_PHY0_P3_BASE + 0x8B) 3185 #define REG_COMBO_PHY0_P3_46_L (REG_COMBO_PHY0_P3_BASE + 0x8C) 3186 #define REG_COMBO_PHY0_P3_46_H (REG_COMBO_PHY0_P3_BASE + 0x8D) 3187 #define REG_COMBO_PHY0_P3_47_L (REG_COMBO_PHY0_P3_BASE + 0x8E) 3188 #define REG_COMBO_PHY0_P3_47_H (REG_COMBO_PHY0_P3_BASE + 0x8F) 3189 #define REG_COMBO_PHY0_P3_48_L (REG_COMBO_PHY0_P3_BASE + 0x90) 3190 #define REG_COMBO_PHY0_P3_48_H (REG_COMBO_PHY0_P3_BASE + 0x91) 3191 #define REG_COMBO_PHY0_P3_49_L (REG_COMBO_PHY0_P3_BASE + 0x92) 3192 #define REG_COMBO_PHY0_P3_49_H (REG_COMBO_PHY0_P3_BASE + 0x93) 3193 #define REG_COMBO_PHY0_P3_4A_L (REG_COMBO_PHY0_P3_BASE + 0x94) 3194 #define REG_COMBO_PHY0_P3_4A_H (REG_COMBO_PHY0_P3_BASE + 0x95) 3195 #define REG_COMBO_PHY0_P3_4B_L (REG_COMBO_PHY0_P3_BASE + 0x96) 3196 #define REG_COMBO_PHY0_P3_4B_H (REG_COMBO_PHY0_P3_BASE + 0x97) 3197 #define REG_COMBO_PHY0_P3_4C_L (REG_COMBO_PHY0_P3_BASE + 0x98) 3198 #define REG_COMBO_PHY0_P3_4C_H (REG_COMBO_PHY0_P3_BASE + 0x99) 3199 #define REG_COMBO_PHY0_P3_4D_L (REG_COMBO_PHY0_P3_BASE + 0x9A) 3200 #define REG_COMBO_PHY0_P3_4D_H (REG_COMBO_PHY0_P3_BASE + 0x9B) 3201 #define REG_COMBO_PHY0_P3_4E_L (REG_COMBO_PHY0_P3_BASE + 0x9C) 3202 #define REG_COMBO_PHY0_P3_4E_H (REG_COMBO_PHY0_P3_BASE + 0x9D) 3203 #define REG_COMBO_PHY0_P3_4F_L (REG_COMBO_PHY0_P3_BASE + 0x9E) 3204 #define REG_COMBO_PHY0_P3_4F_H (REG_COMBO_PHY0_P3_BASE + 0x9F) 3205 #define REG_COMBO_PHY0_P3_50_L (REG_COMBO_PHY0_P3_BASE + 0xA0) 3206 #define REG_COMBO_PHY0_P3_50_H (REG_COMBO_PHY0_P3_BASE + 0xA1) 3207 #define REG_COMBO_PHY0_P3_51_L (REG_COMBO_PHY0_P3_BASE + 0xA2) 3208 #define REG_COMBO_PHY0_P3_51_H (REG_COMBO_PHY0_P3_BASE + 0xA3) 3209 #define REG_COMBO_PHY0_P3_52_L (REG_COMBO_PHY0_P3_BASE + 0xA4) 3210 #define REG_COMBO_PHY0_P3_52_H (REG_COMBO_PHY0_P3_BASE + 0xA5) 3211 #define REG_COMBO_PHY0_P3_53_L (REG_COMBO_PHY0_P3_BASE + 0xA6) 3212 #define REG_COMBO_PHY0_P3_53_H (REG_COMBO_PHY0_P3_BASE + 0xA7) 3213 #define REG_COMBO_PHY0_P3_54_L (REG_COMBO_PHY0_P3_BASE + 0xA8) 3214 #define REG_COMBO_PHY0_P3_54_H (REG_COMBO_PHY0_P3_BASE + 0xA9) 3215 #define REG_COMBO_PHY0_P3_55_L (REG_COMBO_PHY0_P3_BASE + 0xAA) 3216 #define REG_COMBO_PHY0_P3_55_H (REG_COMBO_PHY0_P3_BASE + 0xAB) 3217 #define REG_COMBO_PHY0_P3_56_L (REG_COMBO_PHY0_P3_BASE + 0xAC) 3218 #define REG_COMBO_PHY0_P3_56_H (REG_COMBO_PHY0_P3_BASE + 0xAD) 3219 #define REG_COMBO_PHY0_P3_57_L (REG_COMBO_PHY0_P3_BASE + 0xAE) 3220 #define REG_COMBO_PHY0_P3_57_H (REG_COMBO_PHY0_P3_BASE + 0xAF) 3221 #define REG_COMBO_PHY0_P3_58_L (REG_COMBO_PHY0_P3_BASE + 0xB0) 3222 #define REG_COMBO_PHY0_P3_58_H (REG_COMBO_PHY0_P3_BASE + 0xB1) 3223 #define REG_COMBO_PHY0_P3_59_L (REG_COMBO_PHY0_P3_BASE + 0xB2) 3224 #define REG_COMBO_PHY0_P3_59_H (REG_COMBO_PHY0_P3_BASE + 0xB3) 3225 #define REG_COMBO_PHY0_P3_5A_L (REG_COMBO_PHY0_P3_BASE + 0xB4) 3226 #define REG_COMBO_PHY0_P3_5A_H (REG_COMBO_PHY0_P3_BASE + 0xB5) 3227 #define REG_COMBO_PHY0_P3_5B_L (REG_COMBO_PHY0_P3_BASE + 0xB6) 3228 #define REG_COMBO_PHY0_P3_5B_H (REG_COMBO_PHY0_P3_BASE + 0xB7) 3229 #define REG_COMBO_PHY0_P3_5C_L (REG_COMBO_PHY0_P3_BASE + 0xB8) 3230 #define REG_COMBO_PHY0_P3_5C_H (REG_COMBO_PHY0_P3_BASE + 0xB9) 3231 #define REG_COMBO_PHY0_P3_5D_L (REG_COMBO_PHY0_P3_BASE + 0xBA) 3232 #define REG_COMBO_PHY0_P3_5D_H (REG_COMBO_PHY0_P3_BASE + 0xBB) 3233 #define REG_COMBO_PHY0_P3_5E_L (REG_COMBO_PHY0_P3_BASE + 0xBC) 3234 #define REG_COMBO_PHY0_P3_5E_H (REG_COMBO_PHY0_P3_BASE + 0xBD) 3235 #define REG_COMBO_PHY0_P3_5F_L (REG_COMBO_PHY0_P3_BASE + 0xBE) 3236 #define REG_COMBO_PHY0_P3_5F_H (REG_COMBO_PHY0_P3_BASE + 0xBF) 3237 #define REG_COMBO_PHY0_P3_60_L (REG_COMBO_PHY0_P3_BASE + 0xC0) 3238 #define REG_COMBO_PHY0_P3_60_H (REG_COMBO_PHY0_P3_BASE + 0xC1) 3239 #define REG_COMBO_PHY0_P3_61_L (REG_COMBO_PHY0_P3_BASE + 0xC2) 3240 #define REG_COMBO_PHY0_P3_61_H (REG_COMBO_PHY0_P3_BASE + 0xC3) 3241 #define REG_COMBO_PHY0_P3_62_L (REG_COMBO_PHY0_P3_BASE + 0xC4) 3242 #define REG_COMBO_PHY0_P3_62_H (REG_COMBO_PHY0_P3_BASE + 0xC5) 3243 #define REG_COMBO_PHY0_P3_63_L (REG_COMBO_PHY0_P3_BASE + 0xC6) 3244 #define REG_COMBO_PHY0_P3_63_H (REG_COMBO_PHY0_P3_BASE + 0xC7) 3245 #define REG_COMBO_PHY0_P3_64_L (REG_COMBO_PHY0_P3_BASE + 0xC8) 3246 #define REG_COMBO_PHY0_P3_64_H (REG_COMBO_PHY0_P3_BASE + 0xC9) 3247 #define REG_COMBO_PHY0_P3_65_L (REG_COMBO_PHY0_P3_BASE + 0xCA) 3248 #define REG_COMBO_PHY0_P3_65_H (REG_COMBO_PHY0_P3_BASE + 0xCB) 3249 #define REG_COMBO_PHY0_P3_66_L (REG_COMBO_PHY0_P3_BASE + 0xCC) 3250 #define REG_COMBO_PHY0_P3_66_H (REG_COMBO_PHY0_P3_BASE + 0xCD) 3251 #define REG_COMBO_PHY0_P3_67_L (REG_COMBO_PHY0_P3_BASE + 0xCE) 3252 #define REG_COMBO_PHY0_P3_67_H (REG_COMBO_PHY0_P3_BASE + 0xCF) 3253 #define REG_COMBO_PHY0_P3_68_L (REG_COMBO_PHY0_P3_BASE + 0xD0) 3254 #define REG_COMBO_PHY0_P3_68_H (REG_COMBO_PHY0_P3_BASE + 0xD1) 3255 #define REG_COMBO_PHY0_P3_69_L (REG_COMBO_PHY0_P3_BASE + 0xD2) 3256 #define REG_COMBO_PHY0_P3_69_H (REG_COMBO_PHY0_P3_BASE + 0xD3) 3257 #define REG_COMBO_PHY0_P3_6A_L (REG_COMBO_PHY0_P3_BASE + 0xD4) 3258 #define REG_COMBO_PHY0_P3_6A_H (REG_COMBO_PHY0_P3_BASE + 0xD5) 3259 #define REG_COMBO_PHY0_P3_6B_L (REG_COMBO_PHY0_P3_BASE + 0xD6) 3260 #define REG_COMBO_PHY0_P3_6B_H (REG_COMBO_PHY0_P3_BASE + 0xD7) 3261 #define REG_COMBO_PHY0_P3_6C_L (REG_COMBO_PHY0_P3_BASE + 0xD8) 3262 #define REG_COMBO_PHY0_P3_6C_H (REG_COMBO_PHY0_P3_BASE + 0xD9) 3263 #define REG_COMBO_PHY0_P3_6D_L (REG_COMBO_PHY0_P3_BASE + 0xDA) 3264 #define REG_COMBO_PHY0_P3_6D_H (REG_COMBO_PHY0_P3_BASE + 0xDB) 3265 #define REG_COMBO_PHY0_P3_6E_L (REG_COMBO_PHY0_P3_BASE + 0xDC) 3266 #define REG_COMBO_PHY0_P3_6E_H (REG_COMBO_PHY0_P3_BASE + 0xDD) 3267 #define REG_COMBO_PHY0_P3_6F_L (REG_COMBO_PHY0_P3_BASE + 0xDE) 3268 #define REG_COMBO_PHY0_P3_6F_H (REG_COMBO_PHY0_P3_BASE + 0xDF) 3269 #define REG_COMBO_PHY0_P3_70_L (REG_COMBO_PHY0_P3_BASE + 0xE0) 3270 #define REG_COMBO_PHY0_P3_70_H (REG_COMBO_PHY0_P3_BASE + 0xE1) 3271 #define REG_COMBO_PHY0_P3_71_L (REG_COMBO_PHY0_P3_BASE + 0xE2) 3272 #define REG_COMBO_PHY0_P3_71_H (REG_COMBO_PHY0_P3_BASE + 0xE3) 3273 #define REG_COMBO_PHY0_P3_72_L (REG_COMBO_PHY0_P3_BASE + 0xE4) 3274 #define REG_COMBO_PHY0_P3_72_H (REG_COMBO_PHY0_P3_BASE + 0xE5) 3275 #define REG_COMBO_PHY0_P3_73_L (REG_COMBO_PHY0_P3_BASE + 0xE6) 3276 #define REG_COMBO_PHY0_P3_73_H (REG_COMBO_PHY0_P3_BASE + 0xE7) 3277 #define REG_COMBO_PHY0_P3_74_L (REG_COMBO_PHY0_P3_BASE + 0xE8) 3278 #define REG_COMBO_PHY0_P3_74_H (REG_COMBO_PHY0_P3_BASE + 0xE9) 3279 #define REG_COMBO_PHY0_P3_75_L (REG_COMBO_PHY0_P3_BASE + 0xEA) 3280 #define REG_COMBO_PHY0_P3_75_H (REG_COMBO_PHY0_P3_BASE + 0xEB) 3281 #define REG_COMBO_PHY0_P3_76_L (REG_COMBO_PHY0_P3_BASE + 0xEC) 3282 #define REG_COMBO_PHY0_P3_76_H (REG_COMBO_PHY0_P3_BASE + 0xED) 3283 #define REG_COMBO_PHY0_P3_77_L (REG_COMBO_PHY0_P3_BASE + 0xEE) 3284 #define REG_COMBO_PHY0_P3_77_H (REG_COMBO_PHY0_P3_BASE + 0xEF) 3285 #define REG_COMBO_PHY0_P3_78_L (REG_COMBO_PHY0_P3_BASE + 0xF0) 3286 #define REG_COMBO_PHY0_P3_78_H (REG_COMBO_PHY0_P3_BASE + 0xF1) 3287 #define REG_COMBO_PHY0_P3_79_L (REG_COMBO_PHY0_P3_BASE + 0xF2) 3288 #define REG_COMBO_PHY0_P3_79_H (REG_COMBO_PHY0_P3_BASE + 0xF3) 3289 #define REG_COMBO_PHY0_P3_7A_L (REG_COMBO_PHY0_P3_BASE + 0xF4) 3290 #define REG_COMBO_PHY0_P3_7A_H (REG_COMBO_PHY0_P3_BASE + 0xF5) 3291 #define REG_COMBO_PHY0_P3_7B_L (REG_COMBO_PHY0_P3_BASE + 0xF6) 3292 #define REG_COMBO_PHY0_P3_7B_H (REG_COMBO_PHY0_P3_BASE + 0xF7) 3293 #define REG_COMBO_PHY0_P3_7C_L (REG_COMBO_PHY0_P3_BASE + 0xF8) 3294 #define REG_COMBO_PHY0_P3_7C_H (REG_COMBO_PHY0_P3_BASE + 0xF9) 3295 #define REG_COMBO_PHY0_P3_7D_L (REG_COMBO_PHY0_P3_BASE + 0xFA) 3296 #define REG_COMBO_PHY0_P3_7D_H (REG_COMBO_PHY0_P3_BASE + 0xFB) 3297 #define REG_COMBO_PHY0_P3_7E_L (REG_COMBO_PHY0_P3_BASE + 0xFC) 3298 #define REG_COMBO_PHY0_P3_7E_H (REG_COMBO_PHY0_P3_BASE + 0xFD) 3299 #define REG_COMBO_PHY0_P3_7F_L (REG_COMBO_PHY0_P3_BASE + 0xFE) 3300 #define REG_COMBO_PHY0_P3_7F_H (REG_COMBO_PHY0_P3_BASE + 0xFF) 3301 3302 // COMBO_PHY1_P3 3303 #define REG_COMBO_PHY1_P3_00_L (REG_COMBO_PHY1_P3_BASE + 0x00) 3304 #define REG_COMBO_PHY1_P3_00_H (REG_COMBO_PHY1_P3_BASE + 0x01) 3305 #define REG_COMBO_PHY1_P3_01_L (REG_COMBO_PHY1_P3_BASE + 0x02) 3306 #define REG_COMBO_PHY1_P3_01_H (REG_COMBO_PHY1_P3_BASE + 0x03) 3307 #define REG_COMBO_PHY1_P3_02_L (REG_COMBO_PHY1_P3_BASE + 0x04) 3308 #define REG_COMBO_PHY1_P3_02_H (REG_COMBO_PHY1_P3_BASE + 0x05) 3309 #define REG_COMBO_PHY1_P3_03_L (REG_COMBO_PHY1_P3_BASE + 0x06) 3310 #define REG_COMBO_PHY1_P3_03_H (REG_COMBO_PHY1_P3_BASE + 0x07) 3311 #define REG_COMBO_PHY1_P3_04_L (REG_COMBO_PHY1_P3_BASE + 0x08) 3312 #define REG_COMBO_PHY1_P3_04_H (REG_COMBO_PHY1_P3_BASE + 0x09) 3313 #define REG_COMBO_PHY1_P3_05_L (REG_COMBO_PHY1_P3_BASE + 0x0A) 3314 #define REG_COMBO_PHY1_P3_05_H (REG_COMBO_PHY1_P3_BASE + 0x0B) 3315 #define REG_COMBO_PHY1_P3_06_L (REG_COMBO_PHY1_P3_BASE + 0x0C) 3316 #define REG_COMBO_PHY1_P3_06_H (REG_COMBO_PHY1_P3_BASE + 0x0D) 3317 #define REG_COMBO_PHY1_P3_07_L (REG_COMBO_PHY1_P3_BASE + 0x0E) 3318 #define REG_COMBO_PHY1_P3_07_H (REG_COMBO_PHY1_P3_BASE + 0x0F) 3319 #define REG_COMBO_PHY1_P3_08_L (REG_COMBO_PHY1_P3_BASE + 0x10) 3320 #define REG_COMBO_PHY1_P3_08_H (REG_COMBO_PHY1_P3_BASE + 0x11) 3321 #define REG_COMBO_PHY1_P3_09_L (REG_COMBO_PHY1_P3_BASE + 0x12) 3322 #define REG_COMBO_PHY1_P3_09_H (REG_COMBO_PHY1_P3_BASE + 0x13) 3323 #define REG_COMBO_PHY1_P3_0A_L (REG_COMBO_PHY1_P3_BASE + 0x14) 3324 #define REG_COMBO_PHY1_P3_0A_H (REG_COMBO_PHY1_P3_BASE + 0x15) 3325 #define REG_COMBO_PHY1_P3_0B_L (REG_COMBO_PHY1_P3_BASE + 0x16) 3326 #define REG_COMBO_PHY1_P3_0B_H (REG_COMBO_PHY1_P3_BASE + 0x17) 3327 #define REG_COMBO_PHY1_P3_0C_L (REG_COMBO_PHY1_P3_BASE + 0x18) 3328 #define REG_COMBO_PHY1_P3_0C_H (REG_COMBO_PHY1_P3_BASE + 0x19) 3329 #define REG_COMBO_PHY1_P3_0D_L (REG_COMBO_PHY1_P3_BASE + 0x1A) 3330 #define REG_COMBO_PHY1_P3_0D_H (REG_COMBO_PHY1_P3_BASE + 0x1B) 3331 #define REG_COMBO_PHY1_P3_0E_L (REG_COMBO_PHY1_P3_BASE + 0x1C) 3332 #define REG_COMBO_PHY1_P3_0E_H (REG_COMBO_PHY1_P3_BASE + 0x1D) 3333 #define REG_COMBO_PHY1_P3_0F_L (REG_COMBO_PHY1_P3_BASE + 0x1E) 3334 #define REG_COMBO_PHY1_P3_0F_H (REG_COMBO_PHY1_P3_BASE + 0x1F) 3335 #define REG_COMBO_PHY1_P3_10_L (REG_COMBO_PHY1_P3_BASE + 0x20) 3336 #define REG_COMBO_PHY1_P3_10_H (REG_COMBO_PHY1_P3_BASE + 0x21) 3337 #define REG_COMBO_PHY1_P3_11_L (REG_COMBO_PHY1_P3_BASE + 0x22) 3338 #define REG_COMBO_PHY1_P3_11_H (REG_COMBO_PHY1_P3_BASE + 0x23) 3339 #define REG_COMBO_PHY1_P3_12_L (REG_COMBO_PHY1_P3_BASE + 0x24) 3340 #define REG_COMBO_PHY1_P3_12_H (REG_COMBO_PHY1_P3_BASE + 0x25) 3341 #define REG_COMBO_PHY1_P3_13_L (REG_COMBO_PHY1_P3_BASE + 0x26) 3342 #define REG_COMBO_PHY1_P3_13_H (REG_COMBO_PHY1_P3_BASE + 0x27) 3343 #define REG_COMBO_PHY1_P3_14_L (REG_COMBO_PHY1_P3_BASE + 0x28) 3344 #define REG_COMBO_PHY1_P3_14_H (REG_COMBO_PHY1_P3_BASE + 0x29) 3345 #define REG_COMBO_PHY1_P3_15_L (REG_COMBO_PHY1_P3_BASE + 0x2A) 3346 #define REG_COMBO_PHY1_P3_15_H (REG_COMBO_PHY1_P3_BASE + 0x2B) 3347 #define REG_COMBO_PHY1_P3_16_L (REG_COMBO_PHY1_P3_BASE + 0x2C) 3348 #define REG_COMBO_PHY1_P3_16_H (REG_COMBO_PHY1_P3_BASE + 0x2D) 3349 #define REG_COMBO_PHY1_P3_17_L (REG_COMBO_PHY1_P3_BASE + 0x2E) 3350 #define REG_COMBO_PHY1_P3_17_H (REG_COMBO_PHY1_P3_BASE + 0x2F) 3351 #define REG_COMBO_PHY1_P3_18_L (REG_COMBO_PHY1_P3_BASE + 0x30) 3352 #define REG_COMBO_PHY1_P3_18_H (REG_COMBO_PHY1_P3_BASE + 0x31) 3353 #define REG_COMBO_PHY1_P3_19_L (REG_COMBO_PHY1_P3_BASE + 0x32) 3354 #define REG_COMBO_PHY1_P3_19_H (REG_COMBO_PHY1_P3_BASE + 0x33) 3355 #define REG_COMBO_PHY1_P3_1A_L (REG_COMBO_PHY1_P3_BASE + 0x34) 3356 #define REG_COMBO_PHY1_P3_1A_H (REG_COMBO_PHY1_P3_BASE + 0x35) 3357 #define REG_COMBO_PHY1_P3_1B_L (REG_COMBO_PHY1_P3_BASE + 0x36) 3358 #define REG_COMBO_PHY1_P3_1B_H (REG_COMBO_PHY1_P3_BASE + 0x37) 3359 #define REG_COMBO_PHY1_P3_1C_L (REG_COMBO_PHY1_P3_BASE + 0x38) 3360 #define REG_COMBO_PHY1_P3_1C_H (REG_COMBO_PHY1_P3_BASE + 0x39) 3361 #define REG_COMBO_PHY1_P3_1D_L (REG_COMBO_PHY1_P3_BASE + 0x3A) 3362 #define REG_COMBO_PHY1_P3_1D_H (REG_COMBO_PHY1_P3_BASE + 0x3B) 3363 #define REG_COMBO_PHY1_P3_1E_L (REG_COMBO_PHY1_P3_BASE + 0x3C) 3364 #define REG_COMBO_PHY1_P3_1E_H (REG_COMBO_PHY1_P3_BASE + 0x3D) 3365 #define REG_COMBO_PHY1_P3_1F_L (REG_COMBO_PHY1_P3_BASE + 0x3E) 3366 #define REG_COMBO_PHY1_P3_1F_H (REG_COMBO_PHY1_P3_BASE + 0x3F) 3367 #define REG_COMBO_PHY1_P3_20_L (REG_COMBO_PHY1_P3_BASE + 0x40) 3368 #define REG_COMBO_PHY1_P3_20_H (REG_COMBO_PHY1_P3_BASE + 0x41) 3369 #define REG_COMBO_PHY1_P3_21_L (REG_COMBO_PHY1_P3_BASE + 0x42) 3370 #define REG_COMBO_PHY1_P3_21_H (REG_COMBO_PHY1_P3_BASE + 0x43) 3371 #define REG_COMBO_PHY1_P3_22_L (REG_COMBO_PHY1_P3_BASE + 0x44) 3372 #define REG_COMBO_PHY1_P3_22_H (REG_COMBO_PHY1_P3_BASE + 0x45) 3373 #define REG_COMBO_PHY1_P3_23_L (REG_COMBO_PHY1_P3_BASE + 0x46) 3374 #define REG_COMBO_PHY1_P3_23_H (REG_COMBO_PHY1_P3_BASE + 0x47) 3375 #define REG_COMBO_PHY1_P3_24_L (REG_COMBO_PHY1_P3_BASE + 0x48) 3376 #define REG_COMBO_PHY1_P3_24_H (REG_COMBO_PHY1_P3_BASE + 0x49) 3377 #define REG_COMBO_PHY1_P3_25_L (REG_COMBO_PHY1_P3_BASE + 0x4A) 3378 #define REG_COMBO_PHY1_P3_25_H (REG_COMBO_PHY1_P3_BASE + 0x4B) 3379 #define REG_COMBO_PHY1_P3_26_L (REG_COMBO_PHY1_P3_BASE + 0x4C) 3380 #define REG_COMBO_PHY1_P3_26_H (REG_COMBO_PHY1_P3_BASE + 0x4D) 3381 #define REG_COMBO_PHY1_P3_27_L (REG_COMBO_PHY1_P3_BASE + 0x4E) 3382 #define REG_COMBO_PHY1_P3_27_H (REG_COMBO_PHY1_P3_BASE + 0x4F) 3383 #define REG_COMBO_PHY1_P3_28_L (REG_COMBO_PHY1_P3_BASE + 0x50) 3384 #define REG_COMBO_PHY1_P3_28_H (REG_COMBO_PHY1_P3_BASE + 0x51) 3385 #define REG_COMBO_PHY1_P3_29_L (REG_COMBO_PHY1_P3_BASE + 0x52) 3386 #define REG_COMBO_PHY1_P3_29_H (REG_COMBO_PHY1_P3_BASE + 0x53) 3387 #define REG_COMBO_PHY1_P3_2A_L (REG_COMBO_PHY1_P3_BASE + 0x54) 3388 #define REG_COMBO_PHY1_P3_2A_H (REG_COMBO_PHY1_P3_BASE + 0x55) 3389 #define REG_COMBO_PHY1_P3_2B_L (REG_COMBO_PHY1_P3_BASE + 0x56) 3390 #define REG_COMBO_PHY1_P3_2B_H (REG_COMBO_PHY1_P3_BASE + 0x57) 3391 #define REG_COMBO_PHY1_P3_2C_L (REG_COMBO_PHY1_P3_BASE + 0x58) 3392 #define REG_COMBO_PHY1_P3_2C_H (REG_COMBO_PHY1_P3_BASE + 0x59) 3393 #define REG_COMBO_PHY1_P3_2D_L (REG_COMBO_PHY1_P3_BASE + 0x5A) 3394 #define REG_COMBO_PHY1_P3_2D_H (REG_COMBO_PHY1_P3_BASE + 0x5B) 3395 #define REG_COMBO_PHY1_P3_2E_L (REG_COMBO_PHY1_P3_BASE + 0x5C) 3396 #define REG_COMBO_PHY1_P3_2E_H (REG_COMBO_PHY1_P3_BASE + 0x5D) 3397 #define REG_COMBO_PHY1_P3_2F_L (REG_COMBO_PHY1_P3_BASE + 0x5E) 3398 #define REG_COMBO_PHY1_P3_2F_H (REG_COMBO_PHY1_P3_BASE + 0x5F) 3399 #define REG_COMBO_PHY1_P3_30_L (REG_COMBO_PHY1_P3_BASE + 0x60) 3400 #define REG_COMBO_PHY1_P3_30_H (REG_COMBO_PHY1_P3_BASE + 0x61) 3401 #define REG_COMBO_PHY1_P3_31_L (REG_COMBO_PHY1_P3_BASE + 0x62) 3402 #define REG_COMBO_PHY1_P3_31_H (REG_COMBO_PHY1_P3_BASE + 0x63) 3403 #define REG_COMBO_PHY1_P3_32_L (REG_COMBO_PHY1_P3_BASE + 0x64) 3404 #define REG_COMBO_PHY1_P3_32_H (REG_COMBO_PHY1_P3_BASE + 0x65) 3405 #define REG_COMBO_PHY1_P3_33_L (REG_COMBO_PHY1_P3_BASE + 0x66) 3406 #define REG_COMBO_PHY1_P3_33_H (REG_COMBO_PHY1_P3_BASE + 0x67) 3407 #define REG_COMBO_PHY1_P3_34_L (REG_COMBO_PHY1_P3_BASE + 0x68) 3408 #define REG_COMBO_PHY1_P3_34_H (REG_COMBO_PHY1_P3_BASE + 0x69) 3409 #define REG_COMBO_PHY1_P3_35_L (REG_COMBO_PHY1_P3_BASE + 0x6A) 3410 #define REG_COMBO_PHY1_P3_35_H (REG_COMBO_PHY1_P3_BASE + 0x6B) 3411 #define REG_COMBO_PHY1_P3_36_L (REG_COMBO_PHY1_P3_BASE + 0x6C) 3412 #define REG_COMBO_PHY1_P3_36_H (REG_COMBO_PHY1_P3_BASE + 0x6D) 3413 #define REG_COMBO_PHY1_P3_37_L (REG_COMBO_PHY1_P3_BASE + 0x6E) 3414 #define REG_COMBO_PHY1_P3_37_H (REG_COMBO_PHY1_P3_BASE + 0x6F) 3415 #define REG_COMBO_PHY1_P3_38_L (REG_COMBO_PHY1_P3_BASE + 0x70) 3416 #define REG_COMBO_PHY1_P3_38_H (REG_COMBO_PHY1_P3_BASE + 0x71) 3417 #define REG_COMBO_PHY1_P3_39_L (REG_COMBO_PHY1_P3_BASE + 0x72) 3418 #define REG_COMBO_PHY1_P3_39_H (REG_COMBO_PHY1_P3_BASE + 0x73) 3419 #define REG_COMBO_PHY1_P3_3A_L (REG_COMBO_PHY1_P3_BASE + 0x74) 3420 #define REG_COMBO_PHY1_P3_3A_H (REG_COMBO_PHY1_P3_BASE + 0x75) 3421 #define REG_COMBO_PHY1_P3_3B_L (REG_COMBO_PHY1_P3_BASE + 0x76) 3422 #define REG_COMBO_PHY1_P3_3B_H (REG_COMBO_PHY1_P3_BASE + 0x77) 3423 #define REG_COMBO_PHY1_P3_3C_L (REG_COMBO_PHY1_P3_BASE + 0x78) 3424 #define REG_COMBO_PHY1_P3_3C_H (REG_COMBO_PHY1_P3_BASE + 0x79) 3425 #define REG_COMBO_PHY1_P3_3D_L (REG_COMBO_PHY1_P3_BASE + 0x7A) 3426 #define REG_COMBO_PHY1_P3_3D_H (REG_COMBO_PHY1_P3_BASE + 0x7B) 3427 #define REG_COMBO_PHY1_P3_3E_L (REG_COMBO_PHY1_P3_BASE + 0x7C) 3428 #define REG_COMBO_PHY1_P3_3E_H (REG_COMBO_PHY1_P3_BASE + 0x7D) 3429 #define REG_COMBO_PHY1_P3_3F_L (REG_COMBO_PHY1_P3_BASE + 0x7E) 3430 #define REG_COMBO_PHY1_P3_3F_H (REG_COMBO_PHY1_P3_BASE + 0x7F) 3431 #define REG_COMBO_PHY1_P3_40_L (REG_COMBO_PHY1_P3_BASE + 0x80) 3432 #define REG_COMBO_PHY1_P3_40_H (REG_COMBO_PHY1_P3_BASE + 0x81) 3433 #define REG_COMBO_PHY1_P3_41_L (REG_COMBO_PHY1_P3_BASE + 0x82) 3434 #define REG_COMBO_PHY1_P3_41_H (REG_COMBO_PHY1_P3_BASE + 0x83) 3435 #define REG_COMBO_PHY1_P3_42_L (REG_COMBO_PHY1_P3_BASE + 0x84) 3436 #define REG_COMBO_PHY1_P3_42_H (REG_COMBO_PHY1_P3_BASE + 0x85) 3437 #define REG_COMBO_PHY1_P3_43_L (REG_COMBO_PHY1_P3_BASE + 0x86) 3438 #define REG_COMBO_PHY1_P3_43_H (REG_COMBO_PHY1_P3_BASE + 0x87) 3439 #define REG_COMBO_PHY1_P3_44_L (REG_COMBO_PHY1_P3_BASE + 0x88) 3440 #define REG_COMBO_PHY1_P3_44_H (REG_COMBO_PHY1_P3_BASE + 0x89) 3441 #define REG_COMBO_PHY1_P3_45_L (REG_COMBO_PHY1_P3_BASE + 0x8A) 3442 #define REG_COMBO_PHY1_P3_45_H (REG_COMBO_PHY1_P3_BASE + 0x8B) 3443 #define REG_COMBO_PHY1_P3_46_L (REG_COMBO_PHY1_P3_BASE + 0x8C) 3444 #define REG_COMBO_PHY1_P3_46_H (REG_COMBO_PHY1_P3_BASE + 0x8D) 3445 #define REG_COMBO_PHY1_P3_47_L (REG_COMBO_PHY1_P3_BASE + 0x8E) 3446 #define REG_COMBO_PHY1_P3_47_H (REG_COMBO_PHY1_P3_BASE + 0x8F) 3447 #define REG_COMBO_PHY1_P3_48_L (REG_COMBO_PHY1_P3_BASE + 0x90) 3448 #define REG_COMBO_PHY1_P3_48_H (REG_COMBO_PHY1_P3_BASE + 0x91) 3449 #define REG_COMBO_PHY1_P3_49_L (REG_COMBO_PHY1_P3_BASE + 0x92) 3450 #define REG_COMBO_PHY1_P3_49_H (REG_COMBO_PHY1_P3_BASE + 0x93) 3451 #define REG_COMBO_PHY1_P3_4A_L (REG_COMBO_PHY1_P3_BASE + 0x94) 3452 #define REG_COMBO_PHY1_P3_4A_H (REG_COMBO_PHY1_P3_BASE + 0x95) 3453 #define REG_COMBO_PHY1_P3_4B_L (REG_COMBO_PHY1_P3_BASE + 0x96) 3454 #define REG_COMBO_PHY1_P3_4B_H (REG_COMBO_PHY1_P3_BASE + 0x97) 3455 #define REG_COMBO_PHY1_P3_4C_L (REG_COMBO_PHY1_P3_BASE + 0x98) 3456 #define REG_COMBO_PHY1_P3_4C_H (REG_COMBO_PHY1_P3_BASE + 0x99) 3457 #define REG_COMBO_PHY1_P3_4D_L (REG_COMBO_PHY1_P3_BASE + 0x9A) 3458 #define REG_COMBO_PHY1_P3_4D_H (REG_COMBO_PHY1_P3_BASE + 0x9B) 3459 #define REG_COMBO_PHY1_P3_4E_L (REG_COMBO_PHY1_P3_BASE + 0x9C) 3460 #define REG_COMBO_PHY1_P3_4E_H (REG_COMBO_PHY1_P3_BASE + 0x9D) 3461 #define REG_COMBO_PHY1_P3_4F_L (REG_COMBO_PHY1_P3_BASE + 0x9E) 3462 #define REG_COMBO_PHY1_P3_4F_H (REG_COMBO_PHY1_P3_BASE + 0x9F) 3463 #define REG_COMBO_PHY1_P3_50_L (REG_COMBO_PHY1_P3_BASE + 0xA0) 3464 #define REG_COMBO_PHY1_P3_50_H (REG_COMBO_PHY1_P3_BASE + 0xA1) 3465 #define REG_COMBO_PHY1_P3_51_L (REG_COMBO_PHY1_P3_BASE + 0xA2) 3466 #define REG_COMBO_PHY1_P3_51_H (REG_COMBO_PHY1_P3_BASE + 0xA3) 3467 #define REG_COMBO_PHY1_P3_52_L (REG_COMBO_PHY1_P3_BASE + 0xA4) 3468 #define REG_COMBO_PHY1_P3_52_H (REG_COMBO_PHY1_P3_BASE + 0xA5) 3469 #define REG_COMBO_PHY1_P3_53_L (REG_COMBO_PHY1_P3_BASE + 0xA6) 3470 #define REG_COMBO_PHY1_P3_53_H (REG_COMBO_PHY1_P3_BASE + 0xA7) 3471 #define REG_COMBO_PHY1_P3_54_L (REG_COMBO_PHY1_P3_BASE + 0xA8) 3472 #define REG_COMBO_PHY1_P3_54_H (REG_COMBO_PHY1_P3_BASE + 0xA9) 3473 #define REG_COMBO_PHY1_P3_55_L (REG_COMBO_PHY1_P3_BASE + 0xAA) 3474 #define REG_COMBO_PHY1_P3_55_H (REG_COMBO_PHY1_P3_BASE + 0xAB) 3475 #define REG_COMBO_PHY1_P3_56_L (REG_COMBO_PHY1_P3_BASE + 0xAC) 3476 #define REG_COMBO_PHY1_P3_56_H (REG_COMBO_PHY1_P3_BASE + 0xAD) 3477 #define REG_COMBO_PHY1_P3_57_L (REG_COMBO_PHY1_P3_BASE + 0xAE) 3478 #define REG_COMBO_PHY1_P3_57_H (REG_COMBO_PHY1_P3_BASE + 0xAF) 3479 #define REG_COMBO_PHY1_P3_58_L (REG_COMBO_PHY1_P3_BASE + 0xB0) 3480 #define REG_COMBO_PHY1_P3_58_H (REG_COMBO_PHY1_P3_BASE + 0xB1) 3481 #define REG_COMBO_PHY1_P3_59_L (REG_COMBO_PHY1_P3_BASE + 0xB2) 3482 #define REG_COMBO_PHY1_P3_59_H (REG_COMBO_PHY1_P3_BASE + 0xB3) 3483 #define REG_COMBO_PHY1_P3_5A_L (REG_COMBO_PHY1_P3_BASE + 0xB4) 3484 #define REG_COMBO_PHY1_P3_5A_H (REG_COMBO_PHY1_P3_BASE + 0xB5) 3485 #define REG_COMBO_PHY1_P3_5B_L (REG_COMBO_PHY1_P3_BASE + 0xB6) 3486 #define REG_COMBO_PHY1_P3_5B_H (REG_COMBO_PHY1_P3_BASE + 0xB7) 3487 #define REG_COMBO_PHY1_P3_5C_L (REG_COMBO_PHY1_P3_BASE + 0xB8) 3488 #define REG_COMBO_PHY1_P3_5C_H (REG_COMBO_PHY1_P3_BASE + 0xB9) 3489 #define REG_COMBO_PHY1_P3_5D_L (REG_COMBO_PHY1_P3_BASE + 0xBA) 3490 #define REG_COMBO_PHY1_P3_5D_H (REG_COMBO_PHY1_P3_BASE + 0xBB) 3491 #define REG_COMBO_PHY1_P3_5E_L (REG_COMBO_PHY1_P3_BASE + 0xBC) 3492 #define REG_COMBO_PHY1_P3_5E_H (REG_COMBO_PHY1_P3_BASE + 0xBD) 3493 #define REG_COMBO_PHY1_P3_5F_L (REG_COMBO_PHY1_P3_BASE + 0xBE) 3494 #define REG_COMBO_PHY1_P3_5F_H (REG_COMBO_PHY1_P3_BASE + 0xBF) 3495 #define REG_COMBO_PHY1_P3_60_L (REG_COMBO_PHY1_P3_BASE + 0xC0) 3496 #define REG_COMBO_PHY1_P3_60_H (REG_COMBO_PHY1_P3_BASE + 0xC1) 3497 #define REG_COMBO_PHY1_P3_61_L (REG_COMBO_PHY1_P3_BASE + 0xC2) 3498 #define REG_COMBO_PHY1_P3_61_H (REG_COMBO_PHY1_P3_BASE + 0xC3) 3499 #define REG_COMBO_PHY1_P3_62_L (REG_COMBO_PHY1_P3_BASE + 0xC4) 3500 #define REG_COMBO_PHY1_P3_62_H (REG_COMBO_PHY1_P3_BASE + 0xC5) 3501 #define REG_COMBO_PHY1_P3_63_L (REG_COMBO_PHY1_P3_BASE + 0xC6) 3502 #define REG_COMBO_PHY1_P3_63_H (REG_COMBO_PHY1_P3_BASE + 0xC7) 3503 #define REG_COMBO_PHY1_P3_64_L (REG_COMBO_PHY1_P3_BASE + 0xC8) 3504 #define REG_COMBO_PHY1_P3_64_H (REG_COMBO_PHY1_P3_BASE + 0xC9) 3505 #define REG_COMBO_PHY1_P3_65_L (REG_COMBO_PHY1_P3_BASE + 0xCA) 3506 #define REG_COMBO_PHY1_P3_65_H (REG_COMBO_PHY1_P3_BASE + 0xCB) 3507 #define REG_COMBO_PHY1_P3_66_L (REG_COMBO_PHY1_P3_BASE + 0xCC) 3508 #define REG_COMBO_PHY1_P3_66_H (REG_COMBO_PHY1_P3_BASE + 0xCD) 3509 #define REG_COMBO_PHY1_P3_67_L (REG_COMBO_PHY1_P3_BASE + 0xCE) 3510 #define REG_COMBO_PHY1_P3_67_H (REG_COMBO_PHY1_P3_BASE + 0xCF) 3511 #define REG_COMBO_PHY1_P3_68_L (REG_COMBO_PHY1_P3_BASE + 0xD0) 3512 #define REG_COMBO_PHY1_P3_68_H (REG_COMBO_PHY1_P3_BASE + 0xD1) 3513 #define REG_COMBO_PHY1_P3_69_L (REG_COMBO_PHY1_P3_BASE + 0xD2) 3514 #define REG_COMBO_PHY1_P3_69_H (REG_COMBO_PHY1_P3_BASE + 0xD3) 3515 #define REG_COMBO_PHY1_P3_6A_L (REG_COMBO_PHY1_P3_BASE + 0xD4) 3516 #define REG_COMBO_PHY1_P3_6A_H (REG_COMBO_PHY1_P3_BASE + 0xD5) 3517 #define REG_COMBO_PHY1_P3_6B_L (REG_COMBO_PHY1_P3_BASE + 0xD6) 3518 #define REG_COMBO_PHY1_P3_6B_H (REG_COMBO_PHY1_P3_BASE + 0xD7) 3519 #define REG_COMBO_PHY1_P3_6C_L (REG_COMBO_PHY1_P3_BASE + 0xD8) 3520 #define REG_COMBO_PHY1_P3_6C_H (REG_COMBO_PHY1_P3_BASE + 0xD9) 3521 #define REG_COMBO_PHY1_P3_6D_L (REG_COMBO_PHY1_P3_BASE + 0xDA) 3522 #define REG_COMBO_PHY1_P3_6D_H (REG_COMBO_PHY1_P3_BASE + 0xDB) 3523 #define REG_COMBO_PHY1_P3_6E_L (REG_COMBO_PHY1_P3_BASE + 0xDC) 3524 #define REG_COMBO_PHY1_P3_6E_H (REG_COMBO_PHY1_P3_BASE + 0xDD) 3525 #define REG_COMBO_PHY1_P3_6F_L (REG_COMBO_PHY1_P3_BASE + 0xDE) 3526 #define REG_COMBO_PHY1_P3_6F_H (REG_COMBO_PHY1_P3_BASE + 0xDF) 3527 #define REG_COMBO_PHY1_P3_70_L (REG_COMBO_PHY1_P3_BASE + 0xE0) 3528 #define REG_COMBO_PHY1_P3_70_H (REG_COMBO_PHY1_P3_BASE + 0xE1) 3529 #define REG_COMBO_PHY1_P3_71_L (REG_COMBO_PHY1_P3_BASE + 0xE2) 3530 #define REG_COMBO_PHY1_P3_71_H (REG_COMBO_PHY1_P3_BASE + 0xE3) 3531 #define REG_COMBO_PHY1_P3_72_L (REG_COMBO_PHY1_P3_BASE + 0xE4) 3532 #define REG_COMBO_PHY1_P3_72_H (REG_COMBO_PHY1_P3_BASE + 0xE5) 3533 #define REG_COMBO_PHY1_P3_73_L (REG_COMBO_PHY1_P3_BASE + 0xE6) 3534 #define REG_COMBO_PHY1_P3_73_H (REG_COMBO_PHY1_P3_BASE + 0xE7) 3535 #define REG_COMBO_PHY1_P3_74_L (REG_COMBO_PHY1_P3_BASE + 0xE8) 3536 #define REG_COMBO_PHY1_P3_74_H (REG_COMBO_PHY1_P3_BASE + 0xE9) 3537 #define REG_COMBO_PHY1_P3_75_L (REG_COMBO_PHY1_P3_BASE + 0xEA) 3538 #define REG_COMBO_PHY1_P3_75_H (REG_COMBO_PHY1_P3_BASE + 0xEB) 3539 #define REG_COMBO_PHY1_P3_76_L (REG_COMBO_PHY1_P3_BASE + 0xEC) 3540 #define REG_COMBO_PHY1_P3_76_H (REG_COMBO_PHY1_P3_BASE + 0xED) 3541 #define REG_COMBO_PHY1_P3_77_L (REG_COMBO_PHY1_P3_BASE + 0xEE) 3542 #define REG_COMBO_PHY1_P3_77_H (REG_COMBO_PHY1_P3_BASE + 0xEF) 3543 #define REG_COMBO_PHY1_P3_78_L (REG_COMBO_PHY1_P3_BASE + 0xF0) 3544 #define REG_COMBO_PHY1_P3_78_H (REG_COMBO_PHY1_P3_BASE + 0xF1) 3545 #define REG_COMBO_PHY1_P3_79_L (REG_COMBO_PHY1_P3_BASE + 0xF2) 3546 #define REG_COMBO_PHY1_P3_79_H (REG_COMBO_PHY1_P3_BASE + 0xF3) 3547 #define REG_COMBO_PHY1_P3_7A_L (REG_COMBO_PHY1_P3_BASE + 0xF4) 3548 #define REG_COMBO_PHY1_P3_7A_H (REG_COMBO_PHY1_P3_BASE + 0xF5) 3549 #define REG_COMBO_PHY1_P3_7B_L (REG_COMBO_PHY1_P3_BASE + 0xF6) 3550 #define REG_COMBO_PHY1_P3_7B_H (REG_COMBO_PHY1_P3_BASE + 0xF7) 3551 #define REG_COMBO_PHY1_P3_7C_L (REG_COMBO_PHY1_P3_BASE + 0xF8) 3552 #define REG_COMBO_PHY1_P3_7C_H (REG_COMBO_PHY1_P3_BASE + 0xF9) 3553 #define REG_COMBO_PHY1_P3_7D_L (REG_COMBO_PHY1_P3_BASE + 0xFA) 3554 #define REG_COMBO_PHY1_P3_7D_H (REG_COMBO_PHY1_P3_BASE + 0xFB) 3555 #define REG_COMBO_PHY1_P3_7E_L (REG_COMBO_PHY1_P3_BASE + 0xFC) 3556 #define REG_COMBO_PHY1_P3_7E_H (REG_COMBO_PHY1_P3_BASE + 0xFD) 3557 #define REG_COMBO_PHY1_P3_7F_L (REG_COMBO_PHY1_P3_BASE + 0xFE) 3558 #define REG_COMBO_PHY1_P3_7F_H (REG_COMBO_PHY1_P3_BASE + 0xFF) 3559 3560 //============================================================= 3561 3562 // DVI_DTOP_DUAL_P0 3563 #define REG_DVI_DTOP_DUAL_P0_00_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x00) 3564 #define REG_DVI_DTOP_DUAL_P0_00_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x01) 3565 #define REG_DVI_DTOP_DUAL_P0_01_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x02) 3566 #define REG_DVI_DTOP_DUAL_P0_01_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x03) 3567 #define REG_DVI_DTOP_DUAL_P0_02_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x04) 3568 #define REG_DVI_DTOP_DUAL_P0_02_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x05) 3569 #define REG_DVI_DTOP_DUAL_P0_03_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x06) 3570 #define REG_DVI_DTOP_DUAL_P0_03_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x07) 3571 #define REG_DVI_DTOP_DUAL_P0_04_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x08) 3572 #define REG_DVI_DTOP_DUAL_P0_04_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x09) 3573 #define REG_DVI_DTOP_DUAL_P0_05_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x0A) 3574 #define REG_DVI_DTOP_DUAL_P0_05_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x0B) 3575 #define REG_DVI_DTOP_DUAL_P0_06_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x0C) 3576 #define REG_DVI_DTOP_DUAL_P0_06_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x0D) 3577 #define REG_DVI_DTOP_DUAL_P0_07_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x0E) 3578 #define REG_DVI_DTOP_DUAL_P0_07_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x0F) 3579 #define REG_DVI_DTOP_DUAL_P0_08_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x10) 3580 #define REG_DVI_DTOP_DUAL_P0_08_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x11) 3581 #define REG_DVI_DTOP_DUAL_P0_09_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x12) 3582 #define REG_DVI_DTOP_DUAL_P0_09_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x13) 3583 #define REG_DVI_DTOP_DUAL_P0_0A_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x14) 3584 #define REG_DVI_DTOP_DUAL_P0_0A_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x15) 3585 #define REG_DVI_DTOP_DUAL_P0_0B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x16) 3586 #define REG_DVI_DTOP_DUAL_P0_0B_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x17) 3587 #define REG_DVI_DTOP_DUAL_P0_0C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x18) 3588 #define REG_DVI_DTOP_DUAL_P0_0C_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x19) 3589 #define REG_DVI_DTOP_DUAL_P0_0D_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x1A) 3590 #define REG_DVI_DTOP_DUAL_P0_0D_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x1B) 3591 #define REG_DVI_DTOP_DUAL_P0_0E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x1C) 3592 #define REG_DVI_DTOP_DUAL_P0_0E_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x1D) 3593 #define REG_DVI_DTOP_DUAL_P0_0F_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x1E) 3594 #define REG_DVI_DTOP_DUAL_P0_0F_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x1F) 3595 #define REG_DVI_DTOP_DUAL_P0_10_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x20) 3596 #define REG_DVI_DTOP_DUAL_P0_10_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x21) 3597 #define REG_DVI_DTOP_DUAL_P0_11_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x22) 3598 #define REG_DVI_DTOP_DUAL_P0_11_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x23) 3599 #define REG_DVI_DTOP_DUAL_P0_12_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x24) 3600 #define REG_DVI_DTOP_DUAL_P0_12_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x25) 3601 #define REG_DVI_DTOP_DUAL_P0_13_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x26) 3602 #define REG_DVI_DTOP_DUAL_P0_13_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x27) 3603 #define REG_DVI_DTOP_DUAL_P0_14_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x28) 3604 #define REG_DVI_DTOP_DUAL_P0_14_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x29) 3605 #define REG_DVI_DTOP_DUAL_P0_15_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x2A) 3606 #define REG_DVI_DTOP_DUAL_P0_15_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x2B) 3607 #define REG_DVI_DTOP_DUAL_P0_16_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x2C) 3608 #define REG_DVI_DTOP_DUAL_P0_16_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x2D) 3609 #define REG_DVI_DTOP_DUAL_P0_17_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x2E) 3610 #define REG_DVI_DTOP_DUAL_P0_17_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x2F) 3611 #define REG_DVI_DTOP_DUAL_P0_18_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x30) 3612 #define REG_DVI_DTOP_DUAL_P0_18_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x31) 3613 #define REG_DVI_DTOP_DUAL_P0_19_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x32) 3614 #define REG_DVI_DTOP_DUAL_P0_19_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x33) 3615 #define REG_DVI_DTOP_DUAL_P0_1A_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x34) 3616 #define REG_DVI_DTOP_DUAL_P0_1A_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x35) 3617 #define REG_DVI_DTOP_DUAL_P0_1B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x36) 3618 #define REG_DVI_DTOP_DUAL_P0_1B_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x37) 3619 #define REG_DVI_DTOP_DUAL_P0_1C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x38) 3620 #define REG_DVI_DTOP_DUAL_P0_1C_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x39) 3621 #define REG_DVI_DTOP_DUAL_P0_1D_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x3A) 3622 #define REG_DVI_DTOP_DUAL_P0_1D_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x3B) 3623 #define REG_DVI_DTOP_DUAL_P0_1E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x3C) 3624 #define REG_DVI_DTOP_DUAL_P0_1E_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x3D) 3625 #define REG_DVI_DTOP_DUAL_P0_1F_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x3E) 3626 #define REG_DVI_DTOP_DUAL_P0_1F_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x3F) 3627 #define REG_DVI_DTOP_DUAL_P0_20_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x40) 3628 #define REG_DVI_DTOP_DUAL_P0_20_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x41) 3629 #define REG_DVI_DTOP_DUAL_P0_21_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x42) 3630 #define REG_DVI_DTOP_DUAL_P0_21_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x43) 3631 #define REG_DVI_DTOP_DUAL_P0_22_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x44) 3632 #define REG_DVI_DTOP_DUAL_P0_22_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x45) 3633 #define REG_DVI_DTOP_DUAL_P0_23_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x46) 3634 #define REG_DVI_DTOP_DUAL_P0_23_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x47) 3635 #define REG_DVI_DTOP_DUAL_P0_24_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x48) 3636 #define REG_DVI_DTOP_DUAL_P0_24_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x49) 3637 #define REG_DVI_DTOP_DUAL_P0_25_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x4A) 3638 #define REG_DVI_DTOP_DUAL_P0_25_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x4B) 3639 #define REG_DVI_DTOP_DUAL_P0_26_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x4C) 3640 #define REG_DVI_DTOP_DUAL_P0_26_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x4D) 3641 #define REG_DVI_DTOP_DUAL_P0_27_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x4E) 3642 #define REG_DVI_DTOP_DUAL_P0_27_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x4F) 3643 #define REG_DVI_DTOP_DUAL_P0_28_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x50) 3644 #define REG_DVI_DTOP_DUAL_P0_28_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x51) 3645 #define REG_DVI_DTOP_DUAL_P0_29_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x52) 3646 #define REG_DVI_DTOP_DUAL_P0_29_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x53) 3647 #define REG_DVI_DTOP_DUAL_P0_2A_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x54) 3648 #define REG_DVI_DTOP_DUAL_P0_2A_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x55) 3649 #define REG_DVI_DTOP_DUAL_P0_2B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x56) 3650 #define REG_DVI_DTOP_DUAL_P0_2B_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x57) 3651 #define REG_DVI_DTOP_DUAL_P0_2C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x58) 3652 #define REG_DVI_DTOP_DUAL_P0_2C_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x59) 3653 #define REG_DVI_DTOP_DUAL_P0_2D_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x5A) 3654 #define REG_DVI_DTOP_DUAL_P0_2D_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x5B) 3655 #define REG_DVI_DTOP_DUAL_P0_2E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x5C) 3656 #define REG_DVI_DTOP_DUAL_P0_2E_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x5D) 3657 #define REG_DVI_DTOP_DUAL_P0_2F_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x5E) 3658 #define REG_DVI_DTOP_DUAL_P0_2F_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x5F) 3659 #define REG_DVI_DTOP_DUAL_P0_30_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x60) 3660 #define REG_DVI_DTOP_DUAL_P0_30_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x61) 3661 #define REG_DVI_DTOP_DUAL_P0_31_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x62) 3662 #define REG_DVI_DTOP_DUAL_P0_31_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x63) 3663 #define REG_DVI_DTOP_DUAL_P0_32_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x64) 3664 #define REG_DVI_DTOP_DUAL_P0_32_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x65) 3665 #define REG_DVI_DTOP_DUAL_P0_33_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x66) 3666 #define REG_DVI_DTOP_DUAL_P0_33_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x67) 3667 #define REG_DVI_DTOP_DUAL_P0_34_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x68) 3668 #define REG_DVI_DTOP_DUAL_P0_34_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x69) 3669 #define REG_DVI_DTOP_DUAL_P0_35_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x6A) 3670 #define REG_DVI_DTOP_DUAL_P0_35_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x6B) 3671 #define REG_DVI_DTOP_DUAL_P0_36_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x6C) 3672 #define REG_DVI_DTOP_DUAL_P0_36_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x6D) 3673 #define REG_DVI_DTOP_DUAL_P0_37_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x6E) 3674 #define REG_DVI_DTOP_DUAL_P0_37_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x6F) 3675 #define REG_DVI_DTOP_DUAL_P0_38_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x70) 3676 #define REG_DVI_DTOP_DUAL_P0_38_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x71) 3677 #define REG_DVI_DTOP_DUAL_P0_39_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x72) 3678 #define REG_DVI_DTOP_DUAL_P0_39_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x73) 3679 #define REG_DVI_DTOP_DUAL_P0_3A_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x74) 3680 #define REG_DVI_DTOP_DUAL_P0_3A_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x75) 3681 #define REG_DVI_DTOP_DUAL_P0_3B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x76) 3682 #define REG_DVI_DTOP_DUAL_P0_3B_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x77) 3683 #define REG_DVI_DTOP_DUAL_P0_3C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x78) 3684 #define REG_DVI_DTOP_DUAL_P0_3C_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x79) 3685 #define REG_DVI_DTOP_DUAL_P0_3D_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x7A) 3686 #define REG_DVI_DTOP_DUAL_P0_3D_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x7B) 3687 #define REG_DVI_DTOP_DUAL_P0_3E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x7C) 3688 #define REG_DVI_DTOP_DUAL_P0_3E_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x7D) 3689 #define REG_DVI_DTOP_DUAL_P0_3F_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x7E) 3690 #define REG_DVI_DTOP_DUAL_P0_3F_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x7F) 3691 #define REG_DVI_DTOP_DUAL_P0_40_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x80) 3692 #define REG_DVI_DTOP_DUAL_P0_40_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x81) 3693 #define REG_DVI_DTOP_DUAL_P0_41_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x82) 3694 #define REG_DVI_DTOP_DUAL_P0_41_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x83) 3695 #define REG_DVI_DTOP_DUAL_P0_42_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x84) 3696 #define REG_DVI_DTOP_DUAL_P0_42_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x85) 3697 #define REG_DVI_DTOP_DUAL_P0_43_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x86) 3698 #define REG_DVI_DTOP_DUAL_P0_43_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x87) 3699 #define REG_DVI_DTOP_DUAL_P0_44_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x88) 3700 #define REG_DVI_DTOP_DUAL_P0_44_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x89) 3701 #define REG_DVI_DTOP_DUAL_P0_45_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x8A) 3702 #define REG_DVI_DTOP_DUAL_P0_45_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x8B) 3703 #define REG_DVI_DTOP_DUAL_P0_46_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x8C) 3704 #define REG_DVI_DTOP_DUAL_P0_46_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x8D) 3705 #define REG_DVI_DTOP_DUAL_P0_47_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x8E) 3706 #define REG_DVI_DTOP_DUAL_P0_47_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x8F) 3707 #define REG_DVI_DTOP_DUAL_P0_48_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x90) 3708 #define REG_DVI_DTOP_DUAL_P0_48_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x91) 3709 #define REG_DVI_DTOP_DUAL_P0_49_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x92) 3710 #define REG_DVI_DTOP_DUAL_P0_49_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x93) 3711 #define REG_DVI_DTOP_DUAL_P0_4A_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x94) 3712 #define REG_DVI_DTOP_DUAL_P0_4A_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x95) 3713 #define REG_DVI_DTOP_DUAL_P0_4B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x96) 3714 #define REG_DVI_DTOP_DUAL_P0_4B_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x97) 3715 #define REG_DVI_DTOP_DUAL_P0_4C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x98) 3716 #define REG_DVI_DTOP_DUAL_P0_4C_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x99) 3717 #define REG_DVI_DTOP_DUAL_P0_4D_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x9A) 3718 #define REG_DVI_DTOP_DUAL_P0_4D_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x9B) 3719 #define REG_DVI_DTOP_DUAL_P0_4E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x9C) 3720 #define REG_DVI_DTOP_DUAL_P0_4E_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x9D) 3721 #define REG_DVI_DTOP_DUAL_P0_4F_L (REG_DVI_DTOP_DUAL_P0_BASE + 0x9E) 3722 #define REG_DVI_DTOP_DUAL_P0_4F_H (REG_DVI_DTOP_DUAL_P0_BASE + 0x9F) 3723 #define REG_DVI_DTOP_DUAL_P0_50_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xA0) 3724 #define REG_DVI_DTOP_DUAL_P0_50_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xA1) 3725 #define REG_DVI_DTOP_DUAL_P0_51_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xA2) 3726 #define REG_DVI_DTOP_DUAL_P0_51_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xA3) 3727 #define REG_DVI_DTOP_DUAL_P0_52_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xA4) 3728 #define REG_DVI_DTOP_DUAL_P0_52_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xA5) 3729 #define REG_DVI_DTOP_DUAL_P0_53_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xA6) 3730 #define REG_DVI_DTOP_DUAL_P0_53_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xA7) 3731 #define REG_DVI_DTOP_DUAL_P0_54_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xA8) 3732 #define REG_DVI_DTOP_DUAL_P0_54_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xA9) 3733 #define REG_DVI_DTOP_DUAL_P0_55_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xAA) 3734 #define REG_DVI_DTOP_DUAL_P0_55_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xAB) 3735 #define REG_DVI_DTOP_DUAL_P0_56_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xAC) 3736 #define REG_DVI_DTOP_DUAL_P0_56_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xAD) 3737 #define REG_DVI_DTOP_DUAL_P0_57_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xAE) 3738 #define REG_DVI_DTOP_DUAL_P0_57_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xAF) 3739 #define REG_DVI_DTOP_DUAL_P0_58_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xB0) 3740 #define REG_DVI_DTOP_DUAL_P0_58_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xB1) 3741 #define REG_DVI_DTOP_DUAL_P0_59_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xB2) 3742 #define REG_DVI_DTOP_DUAL_P0_59_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xB3) 3743 #define REG_DVI_DTOP_DUAL_P0_5A_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xB4) 3744 #define REG_DVI_DTOP_DUAL_P0_5A_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xB5) 3745 #define REG_DVI_DTOP_DUAL_P0_5B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xB6) 3746 #define REG_DVI_DTOP_DUAL_P0_5B_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xB7) 3747 #define REG_DVI_DTOP_DUAL_P0_5C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xB8) 3748 #define REG_DVI_DTOP_DUAL_P0_5C_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xB9) 3749 #define REG_DVI_DTOP_DUAL_P0_5D_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xBA) 3750 #define REG_DVI_DTOP_DUAL_P0_5D_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xBB) 3751 #define REG_DVI_DTOP_DUAL_P0_5E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xBC) 3752 #define REG_DVI_DTOP_DUAL_P0_5E_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xBD) 3753 #define REG_DVI_DTOP_DUAL_P0_5F_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xBE) 3754 #define REG_DVI_DTOP_DUAL_P0_5F_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xBF) 3755 #define REG_DVI_DTOP_DUAL_P0_60_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xC0) 3756 #define REG_DVI_DTOP_DUAL_P0_60_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xC1) 3757 #define REG_DVI_DTOP_DUAL_P0_61_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xC2) 3758 #define REG_DVI_DTOP_DUAL_P0_61_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xC3) 3759 #define REG_DVI_DTOP_DUAL_P0_62_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xC4) 3760 #define REG_DVI_DTOP_DUAL_P0_62_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xC5) 3761 #define REG_DVI_DTOP_DUAL_P0_63_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xC6) 3762 #define REG_DVI_DTOP_DUAL_P0_63_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xC7) 3763 #define REG_DVI_DTOP_DUAL_P0_64_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xC8) 3764 #define REG_DVI_DTOP_DUAL_P0_64_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xC9) 3765 #define REG_DVI_DTOP_DUAL_P0_65_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xCA) 3766 #define REG_DVI_DTOP_DUAL_P0_65_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xCB) 3767 #define REG_DVI_DTOP_DUAL_P0_66_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xCC) 3768 #define REG_DVI_DTOP_DUAL_P0_66_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xCD) 3769 #define REG_DVI_DTOP_DUAL_P0_67_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xCE) 3770 #define REG_DVI_DTOP_DUAL_P0_67_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xCF) 3771 #define REG_DVI_DTOP_DUAL_P0_68_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xD0) 3772 #define REG_DVI_DTOP_DUAL_P0_68_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xD1) 3773 #define REG_DVI_DTOP_DUAL_P0_69_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xD2) 3774 #define REG_DVI_DTOP_DUAL_P0_69_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xD3) 3775 #define REG_DVI_DTOP_DUAL_P0_6A_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xD4) 3776 #define REG_DVI_DTOP_DUAL_P0_6A_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xD5) 3777 #define REG_DVI_DTOP_DUAL_P0_6B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xD6) 3778 #define REG_DVI_DTOP_DUAL_P0_6B_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xD7) 3779 #define REG_DVI_DTOP_DUAL_P0_6C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xD8) 3780 #define REG_DVI_DTOP_DUAL_P0_6C_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xD9) 3781 #define REG_DVI_DTOP_DUAL_P0_6D_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xDA) 3782 #define REG_DVI_DTOP_DUAL_P0_6D_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xDB) 3783 #define REG_DVI_DTOP_DUAL_P0_6E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xDC) 3784 #define REG_DVI_DTOP_DUAL_P0_6E_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xDD) 3785 #define REG_DVI_DTOP_DUAL_P0_6F_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xDE) 3786 #define REG_DVI_DTOP_DUAL_P0_6F_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xDF) 3787 #define REG_DVI_DTOP_DUAL_P0_70_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xE0) 3788 #define REG_DVI_DTOP_DUAL_P0_70_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xE1) 3789 #define REG_DVI_DTOP_DUAL_P0_71_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xE2) 3790 #define REG_DVI_DTOP_DUAL_P0_71_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xE3) 3791 #define REG_DVI_DTOP_DUAL_P0_72_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xE4) 3792 #define REG_DVI_DTOP_DUAL_P0_72_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xE5) 3793 #define REG_DVI_DTOP_DUAL_P0_73_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xE6) 3794 #define REG_DVI_DTOP_DUAL_P0_73_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xE7) 3795 #define REG_DVI_DTOP_DUAL_P0_74_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xE8) 3796 #define REG_DVI_DTOP_DUAL_P0_74_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xE9) 3797 #define REG_DVI_DTOP_DUAL_P0_75_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xEA) 3798 #define REG_DVI_DTOP_DUAL_P0_75_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xEB) 3799 #define REG_DVI_DTOP_DUAL_P0_76_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xEC) 3800 #define REG_DVI_DTOP_DUAL_P0_76_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xED) 3801 #define REG_DVI_DTOP_DUAL_P0_77_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xEE) 3802 #define REG_DVI_DTOP_DUAL_P0_77_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xEF) 3803 #define REG_DVI_DTOP_DUAL_P0_78_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xF0) 3804 #define REG_DVI_DTOP_DUAL_P0_78_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xF1) 3805 #define REG_DVI_DTOP_DUAL_P0_79_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xF2) 3806 #define REG_DVI_DTOP_DUAL_P0_79_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xF3) 3807 #define REG_DVI_DTOP_DUAL_P0_7A_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xF4) 3808 #define REG_DVI_DTOP_DUAL_P0_7A_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xF5) 3809 #define REG_DVI_DTOP_DUAL_P0_7B_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xF6) 3810 #define REG_DVI_DTOP_DUAL_P0_7B_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xF7) 3811 #define REG_DVI_DTOP_DUAL_P0_7C_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xF8) 3812 #define REG_DVI_DTOP_DUAL_P0_7C_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xF9) 3813 #define REG_DVI_DTOP_DUAL_P0_7D_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xFA) 3814 #define REG_DVI_DTOP_DUAL_P0_7D_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xFB) 3815 #define REG_DVI_DTOP_DUAL_P0_7E_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xFC) 3816 #define REG_DVI_DTOP_DUAL_P0_7E_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xFD) 3817 #define REG_DVI_DTOP_DUAL_P0_7F_L (REG_DVI_DTOP_DUAL_P0_BASE + 0xFE) 3818 #define REG_DVI_DTOP_DUAL_P0_7F_H (REG_DVI_DTOP_DUAL_P0_BASE + 0xFF) 3819 3820 // DVI_RSV_DUAL_P0 3821 #define REG_DVI_RSV_DUAL_P0_00_L (REG_DVI_RSV_DUAL_P0_BASE + 0x00) 3822 #define REG_DVI_RSV_DUAL_P0_00_H (REG_DVI_RSV_DUAL_P0_BASE + 0x01) 3823 #define REG_DVI_RSV_DUAL_P0_01_L (REG_DVI_RSV_DUAL_P0_BASE + 0x02) 3824 #define REG_DVI_RSV_DUAL_P0_01_H (REG_DVI_RSV_DUAL_P0_BASE + 0x03) 3825 #define REG_DVI_RSV_DUAL_P0_02_L (REG_DVI_RSV_DUAL_P0_BASE + 0x04) 3826 #define REG_DVI_RSV_DUAL_P0_02_H (REG_DVI_RSV_DUAL_P0_BASE + 0x05) 3827 #define REG_DVI_RSV_DUAL_P0_03_L (REG_DVI_RSV_DUAL_P0_BASE + 0x06) 3828 #define REG_DVI_RSV_DUAL_P0_03_H (REG_DVI_RSV_DUAL_P0_BASE + 0x07) 3829 #define REG_DVI_RSV_DUAL_P0_04_L (REG_DVI_RSV_DUAL_P0_BASE + 0x08) 3830 #define REG_DVI_RSV_DUAL_P0_04_H (REG_DVI_RSV_DUAL_P0_BASE + 0x09) 3831 #define REG_DVI_RSV_DUAL_P0_05_L (REG_DVI_RSV_DUAL_P0_BASE + 0x0A) 3832 #define REG_DVI_RSV_DUAL_P0_05_H (REG_DVI_RSV_DUAL_P0_BASE + 0x0B) 3833 #define REG_DVI_RSV_DUAL_P0_06_L (REG_DVI_RSV_DUAL_P0_BASE + 0x0C) 3834 #define REG_DVI_RSV_DUAL_P0_06_H (REG_DVI_RSV_DUAL_P0_BASE + 0x0D) 3835 #define REG_DVI_RSV_DUAL_P0_07_L (REG_DVI_RSV_DUAL_P0_BASE + 0x0E) 3836 #define REG_DVI_RSV_DUAL_P0_07_H (REG_DVI_RSV_DUAL_P0_BASE + 0x0F) 3837 #define REG_DVI_RSV_DUAL_P0_08_L (REG_DVI_RSV_DUAL_P0_BASE + 0x10) 3838 #define REG_DVI_RSV_DUAL_P0_08_H (REG_DVI_RSV_DUAL_P0_BASE + 0x11) 3839 #define REG_DVI_RSV_DUAL_P0_09_L (REG_DVI_RSV_DUAL_P0_BASE + 0x12) 3840 #define REG_DVI_RSV_DUAL_P0_09_H (REG_DVI_RSV_DUAL_P0_BASE + 0x13) 3841 #define REG_DVI_RSV_DUAL_P0_0A_L (REG_DVI_RSV_DUAL_P0_BASE + 0x14) 3842 #define REG_DVI_RSV_DUAL_P0_0A_H (REG_DVI_RSV_DUAL_P0_BASE + 0x15) 3843 #define REG_DVI_RSV_DUAL_P0_0B_L (REG_DVI_RSV_DUAL_P0_BASE + 0x16) 3844 #define REG_DVI_RSV_DUAL_P0_0B_H (REG_DVI_RSV_DUAL_P0_BASE + 0x17) 3845 #define REG_DVI_RSV_DUAL_P0_0C_L (REG_DVI_RSV_DUAL_P0_BASE + 0x18) 3846 #define REG_DVI_RSV_DUAL_P0_0C_H (REG_DVI_RSV_DUAL_P0_BASE + 0x19) 3847 #define REG_DVI_RSV_DUAL_P0_0D_L (REG_DVI_RSV_DUAL_P0_BASE + 0x1A) 3848 #define REG_DVI_RSV_DUAL_P0_0D_H (REG_DVI_RSV_DUAL_P0_BASE + 0x1B) 3849 #define REG_DVI_RSV_DUAL_P0_0E_L (REG_DVI_RSV_DUAL_P0_BASE + 0x1C) 3850 #define REG_DVI_RSV_DUAL_P0_0E_H (REG_DVI_RSV_DUAL_P0_BASE + 0x1D) 3851 #define REG_DVI_RSV_DUAL_P0_0F_L (REG_DVI_RSV_DUAL_P0_BASE + 0x1E) 3852 #define REG_DVI_RSV_DUAL_P0_0F_H (REG_DVI_RSV_DUAL_P0_BASE + 0x1F) 3853 #define REG_DVI_RSV_DUAL_P0_10_L (REG_DVI_RSV_DUAL_P0_BASE + 0x20) 3854 #define REG_DVI_RSV_DUAL_P0_10_H (REG_DVI_RSV_DUAL_P0_BASE + 0x21) 3855 #define REG_DVI_RSV_DUAL_P0_11_L (REG_DVI_RSV_DUAL_P0_BASE + 0x22) 3856 #define REG_DVI_RSV_DUAL_P0_11_H (REG_DVI_RSV_DUAL_P0_BASE + 0x23) 3857 #define REG_DVI_RSV_DUAL_P0_12_L (REG_DVI_RSV_DUAL_P0_BASE + 0x24) 3858 #define REG_DVI_RSV_DUAL_P0_12_H (REG_DVI_RSV_DUAL_P0_BASE + 0x25) 3859 #define REG_DVI_RSV_DUAL_P0_13_L (REG_DVI_RSV_DUAL_P0_BASE + 0x26) 3860 #define REG_DVI_RSV_DUAL_P0_13_H (REG_DVI_RSV_DUAL_P0_BASE + 0x27) 3861 #define REG_DVI_RSV_DUAL_P0_14_L (REG_DVI_RSV_DUAL_P0_BASE + 0x28) 3862 #define REG_DVI_RSV_DUAL_P0_14_H (REG_DVI_RSV_DUAL_P0_BASE + 0x29) 3863 #define REG_DVI_RSV_DUAL_P0_15_L (REG_DVI_RSV_DUAL_P0_BASE + 0x2A) 3864 #define REG_DVI_RSV_DUAL_P0_15_H (REG_DVI_RSV_DUAL_P0_BASE + 0x2B) 3865 #define REG_DVI_RSV_DUAL_P0_16_L (REG_DVI_RSV_DUAL_P0_BASE + 0x2C) 3866 #define REG_DVI_RSV_DUAL_P0_16_H (REG_DVI_RSV_DUAL_P0_BASE + 0x2D) 3867 #define REG_DVI_RSV_DUAL_P0_17_L (REG_DVI_RSV_DUAL_P0_BASE + 0x2E) 3868 #define REG_DVI_RSV_DUAL_P0_17_H (REG_DVI_RSV_DUAL_P0_BASE + 0x2F) 3869 #define REG_DVI_RSV_DUAL_P0_18_L (REG_DVI_RSV_DUAL_P0_BASE + 0x30) 3870 #define REG_DVI_RSV_DUAL_P0_18_H (REG_DVI_RSV_DUAL_P0_BASE + 0x31) 3871 #define REG_DVI_RSV_DUAL_P0_19_L (REG_DVI_RSV_DUAL_P0_BASE + 0x32) 3872 #define REG_DVI_RSV_DUAL_P0_19_H (REG_DVI_RSV_DUAL_P0_BASE + 0x33) 3873 #define REG_DVI_RSV_DUAL_P0_1A_L (REG_DVI_RSV_DUAL_P0_BASE + 0x34) 3874 #define REG_DVI_RSV_DUAL_P0_1A_H (REG_DVI_RSV_DUAL_P0_BASE + 0x35) 3875 #define REG_DVI_RSV_DUAL_P0_1B_L (REG_DVI_RSV_DUAL_P0_BASE + 0x36) 3876 #define REG_DVI_RSV_DUAL_P0_1B_H (REG_DVI_RSV_DUAL_P0_BASE + 0x37) 3877 #define REG_DVI_RSV_DUAL_P0_1C_L (REG_DVI_RSV_DUAL_P0_BASE + 0x38) 3878 #define REG_DVI_RSV_DUAL_P0_1C_H (REG_DVI_RSV_DUAL_P0_BASE + 0x39) 3879 #define REG_DVI_RSV_DUAL_P0_1D_L (REG_DVI_RSV_DUAL_P0_BASE + 0x3A) 3880 #define REG_DVI_RSV_DUAL_P0_1D_H (REG_DVI_RSV_DUAL_P0_BASE + 0x3B) 3881 #define REG_DVI_RSV_DUAL_P0_1E_L (REG_DVI_RSV_DUAL_P0_BASE + 0x3C) 3882 #define REG_DVI_RSV_DUAL_P0_1E_H (REG_DVI_RSV_DUAL_P0_BASE + 0x3D) 3883 #define REG_DVI_RSV_DUAL_P0_1F_L (REG_DVI_RSV_DUAL_P0_BASE + 0x3E) 3884 #define REG_DVI_RSV_DUAL_P0_1F_H (REG_DVI_RSV_DUAL_P0_BASE + 0x3F) 3885 3886 // HDCP_DUAL_P0 3887 #define REG_HDCP_DUAL_P0_00_L (REG_HDCP_DUAL_P0_BASE + 0x00) 3888 #define REG_HDCP_DUAL_P0_00_H (REG_HDCP_DUAL_P0_BASE + 0x01) 3889 #define REG_HDCP_DUAL_P0_01_L (REG_HDCP_DUAL_P0_BASE + 0x02) 3890 #define REG_HDCP_DUAL_P0_01_H (REG_HDCP_DUAL_P0_BASE + 0x03) 3891 #define REG_HDCP_DUAL_P0_02_L (REG_HDCP_DUAL_P0_BASE + 0x04) 3892 #define REG_HDCP_DUAL_P0_02_H (REG_HDCP_DUAL_P0_BASE + 0x05) 3893 #define REG_HDCP_DUAL_P0_03_L (REG_HDCP_DUAL_P0_BASE + 0x06) 3894 #define REG_HDCP_DUAL_P0_03_H (REG_HDCP_DUAL_P0_BASE + 0x07) 3895 #define REG_HDCP_DUAL_P0_04_L (REG_HDCP_DUAL_P0_BASE + 0x08) 3896 #define REG_HDCP_DUAL_P0_04_H (REG_HDCP_DUAL_P0_BASE + 0x09) 3897 #define REG_HDCP_DUAL_P0_05_L (REG_HDCP_DUAL_P0_BASE + 0x0A) 3898 #define REG_HDCP_DUAL_P0_05_H (REG_HDCP_DUAL_P0_BASE + 0x0B) 3899 #define REG_HDCP_DUAL_P0_06_L (REG_HDCP_DUAL_P0_BASE + 0x0C) 3900 #define REG_HDCP_DUAL_P0_06_H (REG_HDCP_DUAL_P0_BASE + 0x0D) 3901 #define REG_HDCP_DUAL_P0_07_L (REG_HDCP_DUAL_P0_BASE + 0x0E) 3902 #define REG_HDCP_DUAL_P0_07_H (REG_HDCP_DUAL_P0_BASE + 0x0F) 3903 #define REG_HDCP_DUAL_P0_08_L (REG_HDCP_DUAL_P0_BASE + 0x10) 3904 #define REG_HDCP_DUAL_P0_08_H (REG_HDCP_DUAL_P0_BASE + 0x11) 3905 #define REG_HDCP_DUAL_P0_09_L (REG_HDCP_DUAL_P0_BASE + 0x12) 3906 #define REG_HDCP_DUAL_P0_09_H (REG_HDCP_DUAL_P0_BASE + 0x13) 3907 #define REG_HDCP_DUAL_P0_0A_L (REG_HDCP_DUAL_P0_BASE + 0x14) 3908 #define REG_HDCP_DUAL_P0_0A_H (REG_HDCP_DUAL_P0_BASE + 0x15) 3909 #define REG_HDCP_DUAL_P0_0B_L (REG_HDCP_DUAL_P0_BASE + 0x16) 3910 #define REG_HDCP_DUAL_P0_0B_H (REG_HDCP_DUAL_P0_BASE + 0x17) 3911 #define REG_HDCP_DUAL_P0_0C_L (REG_HDCP_DUAL_P0_BASE + 0x18) 3912 #define REG_HDCP_DUAL_P0_0C_H (REG_HDCP_DUAL_P0_BASE + 0x19) 3913 #define REG_HDCP_DUAL_P0_0D_L (REG_HDCP_DUAL_P0_BASE + 0x1A) 3914 #define REG_HDCP_DUAL_P0_0D_H (REG_HDCP_DUAL_P0_BASE + 0x1B) 3915 #define REG_HDCP_DUAL_P0_0E_L (REG_HDCP_DUAL_P0_BASE + 0x1C) 3916 #define REG_HDCP_DUAL_P0_0E_H (REG_HDCP_DUAL_P0_BASE + 0x1D) 3917 #define REG_HDCP_DUAL_P0_0F_L (REG_HDCP_DUAL_P0_BASE + 0x1E) 3918 #define REG_HDCP_DUAL_P0_0F_H (REG_HDCP_DUAL_P0_BASE + 0x1F) 3919 #define REG_HDCP_DUAL_P0_10_L (REG_HDCP_DUAL_P0_BASE + 0x20) 3920 #define REG_HDCP_DUAL_P0_10_H (REG_HDCP_DUAL_P0_BASE + 0x21) 3921 #define REG_HDCP_DUAL_P0_11_L (REG_HDCP_DUAL_P0_BASE + 0x22) 3922 #define REG_HDCP_DUAL_P0_11_H (REG_HDCP_DUAL_P0_BASE + 0x23) 3923 #define REG_HDCP_DUAL_P0_12_L (REG_HDCP_DUAL_P0_BASE + 0x24) 3924 #define REG_HDCP_DUAL_P0_12_H (REG_HDCP_DUAL_P0_BASE + 0x25) 3925 #define REG_HDCP_DUAL_P0_13_L (REG_HDCP_DUAL_P0_BASE + 0x26) 3926 #define REG_HDCP_DUAL_P0_13_H (REG_HDCP_DUAL_P0_BASE + 0x27) 3927 #define REG_HDCP_DUAL_P0_14_L (REG_HDCP_DUAL_P0_BASE + 0x28) 3928 #define REG_HDCP_DUAL_P0_14_H (REG_HDCP_DUAL_P0_BASE + 0x29) 3929 #define REG_HDCP_DUAL_P0_15_L (REG_HDCP_DUAL_P0_BASE + 0x2A) 3930 #define REG_HDCP_DUAL_P0_15_H (REG_HDCP_DUAL_P0_BASE + 0x2B) 3931 #define REG_HDCP_DUAL_P0_16_L (REG_HDCP_DUAL_P0_BASE + 0x2C) 3932 #define REG_HDCP_DUAL_P0_16_H (REG_HDCP_DUAL_P0_BASE + 0x2D) 3933 #define REG_HDCP_DUAL_P0_17_L (REG_HDCP_DUAL_P0_BASE + 0x2E) 3934 #define REG_HDCP_DUAL_P0_17_H (REG_HDCP_DUAL_P0_BASE + 0x2F) 3935 #define REG_HDCP_DUAL_P0_18_L (REG_HDCP_DUAL_P0_BASE + 0x30) 3936 #define REG_HDCP_DUAL_P0_18_H (REG_HDCP_DUAL_P0_BASE + 0x31) 3937 #define REG_HDCP_DUAL_P0_19_L (REG_HDCP_DUAL_P0_BASE + 0x32) 3938 #define REG_HDCP_DUAL_P0_19_H (REG_HDCP_DUAL_P0_BASE + 0x33) 3939 #define REG_HDCP_DUAL_P0_1A_L (REG_HDCP_DUAL_P0_BASE + 0x34) 3940 #define REG_HDCP_DUAL_P0_1A_H (REG_HDCP_DUAL_P0_BASE + 0x35) 3941 #define REG_HDCP_DUAL_P0_1B_L (REG_HDCP_DUAL_P0_BASE + 0x36) 3942 #define REG_HDCP_DUAL_P0_1B_H (REG_HDCP_DUAL_P0_BASE + 0x37) 3943 #define REG_HDCP_DUAL_P0_1C_L (REG_HDCP_DUAL_P0_BASE + 0x38) 3944 #define REG_HDCP_DUAL_P0_1C_H (REG_HDCP_DUAL_P0_BASE + 0x39) 3945 #define REG_HDCP_DUAL_P0_1D_L (REG_HDCP_DUAL_P0_BASE + 0x3A) 3946 #define REG_HDCP_DUAL_P0_1D_H (REG_HDCP_DUAL_P0_BASE + 0x3B) 3947 #define REG_HDCP_DUAL_P0_1E_L (REG_HDCP_DUAL_P0_BASE + 0x3C) 3948 #define REG_HDCP_DUAL_P0_1E_H (REG_HDCP_DUAL_P0_BASE + 0x3D) 3949 #define REG_HDCP_DUAL_P0_1F_L (REG_HDCP_DUAL_P0_BASE + 0x3E) 3950 #define REG_HDCP_DUAL_P0_1F_H (REG_HDCP_DUAL_P0_BASE + 0x3F) 3951 #define REG_HDCP_DUAL_P0_20_L (REG_HDCP_DUAL_P0_BASE + 0x40) 3952 #define REG_HDCP_DUAL_P0_20_H (REG_HDCP_DUAL_P0_BASE + 0x41) 3953 #define REG_HDCP_DUAL_P0_21_L (REG_HDCP_DUAL_P0_BASE + 0x42) 3954 #define REG_HDCP_DUAL_P0_21_H (REG_HDCP_DUAL_P0_BASE + 0x43) 3955 #define REG_HDCP_DUAL_P0_22_L (REG_HDCP_DUAL_P0_BASE + 0x44) 3956 #define REG_HDCP_DUAL_P0_22_H (REG_HDCP_DUAL_P0_BASE + 0x45) 3957 #define REG_HDCP_DUAL_P0_23_L (REG_HDCP_DUAL_P0_BASE + 0x46) 3958 #define REG_HDCP_DUAL_P0_23_H (REG_HDCP_DUAL_P0_BASE + 0x47) 3959 #define REG_HDCP_DUAL_P0_24_L (REG_HDCP_DUAL_P0_BASE + 0x48) 3960 #define REG_HDCP_DUAL_P0_24_H (REG_HDCP_DUAL_P0_BASE + 0x49) 3961 #define REG_HDCP_DUAL_P0_25_L (REG_HDCP_DUAL_P0_BASE + 0x4A) 3962 #define REG_HDCP_DUAL_P0_25_H (REG_HDCP_DUAL_P0_BASE + 0x4B) 3963 #define REG_HDCP_DUAL_P0_26_L (REG_HDCP_DUAL_P0_BASE + 0x4C) 3964 #define REG_HDCP_DUAL_P0_26_H (REG_HDCP_DUAL_P0_BASE + 0x4D) 3965 #define REG_HDCP_DUAL_P0_27_L (REG_HDCP_DUAL_P0_BASE + 0x4E) 3966 #define REG_HDCP_DUAL_P0_27_H (REG_HDCP_DUAL_P0_BASE + 0x4F) 3967 #define REG_HDCP_DUAL_P0_28_L (REG_HDCP_DUAL_P0_BASE + 0x50) 3968 #define REG_HDCP_DUAL_P0_28_H (REG_HDCP_DUAL_P0_BASE + 0x51) 3969 #define REG_HDCP_DUAL_P0_29_L (REG_HDCP_DUAL_P0_BASE + 0x52) 3970 #define REG_HDCP_DUAL_P0_29_H (REG_HDCP_DUAL_P0_BASE + 0x53) 3971 #define REG_HDCP_DUAL_P0_2A_L (REG_HDCP_DUAL_P0_BASE + 0x54) 3972 #define REG_HDCP_DUAL_P0_2A_H (REG_HDCP_DUAL_P0_BASE + 0x55) 3973 #define REG_HDCP_DUAL_P0_2B_L (REG_HDCP_DUAL_P0_BASE + 0x56) 3974 #define REG_HDCP_DUAL_P0_2B_H (REG_HDCP_DUAL_P0_BASE + 0x57) 3975 #define REG_HDCP_DUAL_P0_2C_L (REG_HDCP_DUAL_P0_BASE + 0x58) 3976 #define REG_HDCP_DUAL_P0_2C_H (REG_HDCP_DUAL_P0_BASE + 0x59) 3977 #define REG_HDCP_DUAL_P0_2D_L (REG_HDCP_DUAL_P0_BASE + 0x5A) 3978 #define REG_HDCP_DUAL_P0_2D_H (REG_HDCP_DUAL_P0_BASE + 0x5B) 3979 #define REG_HDCP_DUAL_P0_2E_L (REG_HDCP_DUAL_P0_BASE + 0x5C) 3980 #define REG_HDCP_DUAL_P0_2E_H (REG_HDCP_DUAL_P0_BASE + 0x5D) 3981 #define REG_HDCP_DUAL_P0_2F_L (REG_HDCP_DUAL_P0_BASE + 0x5E) 3982 #define REG_HDCP_DUAL_P0_2F_H (REG_HDCP_DUAL_P0_BASE + 0x5F) 3983 #define REG_HDCP_DUAL_P0_30_L (REG_HDCP_DUAL_P0_BASE + 0x60) 3984 #define REG_HDCP_DUAL_P0_30_H (REG_HDCP_DUAL_P0_BASE + 0x61) 3985 #define REG_HDCP_DUAL_P0_31_L (REG_HDCP_DUAL_P0_BASE + 0x62) 3986 #define REG_HDCP_DUAL_P0_31_H (REG_HDCP_DUAL_P0_BASE + 0x63) 3987 #define REG_HDCP_DUAL_P0_32_L (REG_HDCP_DUAL_P0_BASE + 0x64) 3988 #define REG_HDCP_DUAL_P0_32_H (REG_HDCP_DUAL_P0_BASE + 0x65) 3989 #define REG_HDCP_DUAL_P0_33_L (REG_HDCP_DUAL_P0_BASE + 0x66) 3990 #define REG_HDCP_DUAL_P0_33_H (REG_HDCP_DUAL_P0_BASE + 0x67) 3991 #define REG_HDCP_DUAL_P0_34_L (REG_HDCP_DUAL_P0_BASE + 0x68) 3992 #define REG_HDCP_DUAL_P0_34_H (REG_HDCP_DUAL_P0_BASE + 0x69) 3993 #define REG_HDCP_DUAL_P0_35_L (REG_HDCP_DUAL_P0_BASE + 0x6A) 3994 #define REG_HDCP_DUAL_P0_35_H (REG_HDCP_DUAL_P0_BASE + 0x6B) 3995 #define REG_HDCP_DUAL_P0_36_L (REG_HDCP_DUAL_P0_BASE + 0x6C) 3996 #define REG_HDCP_DUAL_P0_36_H (REG_HDCP_DUAL_P0_BASE + 0x6D) 3997 #define REG_HDCP_DUAL_P0_37_L (REG_HDCP_DUAL_P0_BASE + 0x6E) 3998 #define REG_HDCP_DUAL_P0_37_H (REG_HDCP_DUAL_P0_BASE + 0x6F) 3999 #define REG_HDCP_DUAL_P0_38_L (REG_HDCP_DUAL_P0_BASE + 0x70) 4000 #define REG_HDCP_DUAL_P0_38_H (REG_HDCP_DUAL_P0_BASE + 0x71) 4001 #define REG_HDCP_DUAL_P0_39_L (REG_HDCP_DUAL_P0_BASE + 0x72) 4002 #define REG_HDCP_DUAL_P0_39_H (REG_HDCP_DUAL_P0_BASE + 0x73) 4003 #define REG_HDCP_DUAL_P0_3A_L (REG_HDCP_DUAL_P0_BASE + 0x74) 4004 #define REG_HDCP_DUAL_P0_3A_H (REG_HDCP_DUAL_P0_BASE + 0x75) 4005 #define REG_HDCP_DUAL_P0_3B_L (REG_HDCP_DUAL_P0_BASE + 0x76) 4006 #define REG_HDCP_DUAL_P0_3B_H (REG_HDCP_DUAL_P0_BASE + 0x77) 4007 #define REG_HDCP_DUAL_P0_3C_L (REG_HDCP_DUAL_P0_BASE + 0x78) 4008 #define REG_HDCP_DUAL_P0_3C_H (REG_HDCP_DUAL_P0_BASE + 0x79) 4009 #define REG_HDCP_DUAL_P0_3D_L (REG_HDCP_DUAL_P0_BASE + 0x7A) 4010 #define REG_HDCP_DUAL_P0_3D_H (REG_HDCP_DUAL_P0_BASE + 0x7B) 4011 #define REG_HDCP_DUAL_P0_3E_L (REG_HDCP_DUAL_P0_BASE + 0x7C) 4012 #define REG_HDCP_DUAL_P0_3E_H (REG_HDCP_DUAL_P0_BASE + 0x7D) 4013 #define REG_HDCP_DUAL_P0_3F_L (REG_HDCP_DUAL_P0_BASE + 0x7E) 4014 #define REG_HDCP_DUAL_P0_3F_H (REG_HDCP_DUAL_P0_BASE + 0x7F) 4015 #define REG_HDCP_DUAL_P0_40_L (REG_HDCP_DUAL_P0_BASE + 0x80) 4016 #define REG_HDCP_DUAL_P0_40_H (REG_HDCP_DUAL_P0_BASE + 0x81) 4017 #define REG_HDCP_DUAL_P0_41_L (REG_HDCP_DUAL_P0_BASE + 0x82) 4018 #define REG_HDCP_DUAL_P0_41_H (REG_HDCP_DUAL_P0_BASE + 0x83) 4019 #define REG_HDCP_DUAL_P0_42_L (REG_HDCP_DUAL_P0_BASE + 0x84) 4020 #define REG_HDCP_DUAL_P0_42_H (REG_HDCP_DUAL_P0_BASE + 0x85) 4021 #define REG_HDCP_DUAL_P0_43_L (REG_HDCP_DUAL_P0_BASE + 0x86) 4022 #define REG_HDCP_DUAL_P0_43_H (REG_HDCP_DUAL_P0_BASE + 0x87) 4023 #define REG_HDCP_DUAL_P0_44_L (REG_HDCP_DUAL_P0_BASE + 0x88) 4024 #define REG_HDCP_DUAL_P0_44_H (REG_HDCP_DUAL_P0_BASE + 0x89) 4025 #define REG_HDCP_DUAL_P0_45_L (REG_HDCP_DUAL_P0_BASE + 0x8A) 4026 #define REG_HDCP_DUAL_P0_45_H (REG_HDCP_DUAL_P0_BASE + 0x8B) 4027 #define REG_HDCP_DUAL_P0_46_L (REG_HDCP_DUAL_P0_BASE + 0x8C) 4028 #define REG_HDCP_DUAL_P0_46_H (REG_HDCP_DUAL_P0_BASE + 0x8D) 4029 #define REG_HDCP_DUAL_P0_47_L (REG_HDCP_DUAL_P0_BASE + 0x8E) 4030 #define REG_HDCP_DUAL_P0_47_H (REG_HDCP_DUAL_P0_BASE + 0x8F) 4031 #define REG_HDCP_DUAL_P0_48_L (REG_HDCP_DUAL_P0_BASE + 0x90) 4032 #define REG_HDCP_DUAL_P0_48_H (REG_HDCP_DUAL_P0_BASE + 0x91) 4033 #define REG_HDCP_DUAL_P0_49_L (REG_HDCP_DUAL_P0_BASE + 0x92) 4034 #define REG_HDCP_DUAL_P0_49_H (REG_HDCP_DUAL_P0_BASE + 0x93) 4035 #define REG_HDCP_DUAL_P0_4A_L (REG_HDCP_DUAL_P0_BASE + 0x94) 4036 #define REG_HDCP_DUAL_P0_4A_H (REG_HDCP_DUAL_P0_BASE + 0x95) 4037 #define REG_HDCP_DUAL_P0_4B_L (REG_HDCP_DUAL_P0_BASE + 0x96) 4038 #define REG_HDCP_DUAL_P0_4B_H (REG_HDCP_DUAL_P0_BASE + 0x97) 4039 #define REG_HDCP_DUAL_P0_4C_L (REG_HDCP_DUAL_P0_BASE + 0x98) 4040 #define REG_HDCP_DUAL_P0_4C_H (REG_HDCP_DUAL_P0_BASE + 0x99) 4041 #define REG_HDCP_DUAL_P0_4D_L (REG_HDCP_DUAL_P0_BASE + 0x9A) 4042 #define REG_HDCP_DUAL_P0_4D_H (REG_HDCP_DUAL_P0_BASE + 0x9B) 4043 #define REG_HDCP_DUAL_P0_4E_L (REG_HDCP_DUAL_P0_BASE + 0x9C) 4044 #define REG_HDCP_DUAL_P0_4E_H (REG_HDCP_DUAL_P0_BASE + 0x9D) 4045 #define REG_HDCP_DUAL_P0_4F_L (REG_HDCP_DUAL_P0_BASE + 0x9E) 4046 #define REG_HDCP_DUAL_P0_4F_H (REG_HDCP_DUAL_P0_BASE + 0x9F) 4047 #define REG_HDCP_DUAL_P0_50_L (REG_HDCP_DUAL_P0_BASE + 0xA0) 4048 #define REG_HDCP_DUAL_P0_50_H (REG_HDCP_DUAL_P0_BASE + 0xA1) 4049 #define REG_HDCP_DUAL_P0_51_L (REG_HDCP_DUAL_P0_BASE + 0xA2) 4050 #define REG_HDCP_DUAL_P0_51_H (REG_HDCP_DUAL_P0_BASE + 0xA3) 4051 #define REG_HDCP_DUAL_P0_52_L (REG_HDCP_DUAL_P0_BASE + 0xA4) 4052 #define REG_HDCP_DUAL_P0_52_H (REG_HDCP_DUAL_P0_BASE + 0xA5) 4053 #define REG_HDCP_DUAL_P0_53_L (REG_HDCP_DUAL_P0_BASE + 0xA6) 4054 #define REG_HDCP_DUAL_P0_53_H (REG_HDCP_DUAL_P0_BASE + 0xA7) 4055 #define REG_HDCP_DUAL_P0_54_L (REG_HDCP_DUAL_P0_BASE + 0xA8) 4056 #define REG_HDCP_DUAL_P0_54_H (REG_HDCP_DUAL_P0_BASE + 0xA9) 4057 #define REG_HDCP_DUAL_P0_55_L (REG_HDCP_DUAL_P0_BASE + 0xAA) 4058 #define REG_HDCP_DUAL_P0_55_H (REG_HDCP_DUAL_P0_BASE + 0xAB) 4059 #define REG_HDCP_DUAL_P0_56_L (REG_HDCP_DUAL_P0_BASE + 0xAC) 4060 #define REG_HDCP_DUAL_P0_56_H (REG_HDCP_DUAL_P0_BASE + 0xAD) 4061 #define REG_HDCP_DUAL_P0_57_L (REG_HDCP_DUAL_P0_BASE + 0xAE) 4062 #define REG_HDCP_DUAL_P0_57_H (REG_HDCP_DUAL_P0_BASE + 0xAF) 4063 #define REG_HDCP_DUAL_P0_58_L (REG_HDCP_DUAL_P0_BASE + 0xB0) 4064 #define REG_HDCP_DUAL_P0_58_H (REG_HDCP_DUAL_P0_BASE + 0xB1) 4065 #define REG_HDCP_DUAL_P0_59_L (REG_HDCP_DUAL_P0_BASE + 0xB2) 4066 #define REG_HDCP_DUAL_P0_59_H (REG_HDCP_DUAL_P0_BASE + 0xB3) 4067 #define REG_HDCP_DUAL_P0_5A_L (REG_HDCP_DUAL_P0_BASE + 0xB4) 4068 #define REG_HDCP_DUAL_P0_5A_H (REG_HDCP_DUAL_P0_BASE + 0xB5) 4069 #define REG_HDCP_DUAL_P0_5B_L (REG_HDCP_DUAL_P0_BASE + 0xB6) 4070 #define REG_HDCP_DUAL_P0_5B_H (REG_HDCP_DUAL_P0_BASE + 0xB7) 4071 #define REG_HDCP_DUAL_P0_5C_L (REG_HDCP_DUAL_P0_BASE + 0xB8) 4072 #define REG_HDCP_DUAL_P0_5C_H (REG_HDCP_DUAL_P0_BASE + 0xB9) 4073 #define REG_HDCP_DUAL_P0_5D_L (REG_HDCP_DUAL_P0_BASE + 0xBA) 4074 #define REG_HDCP_DUAL_P0_5D_H (REG_HDCP_DUAL_P0_BASE + 0xBB) 4075 #define REG_HDCP_DUAL_P0_5E_L (REG_HDCP_DUAL_P0_BASE + 0xBC) 4076 #define REG_HDCP_DUAL_P0_5E_H (REG_HDCP_DUAL_P0_BASE + 0xBD) 4077 #define REG_HDCP_DUAL_P0_5F_L (REG_HDCP_DUAL_P0_BASE + 0xBE) 4078 #define REG_HDCP_DUAL_P0_5F_H (REG_HDCP_DUAL_P0_BASE + 0xBF) 4079 #define REG_HDCP_DUAL_P0_60_L (REG_HDCP_DUAL_P0_BASE + 0xC0) 4080 #define REG_HDCP_DUAL_P0_60_H (REG_HDCP_DUAL_P0_BASE + 0xC1) 4081 #define REG_HDCP_DUAL_P0_61_L (REG_HDCP_DUAL_P0_BASE + 0xC2) 4082 #define REG_HDCP_DUAL_P0_61_H (REG_HDCP_DUAL_P0_BASE + 0xC3) 4083 #define REG_HDCP_DUAL_P0_62_L (REG_HDCP_DUAL_P0_BASE + 0xC4) 4084 #define REG_HDCP_DUAL_P0_62_H (REG_HDCP_DUAL_P0_BASE + 0xC5) 4085 #define REG_HDCP_DUAL_P0_63_L (REG_HDCP_DUAL_P0_BASE + 0xC6) 4086 #define REG_HDCP_DUAL_P0_63_H (REG_HDCP_DUAL_P0_BASE + 0xC7) 4087 #define REG_HDCP_DUAL_P0_64_L (REG_HDCP_DUAL_P0_BASE + 0xC8) 4088 #define REG_HDCP_DUAL_P0_64_H (REG_HDCP_DUAL_P0_BASE + 0xC9) 4089 #define REG_HDCP_DUAL_P0_65_L (REG_HDCP_DUAL_P0_BASE + 0xCA) 4090 #define REG_HDCP_DUAL_P0_65_H (REG_HDCP_DUAL_P0_BASE + 0xCB) 4091 #define REG_HDCP_DUAL_P0_66_L (REG_HDCP_DUAL_P0_BASE + 0xCC) 4092 #define REG_HDCP_DUAL_P0_66_H (REG_HDCP_DUAL_P0_BASE + 0xCD) 4093 #define REG_HDCP_DUAL_P0_67_L (REG_HDCP_DUAL_P0_BASE + 0xCE) 4094 #define REG_HDCP_DUAL_P0_67_H (REG_HDCP_DUAL_P0_BASE + 0xCF) 4095 #define REG_HDCP_DUAL_P0_68_L (REG_HDCP_DUAL_P0_BASE + 0xD0) 4096 #define REG_HDCP_DUAL_P0_68_H (REG_HDCP_DUAL_P0_BASE + 0xD1) 4097 4098 // DVI_DTOP_DUAL_P1 4099 #define REG_DVI_DTOP_DUAL_P1_00_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x00) 4100 #define REG_DVI_DTOP_DUAL_P1_00_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x01) 4101 #define REG_DVI_DTOP_DUAL_P1_01_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x02) 4102 #define REG_DVI_DTOP_DUAL_P1_01_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x03) 4103 #define REG_DVI_DTOP_DUAL_P1_02_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x04) 4104 #define REG_DVI_DTOP_DUAL_P1_02_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x05) 4105 #define REG_DVI_DTOP_DUAL_P1_03_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x06) 4106 #define REG_DVI_DTOP_DUAL_P1_03_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x07) 4107 #define REG_DVI_DTOP_DUAL_P1_04_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x08) 4108 #define REG_DVI_DTOP_DUAL_P1_04_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x09) 4109 #define REG_DVI_DTOP_DUAL_P1_05_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x0A) 4110 #define REG_DVI_DTOP_DUAL_P1_05_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x0B) 4111 #define REG_DVI_DTOP_DUAL_P1_06_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x0C) 4112 #define REG_DVI_DTOP_DUAL_P1_06_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x0D) 4113 #define REG_DVI_DTOP_DUAL_P1_07_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x0E) 4114 #define REG_DVI_DTOP_DUAL_P1_07_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x0F) 4115 #define REG_DVI_DTOP_DUAL_P1_08_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x10) 4116 #define REG_DVI_DTOP_DUAL_P1_08_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x11) 4117 #define REG_DVI_DTOP_DUAL_P1_09_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x12) 4118 #define REG_DVI_DTOP_DUAL_P1_09_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x13) 4119 #define REG_DVI_DTOP_DUAL_P1_0A_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x14) 4120 #define REG_DVI_DTOP_DUAL_P1_0A_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x15) 4121 #define REG_DVI_DTOP_DUAL_P1_0B_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x16) 4122 #define REG_DVI_DTOP_DUAL_P1_0B_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x17) 4123 #define REG_DVI_DTOP_DUAL_P1_0C_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x18) 4124 #define REG_DVI_DTOP_DUAL_P1_0C_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x19) 4125 #define REG_DVI_DTOP_DUAL_P1_0D_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x1A) 4126 #define REG_DVI_DTOP_DUAL_P1_0D_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x1B) 4127 #define REG_DVI_DTOP_DUAL_P1_0E_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x1C) 4128 #define REG_DVI_DTOP_DUAL_P1_0E_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x1D) 4129 #define REG_DVI_DTOP_DUAL_P1_0F_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x1E) 4130 #define REG_DVI_DTOP_DUAL_P1_0F_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x1F) 4131 #define REG_DVI_DTOP_DUAL_P1_10_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x20) 4132 #define REG_DVI_DTOP_DUAL_P1_10_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x21) 4133 #define REG_DVI_DTOP_DUAL_P1_11_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x22) 4134 #define REG_DVI_DTOP_DUAL_P1_11_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x23) 4135 #define REG_DVI_DTOP_DUAL_P1_12_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x24) 4136 #define REG_DVI_DTOP_DUAL_P1_12_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x25) 4137 #define REG_DVI_DTOP_DUAL_P1_13_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x26) 4138 #define REG_DVI_DTOP_DUAL_P1_13_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x27) 4139 #define REG_DVI_DTOP_DUAL_P1_14_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x28) 4140 #define REG_DVI_DTOP_DUAL_P1_14_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x29) 4141 #define REG_DVI_DTOP_DUAL_P1_15_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x2A) 4142 #define REG_DVI_DTOP_DUAL_P1_15_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x2B) 4143 #define REG_DVI_DTOP_DUAL_P1_16_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x2C) 4144 #define REG_DVI_DTOP_DUAL_P1_16_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x2D) 4145 #define REG_DVI_DTOP_DUAL_P1_17_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x2E) 4146 #define REG_DVI_DTOP_DUAL_P1_17_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x2F) 4147 #define REG_DVI_DTOP_DUAL_P1_18_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x30) 4148 #define REG_DVI_DTOP_DUAL_P1_18_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x31) 4149 #define REG_DVI_DTOP_DUAL_P1_19_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x32) 4150 #define REG_DVI_DTOP_DUAL_P1_19_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x33) 4151 #define REG_DVI_DTOP_DUAL_P1_1A_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x34) 4152 #define REG_DVI_DTOP_DUAL_P1_1A_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x35) 4153 #define REG_DVI_DTOP_DUAL_P1_1B_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x36) 4154 #define REG_DVI_DTOP_DUAL_P1_1B_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x37) 4155 #define REG_DVI_DTOP_DUAL_P1_1C_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x38) 4156 #define REG_DVI_DTOP_DUAL_P1_1C_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x39) 4157 #define REG_DVI_DTOP_DUAL_P1_1D_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x3A) 4158 #define REG_DVI_DTOP_DUAL_P1_1D_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x3B) 4159 #define REG_DVI_DTOP_DUAL_P1_1E_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x3C) 4160 #define REG_DVI_DTOP_DUAL_P1_1E_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x3D) 4161 #define REG_DVI_DTOP_DUAL_P1_1F_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x3E) 4162 #define REG_DVI_DTOP_DUAL_P1_1F_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x3F) 4163 #define REG_DVI_DTOP_DUAL_P1_20_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x40) 4164 #define REG_DVI_DTOP_DUAL_P1_20_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x41) 4165 #define REG_DVI_DTOP_DUAL_P1_21_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x42) 4166 #define REG_DVI_DTOP_DUAL_P1_21_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x43) 4167 #define REG_DVI_DTOP_DUAL_P1_22_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x44) 4168 #define REG_DVI_DTOP_DUAL_P1_22_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x45) 4169 #define REG_DVI_DTOP_DUAL_P1_23_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x46) 4170 #define REG_DVI_DTOP_DUAL_P1_23_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x47) 4171 #define REG_DVI_DTOP_DUAL_P1_24_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x48) 4172 #define REG_DVI_DTOP_DUAL_P1_24_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x49) 4173 #define REG_DVI_DTOP_DUAL_P1_25_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x4A) 4174 #define REG_DVI_DTOP_DUAL_P1_25_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x4B) 4175 #define REG_DVI_DTOP_DUAL_P1_26_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x4C) 4176 #define REG_DVI_DTOP_DUAL_P1_26_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x4D) 4177 #define REG_DVI_DTOP_DUAL_P1_27_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x4E) 4178 #define REG_DVI_DTOP_DUAL_P1_27_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x4F) 4179 #define REG_DVI_DTOP_DUAL_P1_28_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x50) 4180 #define REG_DVI_DTOP_DUAL_P1_28_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x51) 4181 #define REG_DVI_DTOP_DUAL_P1_29_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x52) 4182 #define REG_DVI_DTOP_DUAL_P1_29_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x53) 4183 #define REG_DVI_DTOP_DUAL_P1_2A_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x54) 4184 #define REG_DVI_DTOP_DUAL_P1_2A_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x55) 4185 #define REG_DVI_DTOP_DUAL_P1_2B_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x56) 4186 #define REG_DVI_DTOP_DUAL_P1_2B_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x57) 4187 #define REG_DVI_DTOP_DUAL_P1_2C_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x58) 4188 #define REG_DVI_DTOP_DUAL_P1_2C_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x59) 4189 #define REG_DVI_DTOP_DUAL_P1_2D_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x5A) 4190 #define REG_DVI_DTOP_DUAL_P1_2D_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x5B) 4191 #define REG_DVI_DTOP_DUAL_P1_2E_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x5C) 4192 #define REG_DVI_DTOP_DUAL_P1_2E_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x5D) 4193 #define REG_DVI_DTOP_DUAL_P1_2F_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x5E) 4194 #define REG_DVI_DTOP_DUAL_P1_2F_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x5F) 4195 #define REG_DVI_DTOP_DUAL_P1_30_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x60) 4196 #define REG_DVI_DTOP_DUAL_P1_30_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x61) 4197 #define REG_DVI_DTOP_DUAL_P1_31_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x62) 4198 #define REG_DVI_DTOP_DUAL_P1_31_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x63) 4199 #define REG_DVI_DTOP_DUAL_P1_32_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x64) 4200 #define REG_DVI_DTOP_DUAL_P1_32_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x65) 4201 #define REG_DVI_DTOP_DUAL_P1_33_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x66) 4202 #define REG_DVI_DTOP_DUAL_P1_33_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x67) 4203 #define REG_DVI_DTOP_DUAL_P1_34_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x68) 4204 #define REG_DVI_DTOP_DUAL_P1_34_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x69) 4205 #define REG_DVI_DTOP_DUAL_P1_35_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x6A) 4206 #define REG_DVI_DTOP_DUAL_P1_35_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x6B) 4207 #define REG_DVI_DTOP_DUAL_P1_36_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x6C) 4208 #define REG_DVI_DTOP_DUAL_P1_36_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x6D) 4209 #define REG_DVI_DTOP_DUAL_P1_37_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x6E) 4210 #define REG_DVI_DTOP_DUAL_P1_37_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x6F) 4211 #define REG_DVI_DTOP_DUAL_P1_38_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x70) 4212 #define REG_DVI_DTOP_DUAL_P1_38_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x71) 4213 #define REG_DVI_DTOP_DUAL_P1_39_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x72) 4214 #define REG_DVI_DTOP_DUAL_P1_39_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x73) 4215 #define REG_DVI_DTOP_DUAL_P1_3A_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x74) 4216 #define REG_DVI_DTOP_DUAL_P1_3A_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x75) 4217 #define REG_DVI_DTOP_DUAL_P1_3B_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x76) 4218 #define REG_DVI_DTOP_DUAL_P1_3B_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x77) 4219 #define REG_DVI_DTOP_DUAL_P1_3C_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x78) 4220 #define REG_DVI_DTOP_DUAL_P1_3C_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x79) 4221 #define REG_DVI_DTOP_DUAL_P1_3D_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x7A) 4222 #define REG_DVI_DTOP_DUAL_P1_3D_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x7B) 4223 #define REG_DVI_DTOP_DUAL_P1_3E_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x7C) 4224 #define REG_DVI_DTOP_DUAL_P1_3E_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x7D) 4225 #define REG_DVI_DTOP_DUAL_P1_3F_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x7E) 4226 #define REG_DVI_DTOP_DUAL_P1_3F_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x7F) 4227 #define REG_DVI_DTOP_DUAL_P1_40_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x80) 4228 #define REG_DVI_DTOP_DUAL_P1_40_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x81) 4229 #define REG_DVI_DTOP_DUAL_P1_41_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x82) 4230 #define REG_DVI_DTOP_DUAL_P1_41_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x83) 4231 #define REG_DVI_DTOP_DUAL_P1_42_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x84) 4232 #define REG_DVI_DTOP_DUAL_P1_42_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x85) 4233 #define REG_DVI_DTOP_DUAL_P1_43_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x86) 4234 #define REG_DVI_DTOP_DUAL_P1_43_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x87) 4235 #define REG_DVI_DTOP_DUAL_P1_44_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x88) 4236 #define REG_DVI_DTOP_DUAL_P1_44_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x89) 4237 #define REG_DVI_DTOP_DUAL_P1_45_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x8A) 4238 #define REG_DVI_DTOP_DUAL_P1_45_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x8B) 4239 #define REG_DVI_DTOP_DUAL_P1_46_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x8C) 4240 #define REG_DVI_DTOP_DUAL_P1_46_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x8D) 4241 #define REG_DVI_DTOP_DUAL_P1_47_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x8E) 4242 #define REG_DVI_DTOP_DUAL_P1_47_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x8F) 4243 #define REG_DVI_DTOP_DUAL_P1_48_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x90) 4244 #define REG_DVI_DTOP_DUAL_P1_48_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x91) 4245 #define REG_DVI_DTOP_DUAL_P1_49_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x92) 4246 #define REG_DVI_DTOP_DUAL_P1_49_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x93) 4247 #define REG_DVI_DTOP_DUAL_P1_4A_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x94) 4248 #define REG_DVI_DTOP_DUAL_P1_4A_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x95) 4249 #define REG_DVI_DTOP_DUAL_P1_4B_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x96) 4250 #define REG_DVI_DTOP_DUAL_P1_4B_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x97) 4251 #define REG_DVI_DTOP_DUAL_P1_4C_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x98) 4252 #define REG_DVI_DTOP_DUAL_P1_4C_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x99) 4253 #define REG_DVI_DTOP_DUAL_P1_4D_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x9A) 4254 #define REG_DVI_DTOP_DUAL_P1_4D_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x9B) 4255 #define REG_DVI_DTOP_DUAL_P1_4E_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x9C) 4256 #define REG_DVI_DTOP_DUAL_P1_4E_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x9D) 4257 #define REG_DVI_DTOP_DUAL_P1_4F_L (REG_DVI_DTOP_DUAL_P1_BASE + 0x9E) 4258 #define REG_DVI_DTOP_DUAL_P1_4F_H (REG_DVI_DTOP_DUAL_P1_BASE + 0x9F) 4259 #define REG_DVI_DTOP_DUAL_P1_50_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xA0) 4260 #define REG_DVI_DTOP_DUAL_P1_50_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xA1) 4261 #define REG_DVI_DTOP_DUAL_P1_51_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xA2) 4262 #define REG_DVI_DTOP_DUAL_P1_51_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xA3) 4263 #define REG_DVI_DTOP_DUAL_P1_52_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xA4) 4264 #define REG_DVI_DTOP_DUAL_P1_52_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xA5) 4265 #define REG_DVI_DTOP_DUAL_P1_53_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xA6) 4266 #define REG_DVI_DTOP_DUAL_P1_53_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xA7) 4267 #define REG_DVI_DTOP_DUAL_P1_54_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xA8) 4268 #define REG_DVI_DTOP_DUAL_P1_54_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xA9) 4269 #define REG_DVI_DTOP_DUAL_P1_55_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xAA) 4270 #define REG_DVI_DTOP_DUAL_P1_55_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xAB) 4271 #define REG_DVI_DTOP_DUAL_P1_56_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xAC) 4272 #define REG_DVI_DTOP_DUAL_P1_56_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xAD) 4273 #define REG_DVI_DTOP_DUAL_P1_57_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xAE) 4274 #define REG_DVI_DTOP_DUAL_P1_57_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xAF) 4275 #define REG_DVI_DTOP_DUAL_P1_58_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xB0) 4276 #define REG_DVI_DTOP_DUAL_P1_58_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xB1) 4277 #define REG_DVI_DTOP_DUAL_P1_59_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xB2) 4278 #define REG_DVI_DTOP_DUAL_P1_59_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xB3) 4279 #define REG_DVI_DTOP_DUAL_P1_5A_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xB4) 4280 #define REG_DVI_DTOP_DUAL_P1_5A_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xB5) 4281 #define REG_DVI_DTOP_DUAL_P1_5B_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xB6) 4282 #define REG_DVI_DTOP_DUAL_P1_5B_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xB7) 4283 #define REG_DVI_DTOP_DUAL_P1_5C_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xB8) 4284 #define REG_DVI_DTOP_DUAL_P1_5C_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xB9) 4285 #define REG_DVI_DTOP_DUAL_P1_5D_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xBA) 4286 #define REG_DVI_DTOP_DUAL_P1_5D_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xBB) 4287 #define REG_DVI_DTOP_DUAL_P1_5E_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xBC) 4288 #define REG_DVI_DTOP_DUAL_P1_5E_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xBD) 4289 #define REG_DVI_DTOP_DUAL_P1_5F_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xBE) 4290 #define REG_DVI_DTOP_DUAL_P1_5F_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xBF) 4291 #define REG_DVI_DTOP_DUAL_P1_60_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC0) 4292 #define REG_DVI_DTOP_DUAL_P1_60_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xC1) 4293 #define REG_DVI_DTOP_DUAL_P1_61_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC2) 4294 #define REG_DVI_DTOP_DUAL_P1_61_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xC3) 4295 #define REG_DVI_DTOP_DUAL_P1_62_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC4) 4296 #define REG_DVI_DTOP_DUAL_P1_62_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xC5) 4297 #define REG_DVI_DTOP_DUAL_P1_63_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC6) 4298 #define REG_DVI_DTOP_DUAL_P1_63_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xC7) 4299 #define REG_DVI_DTOP_DUAL_P1_64_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xC8) 4300 #define REG_DVI_DTOP_DUAL_P1_64_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xC9) 4301 #define REG_DVI_DTOP_DUAL_P1_65_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xCA) 4302 #define REG_DVI_DTOP_DUAL_P1_65_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xCB) 4303 #define REG_DVI_DTOP_DUAL_P1_66_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xCC) 4304 #define REG_DVI_DTOP_DUAL_P1_66_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xCD) 4305 #define REG_DVI_DTOP_DUAL_P1_67_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xCE) 4306 #define REG_DVI_DTOP_DUAL_P1_67_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xCF) 4307 #define REG_DVI_DTOP_DUAL_P1_68_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xD0) 4308 #define REG_DVI_DTOP_DUAL_P1_68_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xD1) 4309 #define REG_DVI_DTOP_DUAL_P1_69_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xD2) 4310 #define REG_DVI_DTOP_DUAL_P1_69_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xD3) 4311 #define REG_DVI_DTOP_DUAL_P1_6A_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xD4) 4312 #define REG_DVI_DTOP_DUAL_P1_6A_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xD5) 4313 #define REG_DVI_DTOP_DUAL_P1_6B_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xD6) 4314 #define REG_DVI_DTOP_DUAL_P1_6B_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xD7) 4315 #define REG_DVI_DTOP_DUAL_P1_6C_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xD8) 4316 #define REG_DVI_DTOP_DUAL_P1_6C_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xD9) 4317 #define REG_DVI_DTOP_DUAL_P1_6D_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xDA) 4318 #define REG_DVI_DTOP_DUAL_P1_6D_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xDB) 4319 #define REG_DVI_DTOP_DUAL_P1_6E_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xDC) 4320 #define REG_DVI_DTOP_DUAL_P1_6E_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xDD) 4321 #define REG_DVI_DTOP_DUAL_P1_6F_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xDE) 4322 #define REG_DVI_DTOP_DUAL_P1_6F_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xDF) 4323 #define REG_DVI_DTOP_DUAL_P1_70_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xE0) 4324 #define REG_DVI_DTOP_DUAL_P1_70_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xE1) 4325 #define REG_DVI_DTOP_DUAL_P1_71_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xE2) 4326 #define REG_DVI_DTOP_DUAL_P1_71_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xE3) 4327 #define REG_DVI_DTOP_DUAL_P1_72_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xE4) 4328 #define REG_DVI_DTOP_DUAL_P1_72_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xE5) 4329 #define REG_DVI_DTOP_DUAL_P1_73_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xE6) 4330 #define REG_DVI_DTOP_DUAL_P1_73_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xE7) 4331 #define REG_DVI_DTOP_DUAL_P1_74_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xE8) 4332 #define REG_DVI_DTOP_DUAL_P1_74_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xE9) 4333 #define REG_DVI_DTOP_DUAL_P1_75_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xEA) 4334 #define REG_DVI_DTOP_DUAL_P1_75_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xEB) 4335 #define REG_DVI_DTOP_DUAL_P1_76_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xEC) 4336 #define REG_DVI_DTOP_DUAL_P1_76_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xED) 4337 #define REG_DVI_DTOP_DUAL_P1_77_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xEE) 4338 #define REG_DVI_DTOP_DUAL_P1_77_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xEF) 4339 #define REG_DVI_DTOP_DUAL_P1_78_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xF0) 4340 #define REG_DVI_DTOP_DUAL_P1_78_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xF1) 4341 #define REG_DVI_DTOP_DUAL_P1_79_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xF2) 4342 #define REG_DVI_DTOP_DUAL_P1_79_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xF3) 4343 #define REG_DVI_DTOP_DUAL_P1_7A_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xF4) 4344 #define REG_DVI_DTOP_DUAL_P1_7A_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xF5) 4345 #define REG_DVI_DTOP_DUAL_P1_7B_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xF6) 4346 #define REG_DVI_DTOP_DUAL_P1_7B_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xF7) 4347 #define REG_DVI_DTOP_DUAL_P1_7C_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xF8) 4348 #define REG_DVI_DTOP_DUAL_P1_7C_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xF9) 4349 #define REG_DVI_DTOP_DUAL_P1_7D_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xFA) 4350 #define REG_DVI_DTOP_DUAL_P1_7D_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xFB) 4351 #define REG_DVI_DTOP_DUAL_P1_7E_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xFC) 4352 #define REG_DVI_DTOP_DUAL_P1_7E_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xFD) 4353 #define REG_DVI_DTOP_DUAL_P1_7F_L (REG_DVI_DTOP_DUAL_P1_BASE + 0xFE) 4354 #define REG_DVI_DTOP_DUAL_P1_7F_H (REG_DVI_DTOP_DUAL_P1_BASE + 0xFF) 4355 4356 // DVI_RSV_DUAL_P1 4357 #define REG_DVI_RSV_DUAL_P1_00_L (REG_DVI_RSV_DUAL_P1_BASE + 0x00) 4358 #define REG_DVI_RSV_DUAL_P1_00_H (REG_DVI_RSV_DUAL_P1_BASE + 0x01) 4359 #define REG_DVI_RSV_DUAL_P1_01_L (REG_DVI_RSV_DUAL_P1_BASE + 0x02) 4360 #define REG_DVI_RSV_DUAL_P1_01_H (REG_DVI_RSV_DUAL_P1_BASE + 0x03) 4361 #define REG_DVI_RSV_DUAL_P1_02_L (REG_DVI_RSV_DUAL_P1_BASE + 0x04) 4362 #define REG_DVI_RSV_DUAL_P1_02_H (REG_DVI_RSV_DUAL_P1_BASE + 0x05) 4363 #define REG_DVI_RSV_DUAL_P1_03_L (REG_DVI_RSV_DUAL_P1_BASE + 0x06) 4364 #define REG_DVI_RSV_DUAL_P1_03_H (REG_DVI_RSV_DUAL_P1_BASE + 0x07) 4365 #define REG_DVI_RSV_DUAL_P1_04_L (REG_DVI_RSV_DUAL_P1_BASE + 0x08) 4366 #define REG_DVI_RSV_DUAL_P1_04_H (REG_DVI_RSV_DUAL_P1_BASE + 0x09) 4367 #define REG_DVI_RSV_DUAL_P1_05_L (REG_DVI_RSV_DUAL_P1_BASE + 0x0A) 4368 #define REG_DVI_RSV_DUAL_P1_05_H (REG_DVI_RSV_DUAL_P1_BASE + 0x0B) 4369 #define REG_DVI_RSV_DUAL_P1_06_L (REG_DVI_RSV_DUAL_P1_BASE + 0x0C) 4370 #define REG_DVI_RSV_DUAL_P1_06_H (REG_DVI_RSV_DUAL_P1_BASE + 0x0D) 4371 #define REG_DVI_RSV_DUAL_P1_07_L (REG_DVI_RSV_DUAL_P1_BASE + 0x0E) 4372 #define REG_DVI_RSV_DUAL_P1_07_H (REG_DVI_RSV_DUAL_P1_BASE + 0x0F) 4373 #define REG_DVI_RSV_DUAL_P1_08_L (REG_DVI_RSV_DUAL_P1_BASE + 0x10) 4374 #define REG_DVI_RSV_DUAL_P1_08_H (REG_DVI_RSV_DUAL_P1_BASE + 0x11) 4375 #define REG_DVI_RSV_DUAL_P1_09_L (REG_DVI_RSV_DUAL_P1_BASE + 0x12) 4376 #define REG_DVI_RSV_DUAL_P1_09_H (REG_DVI_RSV_DUAL_P1_BASE + 0x13) 4377 #define REG_DVI_RSV_DUAL_P1_0A_L (REG_DVI_RSV_DUAL_P1_BASE + 0x14) 4378 #define REG_DVI_RSV_DUAL_P1_0A_H (REG_DVI_RSV_DUAL_P1_BASE + 0x15) 4379 #define REG_DVI_RSV_DUAL_P1_0B_L (REG_DVI_RSV_DUAL_P1_BASE + 0x16) 4380 #define REG_DVI_RSV_DUAL_P1_0B_H (REG_DVI_RSV_DUAL_P1_BASE + 0x17) 4381 #define REG_DVI_RSV_DUAL_P1_0C_L (REG_DVI_RSV_DUAL_P1_BASE + 0x18) 4382 #define REG_DVI_RSV_DUAL_P1_0C_H (REG_DVI_RSV_DUAL_P1_BASE + 0x19) 4383 #define REG_DVI_RSV_DUAL_P1_0D_L (REG_DVI_RSV_DUAL_P1_BASE + 0x1A) 4384 #define REG_DVI_RSV_DUAL_P1_0D_H (REG_DVI_RSV_DUAL_P1_BASE + 0x1B) 4385 #define REG_DVI_RSV_DUAL_P1_0E_L (REG_DVI_RSV_DUAL_P1_BASE + 0x1C) 4386 #define REG_DVI_RSV_DUAL_P1_0E_H (REG_DVI_RSV_DUAL_P1_BASE + 0x1D) 4387 #define REG_DVI_RSV_DUAL_P1_0F_L (REG_DVI_RSV_DUAL_P1_BASE + 0x1E) 4388 #define REG_DVI_RSV_DUAL_P1_0F_H (REG_DVI_RSV_DUAL_P1_BASE + 0x1F) 4389 #define REG_DVI_RSV_DUAL_P1_10_L (REG_DVI_RSV_DUAL_P1_BASE + 0x20) 4390 #define REG_DVI_RSV_DUAL_P1_10_H (REG_DVI_RSV_DUAL_P1_BASE + 0x21) 4391 #define REG_DVI_RSV_DUAL_P1_11_L (REG_DVI_RSV_DUAL_P1_BASE + 0x22) 4392 #define REG_DVI_RSV_DUAL_P1_11_H (REG_DVI_RSV_DUAL_P1_BASE + 0x23) 4393 #define REG_DVI_RSV_DUAL_P1_12_L (REG_DVI_RSV_DUAL_P1_BASE + 0x24) 4394 #define REG_DVI_RSV_DUAL_P1_12_H (REG_DVI_RSV_DUAL_P1_BASE + 0x25) 4395 #define REG_DVI_RSV_DUAL_P1_13_L (REG_DVI_RSV_DUAL_P1_BASE + 0x26) 4396 #define REG_DVI_RSV_DUAL_P1_13_H (REG_DVI_RSV_DUAL_P1_BASE + 0x27) 4397 #define REG_DVI_RSV_DUAL_P1_14_L (REG_DVI_RSV_DUAL_P1_BASE + 0x28) 4398 #define REG_DVI_RSV_DUAL_P1_14_H (REG_DVI_RSV_DUAL_P1_BASE + 0x29) 4399 #define REG_DVI_RSV_DUAL_P1_15_L (REG_DVI_RSV_DUAL_P1_BASE + 0x2A) 4400 #define REG_DVI_RSV_DUAL_P1_15_H (REG_DVI_RSV_DUAL_P1_BASE + 0x2B) 4401 #define REG_DVI_RSV_DUAL_P1_16_L (REG_DVI_RSV_DUAL_P1_BASE + 0x2C) 4402 #define REG_DVI_RSV_DUAL_P1_16_H (REG_DVI_RSV_DUAL_P1_BASE + 0x2D) 4403 #define REG_DVI_RSV_DUAL_P1_17_L (REG_DVI_RSV_DUAL_P1_BASE + 0x2E) 4404 #define REG_DVI_RSV_DUAL_P1_17_H (REG_DVI_RSV_DUAL_P1_BASE + 0x2F) 4405 #define REG_DVI_RSV_DUAL_P1_18_L (REG_DVI_RSV_DUAL_P1_BASE + 0x30) 4406 #define REG_DVI_RSV_DUAL_P1_18_H (REG_DVI_RSV_DUAL_P1_BASE + 0x31) 4407 #define REG_DVI_RSV_DUAL_P1_19_L (REG_DVI_RSV_DUAL_P1_BASE + 0x32) 4408 #define REG_DVI_RSV_DUAL_P1_19_H (REG_DVI_RSV_DUAL_P1_BASE + 0x33) 4409 #define REG_DVI_RSV_DUAL_P1_1A_L (REG_DVI_RSV_DUAL_P1_BASE + 0x34) 4410 #define REG_DVI_RSV_DUAL_P1_1A_H (REG_DVI_RSV_DUAL_P1_BASE + 0x35) 4411 #define REG_DVI_RSV_DUAL_P1_1B_L (REG_DVI_RSV_DUAL_P1_BASE + 0x36) 4412 #define REG_DVI_RSV_DUAL_P1_1B_H (REG_DVI_RSV_DUAL_P1_BASE + 0x37) 4413 #define REG_DVI_RSV_DUAL_P1_1C_L (REG_DVI_RSV_DUAL_P1_BASE + 0x38) 4414 #define REG_DVI_RSV_DUAL_P1_1C_H (REG_DVI_RSV_DUAL_P1_BASE + 0x39) 4415 #define REG_DVI_RSV_DUAL_P1_1D_L (REG_DVI_RSV_DUAL_P1_BASE + 0x3A) 4416 #define REG_DVI_RSV_DUAL_P1_1D_H (REG_DVI_RSV_DUAL_P1_BASE + 0x3B) 4417 #define REG_DVI_RSV_DUAL_P1_1E_L (REG_DVI_RSV_DUAL_P1_BASE + 0x3C) 4418 #define REG_DVI_RSV_DUAL_P1_1E_H (REG_DVI_RSV_DUAL_P1_BASE + 0x3D) 4419 #define REG_DVI_RSV_DUAL_P1_1F_L (REG_DVI_RSV_DUAL_P1_BASE + 0x3E) 4420 #define REG_DVI_RSV_DUAL_P1_1F_H (REG_DVI_RSV_DUAL_P1_BASE + 0x3F) 4421 4422 // HDCP_DUAL_P1 4423 #define REG_HDCP_DUAL_P1_00_L (REG_HDCP_DUAL_P1_BASE + 0x00) 4424 #define REG_HDCP_DUAL_P1_00_H (REG_HDCP_DUAL_P1_BASE + 0x01) 4425 #define REG_HDCP_DUAL_P1_01_L (REG_HDCP_DUAL_P1_BASE + 0x02) 4426 #define REG_HDCP_DUAL_P1_01_H (REG_HDCP_DUAL_P1_BASE + 0x03) 4427 #define REG_HDCP_DUAL_P1_02_L (REG_HDCP_DUAL_P1_BASE + 0x04) 4428 #define REG_HDCP_DUAL_P1_02_H (REG_HDCP_DUAL_P1_BASE + 0x05) 4429 #define REG_HDCP_DUAL_P1_03_L (REG_HDCP_DUAL_P1_BASE + 0x06) 4430 #define REG_HDCP_DUAL_P1_03_H (REG_HDCP_DUAL_P1_BASE + 0x07) 4431 #define REG_HDCP_DUAL_P1_04_L (REG_HDCP_DUAL_P1_BASE + 0x08) 4432 #define REG_HDCP_DUAL_P1_04_H (REG_HDCP_DUAL_P1_BASE + 0x09) 4433 #define REG_HDCP_DUAL_P1_05_L (REG_HDCP_DUAL_P1_BASE + 0x0A) 4434 #define REG_HDCP_DUAL_P1_05_H (REG_HDCP_DUAL_P1_BASE + 0x0B) 4435 #define REG_HDCP_DUAL_P1_06_L (REG_HDCP_DUAL_P1_BASE + 0x0C) 4436 #define REG_HDCP_DUAL_P1_06_H (REG_HDCP_DUAL_P1_BASE + 0x0D) 4437 #define REG_HDCP_DUAL_P1_07_L (REG_HDCP_DUAL_P1_BASE + 0x0E) 4438 #define REG_HDCP_DUAL_P1_07_H (REG_HDCP_DUAL_P1_BASE + 0x0F) 4439 #define REG_HDCP_DUAL_P1_08_L (REG_HDCP_DUAL_P1_BASE + 0x10) 4440 #define REG_HDCP_DUAL_P1_08_H (REG_HDCP_DUAL_P1_BASE + 0x11) 4441 #define REG_HDCP_DUAL_P1_09_L (REG_HDCP_DUAL_P1_BASE + 0x12) 4442 #define REG_HDCP_DUAL_P1_09_H (REG_HDCP_DUAL_P1_BASE + 0x13) 4443 #define REG_HDCP_DUAL_P1_0A_L (REG_HDCP_DUAL_P1_BASE + 0x14) 4444 #define REG_HDCP_DUAL_P1_0A_H (REG_HDCP_DUAL_P1_BASE + 0x15) 4445 #define REG_HDCP_DUAL_P1_0B_L (REG_HDCP_DUAL_P1_BASE + 0x16) 4446 #define REG_HDCP_DUAL_P1_0B_H (REG_HDCP_DUAL_P1_BASE + 0x17) 4447 #define REG_HDCP_DUAL_P1_0C_L (REG_HDCP_DUAL_P1_BASE + 0x18) 4448 #define REG_HDCP_DUAL_P1_0C_H (REG_HDCP_DUAL_P1_BASE + 0x19) 4449 #define REG_HDCP_DUAL_P1_0D_L (REG_HDCP_DUAL_P1_BASE + 0x1A) 4450 #define REG_HDCP_DUAL_P1_0D_H (REG_HDCP_DUAL_P1_BASE + 0x1B) 4451 #define REG_HDCP_DUAL_P1_0E_L (REG_HDCP_DUAL_P1_BASE + 0x1C) 4452 #define REG_HDCP_DUAL_P1_0E_H (REG_HDCP_DUAL_P1_BASE + 0x1D) 4453 #define REG_HDCP_DUAL_P1_0F_L (REG_HDCP_DUAL_P1_BASE + 0x1E) 4454 #define REG_HDCP_DUAL_P1_0F_H (REG_HDCP_DUAL_P1_BASE + 0x1F) 4455 #define REG_HDCP_DUAL_P1_10_L (REG_HDCP_DUAL_P1_BASE + 0x20) 4456 #define REG_HDCP_DUAL_P1_10_H (REG_HDCP_DUAL_P1_BASE + 0x21) 4457 #define REG_HDCP_DUAL_P1_11_L (REG_HDCP_DUAL_P1_BASE + 0x22) 4458 #define REG_HDCP_DUAL_P1_11_H (REG_HDCP_DUAL_P1_BASE + 0x23) 4459 #define REG_HDCP_DUAL_P1_12_L (REG_HDCP_DUAL_P1_BASE + 0x24) 4460 #define REG_HDCP_DUAL_P1_12_H (REG_HDCP_DUAL_P1_BASE + 0x25) 4461 #define REG_HDCP_DUAL_P1_13_L (REG_HDCP_DUAL_P1_BASE + 0x26) 4462 #define REG_HDCP_DUAL_P1_13_H (REG_HDCP_DUAL_P1_BASE + 0x27) 4463 #define REG_HDCP_DUAL_P1_14_L (REG_HDCP_DUAL_P1_BASE + 0x28) 4464 #define REG_HDCP_DUAL_P1_14_H (REG_HDCP_DUAL_P1_BASE + 0x29) 4465 #define REG_HDCP_DUAL_P1_15_L (REG_HDCP_DUAL_P1_BASE + 0x2A) 4466 #define REG_HDCP_DUAL_P1_15_H (REG_HDCP_DUAL_P1_BASE + 0x2B) 4467 #define REG_HDCP_DUAL_P1_16_L (REG_HDCP_DUAL_P1_BASE + 0x2C) 4468 #define REG_HDCP_DUAL_P1_16_H (REG_HDCP_DUAL_P1_BASE + 0x2D) 4469 #define REG_HDCP_DUAL_P1_17_L (REG_HDCP_DUAL_P1_BASE + 0x2E) 4470 #define REG_HDCP_DUAL_P1_17_H (REG_HDCP_DUAL_P1_BASE + 0x2F) 4471 #define REG_HDCP_DUAL_P1_18_L (REG_HDCP_DUAL_P1_BASE + 0x30) 4472 #define REG_HDCP_DUAL_P1_18_H (REG_HDCP_DUAL_P1_BASE + 0x31) 4473 #define REG_HDCP_DUAL_P1_19_L (REG_HDCP_DUAL_P1_BASE + 0x32) 4474 #define REG_HDCP_DUAL_P1_19_H (REG_HDCP_DUAL_P1_BASE + 0x33) 4475 #define REG_HDCP_DUAL_P1_1A_L (REG_HDCP_DUAL_P1_BASE + 0x34) 4476 #define REG_HDCP_DUAL_P1_1A_H (REG_HDCP_DUAL_P1_BASE + 0x35) 4477 #define REG_HDCP_DUAL_P1_1B_L (REG_HDCP_DUAL_P1_BASE + 0x36) 4478 #define REG_HDCP_DUAL_P1_1B_H (REG_HDCP_DUAL_P1_BASE + 0x37) 4479 #define REG_HDCP_DUAL_P1_1C_L (REG_HDCP_DUAL_P1_BASE + 0x38) 4480 #define REG_HDCP_DUAL_P1_1C_H (REG_HDCP_DUAL_P1_BASE + 0x39) 4481 #define REG_HDCP_DUAL_P1_1D_L (REG_HDCP_DUAL_P1_BASE + 0x3A) 4482 #define REG_HDCP_DUAL_P1_1D_H (REG_HDCP_DUAL_P1_BASE + 0x3B) 4483 #define REG_HDCP_DUAL_P1_1E_L (REG_HDCP_DUAL_P1_BASE + 0x3C) 4484 #define REG_HDCP_DUAL_P1_1E_H (REG_HDCP_DUAL_P1_BASE + 0x3D) 4485 #define REG_HDCP_DUAL_P1_1F_L (REG_HDCP_DUAL_P1_BASE + 0x3E) 4486 #define REG_HDCP_DUAL_P1_1F_H (REG_HDCP_DUAL_P1_BASE + 0x3F) 4487 #define REG_HDCP_DUAL_P1_20_L (REG_HDCP_DUAL_P1_BASE + 0x40) 4488 #define REG_HDCP_DUAL_P1_20_H (REG_HDCP_DUAL_P1_BASE + 0x41) 4489 #define REG_HDCP_DUAL_P1_21_L (REG_HDCP_DUAL_P1_BASE + 0x42) 4490 #define REG_HDCP_DUAL_P1_21_H (REG_HDCP_DUAL_P1_BASE + 0x43) 4491 #define REG_HDCP_DUAL_P1_22_L (REG_HDCP_DUAL_P1_BASE + 0x44) 4492 #define REG_HDCP_DUAL_P1_22_H (REG_HDCP_DUAL_P1_BASE + 0x45) 4493 #define REG_HDCP_DUAL_P1_23_L (REG_HDCP_DUAL_P1_BASE + 0x46) 4494 #define REG_HDCP_DUAL_P1_23_H (REG_HDCP_DUAL_P1_BASE + 0x47) 4495 #define REG_HDCP_DUAL_P1_24_L (REG_HDCP_DUAL_P1_BASE + 0x48) 4496 #define REG_HDCP_DUAL_P1_24_H (REG_HDCP_DUAL_P1_BASE + 0x49) 4497 #define REG_HDCP_DUAL_P1_25_L (REG_HDCP_DUAL_P1_BASE + 0x4A) 4498 #define REG_HDCP_DUAL_P1_25_H (REG_HDCP_DUAL_P1_BASE + 0x4B) 4499 #define REG_HDCP_DUAL_P1_26_L (REG_HDCP_DUAL_P1_BASE + 0x4C) 4500 #define REG_HDCP_DUAL_P1_26_H (REG_HDCP_DUAL_P1_BASE + 0x4D) 4501 #define REG_HDCP_DUAL_P1_27_L (REG_HDCP_DUAL_P1_BASE + 0x4E) 4502 #define REG_HDCP_DUAL_P1_27_H (REG_HDCP_DUAL_P1_BASE + 0x4F) 4503 #define REG_HDCP_DUAL_P1_28_L (REG_HDCP_DUAL_P1_BASE + 0x50) 4504 #define REG_HDCP_DUAL_P1_28_H (REG_HDCP_DUAL_P1_BASE + 0x51) 4505 #define REG_HDCP_DUAL_P1_29_L (REG_HDCP_DUAL_P1_BASE + 0x52) 4506 #define REG_HDCP_DUAL_P1_29_H (REG_HDCP_DUAL_P1_BASE + 0x53) 4507 #define REG_HDCP_DUAL_P1_2A_L (REG_HDCP_DUAL_P1_BASE + 0x54) 4508 #define REG_HDCP_DUAL_P1_2A_H (REG_HDCP_DUAL_P1_BASE + 0x55) 4509 #define REG_HDCP_DUAL_P1_2B_L (REG_HDCP_DUAL_P1_BASE + 0x56) 4510 #define REG_HDCP_DUAL_P1_2B_H (REG_HDCP_DUAL_P1_BASE + 0x57) 4511 #define REG_HDCP_DUAL_P1_2C_L (REG_HDCP_DUAL_P1_BASE + 0x58) 4512 #define REG_HDCP_DUAL_P1_2C_H (REG_HDCP_DUAL_P1_BASE + 0x59) 4513 #define REG_HDCP_DUAL_P1_2D_L (REG_HDCP_DUAL_P1_BASE + 0x5A) 4514 #define REG_HDCP_DUAL_P1_2D_H (REG_HDCP_DUAL_P1_BASE + 0x5B) 4515 #define REG_HDCP_DUAL_P1_2E_L (REG_HDCP_DUAL_P1_BASE + 0x5C) 4516 #define REG_HDCP_DUAL_P1_2E_H (REG_HDCP_DUAL_P1_BASE + 0x5D) 4517 #define REG_HDCP_DUAL_P1_2F_L (REG_HDCP_DUAL_P1_BASE + 0x5E) 4518 #define REG_HDCP_DUAL_P1_2F_H (REG_HDCP_DUAL_P1_BASE + 0x5F) 4519 #define REG_HDCP_DUAL_P1_30_L (REG_HDCP_DUAL_P1_BASE + 0x60) 4520 #define REG_HDCP_DUAL_P1_30_H (REG_HDCP_DUAL_P1_BASE + 0x61) 4521 #define REG_HDCP_DUAL_P1_31_L (REG_HDCP_DUAL_P1_BASE + 0x62) 4522 #define REG_HDCP_DUAL_P1_31_H (REG_HDCP_DUAL_P1_BASE + 0x63) 4523 #define REG_HDCP_DUAL_P1_32_L (REG_HDCP_DUAL_P1_BASE + 0x64) 4524 #define REG_HDCP_DUAL_P1_32_H (REG_HDCP_DUAL_P1_BASE + 0x65) 4525 #define REG_HDCP_DUAL_P1_33_L (REG_HDCP_DUAL_P1_BASE + 0x66) 4526 #define REG_HDCP_DUAL_P1_33_H (REG_HDCP_DUAL_P1_BASE + 0x67) 4527 #define REG_HDCP_DUAL_P1_34_L (REG_HDCP_DUAL_P1_BASE + 0x68) 4528 #define REG_HDCP_DUAL_P1_34_H (REG_HDCP_DUAL_P1_BASE + 0x69) 4529 #define REG_HDCP_DUAL_P1_35_L (REG_HDCP_DUAL_P1_BASE + 0x6A) 4530 #define REG_HDCP_DUAL_P1_35_H (REG_HDCP_DUAL_P1_BASE + 0x6B) 4531 #define REG_HDCP_DUAL_P1_36_L (REG_HDCP_DUAL_P1_BASE + 0x6C) 4532 #define REG_HDCP_DUAL_P1_36_H (REG_HDCP_DUAL_P1_BASE + 0x6D) 4533 #define REG_HDCP_DUAL_P1_37_L (REG_HDCP_DUAL_P1_BASE + 0x6E) 4534 #define REG_HDCP_DUAL_P1_37_H (REG_HDCP_DUAL_P1_BASE + 0x6F) 4535 #define REG_HDCP_DUAL_P1_38_L (REG_HDCP_DUAL_P1_BASE + 0x70) 4536 #define REG_HDCP_DUAL_P1_38_H (REG_HDCP_DUAL_P1_BASE + 0x71) 4537 #define REG_HDCP_DUAL_P1_39_L (REG_HDCP_DUAL_P1_BASE + 0x72) 4538 #define REG_HDCP_DUAL_P1_39_H (REG_HDCP_DUAL_P1_BASE + 0x73) 4539 #define REG_HDCP_DUAL_P1_3A_L (REG_HDCP_DUAL_P1_BASE + 0x74) 4540 #define REG_HDCP_DUAL_P1_3A_H (REG_HDCP_DUAL_P1_BASE + 0x75) 4541 #define REG_HDCP_DUAL_P1_3B_L (REG_HDCP_DUAL_P1_BASE + 0x76) 4542 #define REG_HDCP_DUAL_P1_3B_H (REG_HDCP_DUAL_P1_BASE + 0x77) 4543 #define REG_HDCP_DUAL_P1_3C_L (REG_HDCP_DUAL_P1_BASE + 0x78) 4544 #define REG_HDCP_DUAL_P1_3C_H (REG_HDCP_DUAL_P1_BASE + 0x79) 4545 #define REG_HDCP_DUAL_P1_3D_L (REG_HDCP_DUAL_P1_BASE + 0x7A) 4546 #define REG_HDCP_DUAL_P1_3D_H (REG_HDCP_DUAL_P1_BASE + 0x7B) 4547 #define REG_HDCP_DUAL_P1_3E_L (REG_HDCP_DUAL_P1_BASE + 0x7C) 4548 #define REG_HDCP_DUAL_P1_3E_H (REG_HDCP_DUAL_P1_BASE + 0x7D) 4549 #define REG_HDCP_DUAL_P1_3F_L (REG_HDCP_DUAL_P1_BASE + 0x7E) 4550 #define REG_HDCP_DUAL_P1_3F_H (REG_HDCP_DUAL_P1_BASE + 0x7F) 4551 #define REG_HDCP_DUAL_P1_40_L (REG_HDCP_DUAL_P1_BASE + 0x80) 4552 #define REG_HDCP_DUAL_P1_40_H (REG_HDCP_DUAL_P1_BASE + 0x81) 4553 #define REG_HDCP_DUAL_P1_41_L (REG_HDCP_DUAL_P1_BASE + 0x82) 4554 #define REG_HDCP_DUAL_P1_41_H (REG_HDCP_DUAL_P1_BASE + 0x83) 4555 #define REG_HDCP_DUAL_P1_42_L (REG_HDCP_DUAL_P1_BASE + 0x84) 4556 #define REG_HDCP_DUAL_P1_42_H (REG_HDCP_DUAL_P1_BASE + 0x85) 4557 #define REG_HDCP_DUAL_P1_43_L (REG_HDCP_DUAL_P1_BASE + 0x86) 4558 #define REG_HDCP_DUAL_P1_43_H (REG_HDCP_DUAL_P1_BASE + 0x87) 4559 #define REG_HDCP_DUAL_P1_44_L (REG_HDCP_DUAL_P1_BASE + 0x88) 4560 #define REG_HDCP_DUAL_P1_44_H (REG_HDCP_DUAL_P1_BASE + 0x89) 4561 #define REG_HDCP_DUAL_P1_45_L (REG_HDCP_DUAL_P1_BASE + 0x8A) 4562 #define REG_HDCP_DUAL_P1_45_H (REG_HDCP_DUAL_P1_BASE + 0x8B) 4563 #define REG_HDCP_DUAL_P1_46_L (REG_HDCP_DUAL_P1_BASE + 0x8C) 4564 #define REG_HDCP_DUAL_P1_46_H (REG_HDCP_DUAL_P1_BASE + 0x8D) 4565 #define REG_HDCP_DUAL_P1_47_L (REG_HDCP_DUAL_P1_BASE + 0x8E) 4566 #define REG_HDCP_DUAL_P1_47_H (REG_HDCP_DUAL_P1_BASE + 0x8F) 4567 #define REG_HDCP_DUAL_P1_48_L (REG_HDCP_DUAL_P1_BASE + 0x90) 4568 #define REG_HDCP_DUAL_P1_48_H (REG_HDCP_DUAL_P1_BASE + 0x91) 4569 #define REG_HDCP_DUAL_P1_49_L (REG_HDCP_DUAL_P1_BASE + 0x92) 4570 #define REG_HDCP_DUAL_P1_49_H (REG_HDCP_DUAL_P1_BASE + 0x93) 4571 #define REG_HDCP_DUAL_P1_4A_L (REG_HDCP_DUAL_P1_BASE + 0x94) 4572 #define REG_HDCP_DUAL_P1_4A_H (REG_HDCP_DUAL_P1_BASE + 0x95) 4573 #define REG_HDCP_DUAL_P1_4B_L (REG_HDCP_DUAL_P1_BASE + 0x96) 4574 #define REG_HDCP_DUAL_P1_4B_H (REG_HDCP_DUAL_P1_BASE + 0x97) 4575 #define REG_HDCP_DUAL_P1_4C_L (REG_HDCP_DUAL_P1_BASE + 0x98) 4576 #define REG_HDCP_DUAL_P1_4C_H (REG_HDCP_DUAL_P1_BASE + 0x99) 4577 #define REG_HDCP_DUAL_P1_4D_L (REG_HDCP_DUAL_P1_BASE + 0x9A) 4578 #define REG_HDCP_DUAL_P1_4D_H (REG_HDCP_DUAL_P1_BASE + 0x9B) 4579 #define REG_HDCP_DUAL_P1_4E_L (REG_HDCP_DUAL_P1_BASE + 0x9C) 4580 #define REG_HDCP_DUAL_P1_4E_H (REG_HDCP_DUAL_P1_BASE + 0x9D) 4581 #define REG_HDCP_DUAL_P1_4F_L (REG_HDCP_DUAL_P1_BASE + 0x9E) 4582 #define REG_HDCP_DUAL_P1_4F_H (REG_HDCP_DUAL_P1_BASE + 0x9F) 4583 #define REG_HDCP_DUAL_P1_50_L (REG_HDCP_DUAL_P1_BASE + 0xA0) 4584 #define REG_HDCP_DUAL_P1_50_H (REG_HDCP_DUAL_P1_BASE + 0xA1) 4585 #define REG_HDCP_DUAL_P1_51_L (REG_HDCP_DUAL_P1_BASE + 0xA2) 4586 #define REG_HDCP_DUAL_P1_51_H (REG_HDCP_DUAL_P1_BASE + 0xA3) 4587 #define REG_HDCP_DUAL_P1_52_L (REG_HDCP_DUAL_P1_BASE + 0xA4) 4588 #define REG_HDCP_DUAL_P1_52_H (REG_HDCP_DUAL_P1_BASE + 0xA5) 4589 #define REG_HDCP_DUAL_P1_53_L (REG_HDCP_DUAL_P1_BASE + 0xA6) 4590 #define REG_HDCP_DUAL_P1_53_H (REG_HDCP_DUAL_P1_BASE + 0xA7) 4591 #define REG_HDCP_DUAL_P1_54_L (REG_HDCP_DUAL_P1_BASE + 0xA8) 4592 #define REG_HDCP_DUAL_P1_54_H (REG_HDCP_DUAL_P1_BASE + 0xA9) 4593 #define REG_HDCP_DUAL_P1_55_L (REG_HDCP_DUAL_P1_BASE + 0xAA) 4594 #define REG_HDCP_DUAL_P1_55_H (REG_HDCP_DUAL_P1_BASE + 0xAB) 4595 #define REG_HDCP_DUAL_P1_56_L (REG_HDCP_DUAL_P1_BASE + 0xAC) 4596 #define REG_HDCP_DUAL_P1_56_H (REG_HDCP_DUAL_P1_BASE + 0xAD) 4597 #define REG_HDCP_DUAL_P1_57_L (REG_HDCP_DUAL_P1_BASE + 0xAE) 4598 #define REG_HDCP_DUAL_P1_57_H (REG_HDCP_DUAL_P1_BASE + 0xAF) 4599 #define REG_HDCP_DUAL_P1_58_L (REG_HDCP_DUAL_P1_BASE + 0xB0) 4600 #define REG_HDCP_DUAL_P1_58_H (REG_HDCP_DUAL_P1_BASE + 0xB1) 4601 #define REG_HDCP_DUAL_P1_59_L (REG_HDCP_DUAL_P1_BASE + 0xB2) 4602 #define REG_HDCP_DUAL_P1_59_H (REG_HDCP_DUAL_P1_BASE + 0xB3) 4603 #define REG_HDCP_DUAL_P1_5A_L (REG_HDCP_DUAL_P1_BASE + 0xB4) 4604 #define REG_HDCP_DUAL_P1_5A_H (REG_HDCP_DUAL_P1_BASE + 0xB5) 4605 #define REG_HDCP_DUAL_P1_5B_L (REG_HDCP_DUAL_P1_BASE + 0xB6) 4606 #define REG_HDCP_DUAL_P1_5B_H (REG_HDCP_DUAL_P1_BASE + 0xB7) 4607 #define REG_HDCP_DUAL_P1_5C_L (REG_HDCP_DUAL_P1_BASE + 0xB8) 4608 #define REG_HDCP_DUAL_P1_5C_H (REG_HDCP_DUAL_P1_BASE + 0xB9) 4609 #define REG_HDCP_DUAL_P1_5D_L (REG_HDCP_DUAL_P1_BASE + 0xBA) 4610 #define REG_HDCP_DUAL_P1_5D_H (REG_HDCP_DUAL_P1_BASE + 0xBB) 4611 #define REG_HDCP_DUAL_P1_5E_L (REG_HDCP_DUAL_P1_BASE + 0xBC) 4612 #define REG_HDCP_DUAL_P1_5E_H (REG_HDCP_DUAL_P1_BASE + 0xBD) 4613 #define REG_HDCP_DUAL_P1_5F_L (REG_HDCP_DUAL_P1_BASE + 0xBE) 4614 #define REG_HDCP_DUAL_P1_5F_H (REG_HDCP_DUAL_P1_BASE + 0xBF) 4615 #define REG_HDCP_DUAL_P1_60_L (REG_HDCP_DUAL_P1_BASE + 0xC0) 4616 #define REG_HDCP_DUAL_P1_60_H (REG_HDCP_DUAL_P1_BASE + 0xC1) 4617 #define REG_HDCP_DUAL_P1_61_L (REG_HDCP_DUAL_P1_BASE + 0xC2) 4618 #define REG_HDCP_DUAL_P1_61_H (REG_HDCP_DUAL_P1_BASE + 0xC3) 4619 #define REG_HDCP_DUAL_P1_62_L (REG_HDCP_DUAL_P1_BASE + 0xC4) 4620 #define REG_HDCP_DUAL_P1_62_H (REG_HDCP_DUAL_P1_BASE + 0xC5) 4621 #define REG_HDCP_DUAL_P1_63_L (REG_HDCP_DUAL_P1_BASE + 0xC6) 4622 #define REG_HDCP_DUAL_P1_63_H (REG_HDCP_DUAL_P1_BASE + 0xC7) 4623 #define REG_HDCP_DUAL_P1_64_L (REG_HDCP_DUAL_P1_BASE + 0xC8) 4624 #define REG_HDCP_DUAL_P1_64_H (REG_HDCP_DUAL_P1_BASE + 0xC9) 4625 #define REG_HDCP_DUAL_P1_65_L (REG_HDCP_DUAL_P1_BASE + 0xCA) 4626 #define REG_HDCP_DUAL_P1_65_H (REG_HDCP_DUAL_P1_BASE + 0xCB) 4627 #define REG_HDCP_DUAL_P1_66_L (REG_HDCP_DUAL_P1_BASE + 0xCC) 4628 #define REG_HDCP_DUAL_P1_66_H (REG_HDCP_DUAL_P1_BASE + 0xCD) 4629 #define REG_HDCP_DUAL_P1_67_L (REG_HDCP_DUAL_P1_BASE + 0xCE) 4630 #define REG_HDCP_DUAL_P1_67_H (REG_HDCP_DUAL_P1_BASE + 0xCF) 4631 #define REG_HDCP_DUAL_P1_68_L (REG_HDCP_DUAL_P1_BASE + 0xD0) 4632 #define REG_HDCP_DUAL_P1_68_H (REG_HDCP_DUAL_P1_BASE + 0xD1) 4633 4634 // DVI_DTOP_DUAL_P2 4635 #define REG_DVI_DTOP_DUAL_P2_00_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x00) 4636 #define REG_DVI_DTOP_DUAL_P2_00_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x01) 4637 #define REG_DVI_DTOP_DUAL_P2_01_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x02) 4638 #define REG_DVI_DTOP_DUAL_P2_01_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x03) 4639 #define REG_DVI_DTOP_DUAL_P2_02_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x04) 4640 #define REG_DVI_DTOP_DUAL_P2_02_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x05) 4641 #define REG_DVI_DTOP_DUAL_P2_03_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x06) 4642 #define REG_DVI_DTOP_DUAL_P2_03_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x07) 4643 #define REG_DVI_DTOP_DUAL_P2_04_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x08) 4644 #define REG_DVI_DTOP_DUAL_P2_04_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x09) 4645 #define REG_DVI_DTOP_DUAL_P2_05_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x0A) 4646 #define REG_DVI_DTOP_DUAL_P2_05_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x0B) 4647 #define REG_DVI_DTOP_DUAL_P2_06_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x0C) 4648 #define REG_DVI_DTOP_DUAL_P2_06_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x0D) 4649 #define REG_DVI_DTOP_DUAL_P2_07_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x0E) 4650 #define REG_DVI_DTOP_DUAL_P2_07_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x0F) 4651 #define REG_DVI_DTOP_DUAL_P2_08_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x10) 4652 #define REG_DVI_DTOP_DUAL_P2_08_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x11) 4653 #define REG_DVI_DTOP_DUAL_P2_09_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x12) 4654 #define REG_DVI_DTOP_DUAL_P2_09_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x13) 4655 #define REG_DVI_DTOP_DUAL_P2_0A_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x14) 4656 #define REG_DVI_DTOP_DUAL_P2_0A_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x15) 4657 #define REG_DVI_DTOP_DUAL_P2_0B_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x16) 4658 #define REG_DVI_DTOP_DUAL_P2_0B_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x17) 4659 #define REG_DVI_DTOP_DUAL_P2_0C_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x18) 4660 #define REG_DVI_DTOP_DUAL_P2_0C_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x19) 4661 #define REG_DVI_DTOP_DUAL_P2_0D_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x1A) 4662 #define REG_DVI_DTOP_DUAL_P2_0D_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x1B) 4663 #define REG_DVI_DTOP_DUAL_P2_0E_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x1C) 4664 #define REG_DVI_DTOP_DUAL_P2_0E_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x1D) 4665 #define REG_DVI_DTOP_DUAL_P2_0F_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x1E) 4666 #define REG_DVI_DTOP_DUAL_P2_0F_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x1F) 4667 #define REG_DVI_DTOP_DUAL_P2_10_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x20) 4668 #define REG_DVI_DTOP_DUAL_P2_10_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x21) 4669 #define REG_DVI_DTOP_DUAL_P2_11_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x22) 4670 #define REG_DVI_DTOP_DUAL_P2_11_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x23) 4671 #define REG_DVI_DTOP_DUAL_P2_12_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x24) 4672 #define REG_DVI_DTOP_DUAL_P2_12_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x25) 4673 #define REG_DVI_DTOP_DUAL_P2_13_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x26) 4674 #define REG_DVI_DTOP_DUAL_P2_13_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x27) 4675 #define REG_DVI_DTOP_DUAL_P2_14_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x28) 4676 #define REG_DVI_DTOP_DUAL_P2_14_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x29) 4677 #define REG_DVI_DTOP_DUAL_P2_15_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x2A) 4678 #define REG_DVI_DTOP_DUAL_P2_15_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x2B) 4679 #define REG_DVI_DTOP_DUAL_P2_16_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x2C) 4680 #define REG_DVI_DTOP_DUAL_P2_16_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x2D) 4681 #define REG_DVI_DTOP_DUAL_P2_17_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x2E) 4682 #define REG_DVI_DTOP_DUAL_P2_17_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x2F) 4683 #define REG_DVI_DTOP_DUAL_P2_18_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x30) 4684 #define REG_DVI_DTOP_DUAL_P2_18_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x31) 4685 #define REG_DVI_DTOP_DUAL_P2_19_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x32) 4686 #define REG_DVI_DTOP_DUAL_P2_19_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x33) 4687 #define REG_DVI_DTOP_DUAL_P2_1A_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x34) 4688 #define REG_DVI_DTOP_DUAL_P2_1A_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x35) 4689 #define REG_DVI_DTOP_DUAL_P2_1B_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x36) 4690 #define REG_DVI_DTOP_DUAL_P2_1B_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x37) 4691 #define REG_DVI_DTOP_DUAL_P2_1C_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x38) 4692 #define REG_DVI_DTOP_DUAL_P2_1C_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x39) 4693 #define REG_DVI_DTOP_DUAL_P2_1D_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x3A) 4694 #define REG_DVI_DTOP_DUAL_P2_1D_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x3B) 4695 #define REG_DVI_DTOP_DUAL_P2_1E_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x3C) 4696 #define REG_DVI_DTOP_DUAL_P2_1E_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x3D) 4697 #define REG_DVI_DTOP_DUAL_P2_1F_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x3E) 4698 #define REG_DVI_DTOP_DUAL_P2_1F_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x3F) 4699 #define REG_DVI_DTOP_DUAL_P2_20_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x40) 4700 #define REG_DVI_DTOP_DUAL_P2_20_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x41) 4701 #define REG_DVI_DTOP_DUAL_P2_21_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x42) 4702 #define REG_DVI_DTOP_DUAL_P2_21_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x43) 4703 #define REG_DVI_DTOP_DUAL_P2_22_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x44) 4704 #define REG_DVI_DTOP_DUAL_P2_22_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x45) 4705 #define REG_DVI_DTOP_DUAL_P2_23_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x46) 4706 #define REG_DVI_DTOP_DUAL_P2_23_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x47) 4707 #define REG_DVI_DTOP_DUAL_P2_24_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x48) 4708 #define REG_DVI_DTOP_DUAL_P2_24_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x49) 4709 #define REG_DVI_DTOP_DUAL_P2_25_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x4A) 4710 #define REG_DVI_DTOP_DUAL_P2_25_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x4B) 4711 #define REG_DVI_DTOP_DUAL_P2_26_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x4C) 4712 #define REG_DVI_DTOP_DUAL_P2_26_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x4D) 4713 #define REG_DVI_DTOP_DUAL_P2_27_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x4E) 4714 #define REG_DVI_DTOP_DUAL_P2_27_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x4F) 4715 #define REG_DVI_DTOP_DUAL_P2_28_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x50) 4716 #define REG_DVI_DTOP_DUAL_P2_28_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x51) 4717 #define REG_DVI_DTOP_DUAL_P2_29_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x52) 4718 #define REG_DVI_DTOP_DUAL_P2_29_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x53) 4719 #define REG_DVI_DTOP_DUAL_P2_2A_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x54) 4720 #define REG_DVI_DTOP_DUAL_P2_2A_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x55) 4721 #define REG_DVI_DTOP_DUAL_P2_2B_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x56) 4722 #define REG_DVI_DTOP_DUAL_P2_2B_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x57) 4723 #define REG_DVI_DTOP_DUAL_P2_2C_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x58) 4724 #define REG_DVI_DTOP_DUAL_P2_2C_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x59) 4725 #define REG_DVI_DTOP_DUAL_P2_2D_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x5A) 4726 #define REG_DVI_DTOP_DUAL_P2_2D_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x5B) 4727 #define REG_DVI_DTOP_DUAL_P2_2E_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x5C) 4728 #define REG_DVI_DTOP_DUAL_P2_2E_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x5D) 4729 #define REG_DVI_DTOP_DUAL_P2_2F_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x5E) 4730 #define REG_DVI_DTOP_DUAL_P2_2F_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x5F) 4731 #define REG_DVI_DTOP_DUAL_P2_30_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x60) 4732 #define REG_DVI_DTOP_DUAL_P2_30_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x61) 4733 #define REG_DVI_DTOP_DUAL_P2_31_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x62) 4734 #define REG_DVI_DTOP_DUAL_P2_31_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x63) 4735 #define REG_DVI_DTOP_DUAL_P2_32_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x64) 4736 #define REG_DVI_DTOP_DUAL_P2_32_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x65) 4737 #define REG_DVI_DTOP_DUAL_P2_33_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x66) 4738 #define REG_DVI_DTOP_DUAL_P2_33_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x67) 4739 #define REG_DVI_DTOP_DUAL_P2_34_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x68) 4740 #define REG_DVI_DTOP_DUAL_P2_34_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x69) 4741 #define REG_DVI_DTOP_DUAL_P2_35_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x6A) 4742 #define REG_DVI_DTOP_DUAL_P2_35_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x6B) 4743 #define REG_DVI_DTOP_DUAL_P2_36_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x6C) 4744 #define REG_DVI_DTOP_DUAL_P2_36_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x6D) 4745 #define REG_DVI_DTOP_DUAL_P2_37_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x6E) 4746 #define REG_DVI_DTOP_DUAL_P2_37_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x6F) 4747 #define REG_DVI_DTOP_DUAL_P2_38_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x70) 4748 #define REG_DVI_DTOP_DUAL_P2_38_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x71) 4749 #define REG_DVI_DTOP_DUAL_P2_39_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x72) 4750 #define REG_DVI_DTOP_DUAL_P2_39_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x73) 4751 #define REG_DVI_DTOP_DUAL_P2_3A_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x74) 4752 #define REG_DVI_DTOP_DUAL_P2_3A_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x75) 4753 #define REG_DVI_DTOP_DUAL_P2_3B_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x76) 4754 #define REG_DVI_DTOP_DUAL_P2_3B_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x77) 4755 #define REG_DVI_DTOP_DUAL_P2_3C_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x78) 4756 #define REG_DVI_DTOP_DUAL_P2_3C_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x79) 4757 #define REG_DVI_DTOP_DUAL_P2_3D_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x7A) 4758 #define REG_DVI_DTOP_DUAL_P2_3D_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x7B) 4759 #define REG_DVI_DTOP_DUAL_P2_3E_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x7C) 4760 #define REG_DVI_DTOP_DUAL_P2_3E_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x7D) 4761 #define REG_DVI_DTOP_DUAL_P2_3F_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x7E) 4762 #define REG_DVI_DTOP_DUAL_P2_3F_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x7F) 4763 #define REG_DVI_DTOP_DUAL_P2_40_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x80) 4764 #define REG_DVI_DTOP_DUAL_P2_40_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x81) 4765 #define REG_DVI_DTOP_DUAL_P2_41_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x82) 4766 #define REG_DVI_DTOP_DUAL_P2_41_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x83) 4767 #define REG_DVI_DTOP_DUAL_P2_42_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x84) 4768 #define REG_DVI_DTOP_DUAL_P2_42_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x85) 4769 #define REG_DVI_DTOP_DUAL_P2_43_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x86) 4770 #define REG_DVI_DTOP_DUAL_P2_43_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x87) 4771 #define REG_DVI_DTOP_DUAL_P2_44_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x88) 4772 #define REG_DVI_DTOP_DUAL_P2_44_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x89) 4773 #define REG_DVI_DTOP_DUAL_P2_45_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x8A) 4774 #define REG_DVI_DTOP_DUAL_P2_45_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x8B) 4775 #define REG_DVI_DTOP_DUAL_P2_46_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x8C) 4776 #define REG_DVI_DTOP_DUAL_P2_46_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x8D) 4777 #define REG_DVI_DTOP_DUAL_P2_47_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x8E) 4778 #define REG_DVI_DTOP_DUAL_P2_47_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x8F) 4779 #define REG_DVI_DTOP_DUAL_P2_48_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x90) 4780 #define REG_DVI_DTOP_DUAL_P2_48_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x91) 4781 #define REG_DVI_DTOP_DUAL_P2_49_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x92) 4782 #define REG_DVI_DTOP_DUAL_P2_49_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x93) 4783 #define REG_DVI_DTOP_DUAL_P2_4A_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x94) 4784 #define REG_DVI_DTOP_DUAL_P2_4A_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x95) 4785 #define REG_DVI_DTOP_DUAL_P2_4B_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x96) 4786 #define REG_DVI_DTOP_DUAL_P2_4B_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x97) 4787 #define REG_DVI_DTOP_DUAL_P2_4C_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x98) 4788 #define REG_DVI_DTOP_DUAL_P2_4C_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x99) 4789 #define REG_DVI_DTOP_DUAL_P2_4D_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x9A) 4790 #define REG_DVI_DTOP_DUAL_P2_4D_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x9B) 4791 #define REG_DVI_DTOP_DUAL_P2_4E_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x9C) 4792 #define REG_DVI_DTOP_DUAL_P2_4E_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x9D) 4793 #define REG_DVI_DTOP_DUAL_P2_4F_L (REG_DVI_DTOP_DUAL_P2_BASE + 0x9E) 4794 #define REG_DVI_DTOP_DUAL_P2_4F_H (REG_DVI_DTOP_DUAL_P2_BASE + 0x9F) 4795 #define REG_DVI_DTOP_DUAL_P2_50_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xA0) 4796 #define REG_DVI_DTOP_DUAL_P2_50_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xA1) 4797 #define REG_DVI_DTOP_DUAL_P2_51_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xA2) 4798 #define REG_DVI_DTOP_DUAL_P2_51_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xA3) 4799 #define REG_DVI_DTOP_DUAL_P2_52_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xA4) 4800 #define REG_DVI_DTOP_DUAL_P2_52_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xA5) 4801 #define REG_DVI_DTOP_DUAL_P2_53_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xA6) 4802 #define REG_DVI_DTOP_DUAL_P2_53_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xA7) 4803 #define REG_DVI_DTOP_DUAL_P2_54_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xA8) 4804 #define REG_DVI_DTOP_DUAL_P2_54_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xA9) 4805 #define REG_DVI_DTOP_DUAL_P2_55_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xAA) 4806 #define REG_DVI_DTOP_DUAL_P2_55_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xAB) 4807 #define REG_DVI_DTOP_DUAL_P2_56_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xAC) 4808 #define REG_DVI_DTOP_DUAL_P2_56_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xAD) 4809 #define REG_DVI_DTOP_DUAL_P2_57_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xAE) 4810 #define REG_DVI_DTOP_DUAL_P2_57_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xAF) 4811 #define REG_DVI_DTOP_DUAL_P2_58_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xB0) 4812 #define REG_DVI_DTOP_DUAL_P2_58_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xB1) 4813 #define REG_DVI_DTOP_DUAL_P2_59_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xB2) 4814 #define REG_DVI_DTOP_DUAL_P2_59_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xB3) 4815 #define REG_DVI_DTOP_DUAL_P2_5A_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xB4) 4816 #define REG_DVI_DTOP_DUAL_P2_5A_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xB5) 4817 #define REG_DVI_DTOP_DUAL_P2_5B_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xB6) 4818 #define REG_DVI_DTOP_DUAL_P2_5B_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xB7) 4819 #define REG_DVI_DTOP_DUAL_P2_5C_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xB8) 4820 #define REG_DVI_DTOP_DUAL_P2_5C_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xB9) 4821 #define REG_DVI_DTOP_DUAL_P2_5D_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xBA) 4822 #define REG_DVI_DTOP_DUAL_P2_5D_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xBB) 4823 #define REG_DVI_DTOP_DUAL_P2_5E_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xBC) 4824 #define REG_DVI_DTOP_DUAL_P2_5E_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xBD) 4825 #define REG_DVI_DTOP_DUAL_P2_5F_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xBE) 4826 #define REG_DVI_DTOP_DUAL_P2_5F_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xBF) 4827 #define REG_DVI_DTOP_DUAL_P2_60_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC0) 4828 #define REG_DVI_DTOP_DUAL_P2_60_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xC1) 4829 #define REG_DVI_DTOP_DUAL_P2_61_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC2) 4830 #define REG_DVI_DTOP_DUAL_P2_61_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xC3) 4831 #define REG_DVI_DTOP_DUAL_P2_62_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC4) 4832 #define REG_DVI_DTOP_DUAL_P2_62_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xC5) 4833 #define REG_DVI_DTOP_DUAL_P2_63_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC6) 4834 #define REG_DVI_DTOP_DUAL_P2_63_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xC7) 4835 #define REG_DVI_DTOP_DUAL_P2_64_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xC8) 4836 #define REG_DVI_DTOP_DUAL_P2_64_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xC9) 4837 #define REG_DVI_DTOP_DUAL_P2_65_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xCA) 4838 #define REG_DVI_DTOP_DUAL_P2_65_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xCB) 4839 #define REG_DVI_DTOP_DUAL_P2_66_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xCC) 4840 #define REG_DVI_DTOP_DUAL_P2_66_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xCD) 4841 #define REG_DVI_DTOP_DUAL_P2_67_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xCE) 4842 #define REG_DVI_DTOP_DUAL_P2_67_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xCF) 4843 #define REG_DVI_DTOP_DUAL_P2_68_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xD0) 4844 #define REG_DVI_DTOP_DUAL_P2_68_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xD1) 4845 #define REG_DVI_DTOP_DUAL_P2_69_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xD2) 4846 #define REG_DVI_DTOP_DUAL_P2_69_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xD3) 4847 #define REG_DVI_DTOP_DUAL_P2_6A_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xD4) 4848 #define REG_DVI_DTOP_DUAL_P2_6A_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xD5) 4849 #define REG_DVI_DTOP_DUAL_P2_6B_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xD6) 4850 #define REG_DVI_DTOP_DUAL_P2_6B_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xD7) 4851 #define REG_DVI_DTOP_DUAL_P2_6C_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xD8) 4852 #define REG_DVI_DTOP_DUAL_P2_6C_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xD9) 4853 #define REG_DVI_DTOP_DUAL_P2_6D_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xDA) 4854 #define REG_DVI_DTOP_DUAL_P2_6D_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xDB) 4855 #define REG_DVI_DTOP_DUAL_P2_6E_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xDC) 4856 #define REG_DVI_DTOP_DUAL_P2_6E_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xDD) 4857 #define REG_DVI_DTOP_DUAL_P2_6F_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xDE) 4858 #define REG_DVI_DTOP_DUAL_P2_6F_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xDF) 4859 #define REG_DVI_DTOP_DUAL_P2_70_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xE0) 4860 #define REG_DVI_DTOP_DUAL_P2_70_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xE1) 4861 #define REG_DVI_DTOP_DUAL_P2_71_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xE2) 4862 #define REG_DVI_DTOP_DUAL_P2_71_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xE3) 4863 #define REG_DVI_DTOP_DUAL_P2_72_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xE4) 4864 #define REG_DVI_DTOP_DUAL_P2_72_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xE5) 4865 #define REG_DVI_DTOP_DUAL_P2_73_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xE6) 4866 #define REG_DVI_DTOP_DUAL_P2_73_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xE7) 4867 #define REG_DVI_DTOP_DUAL_P2_74_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xE8) 4868 #define REG_DVI_DTOP_DUAL_P2_74_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xE9) 4869 #define REG_DVI_DTOP_DUAL_P2_75_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xEA) 4870 #define REG_DVI_DTOP_DUAL_P2_75_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xEB) 4871 #define REG_DVI_DTOP_DUAL_P2_76_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xEC) 4872 #define REG_DVI_DTOP_DUAL_P2_76_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xED) 4873 #define REG_DVI_DTOP_DUAL_P2_77_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xEE) 4874 #define REG_DVI_DTOP_DUAL_P2_77_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xEF) 4875 #define REG_DVI_DTOP_DUAL_P2_78_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xF0) 4876 #define REG_DVI_DTOP_DUAL_P2_78_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xF1) 4877 #define REG_DVI_DTOP_DUAL_P2_79_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xF2) 4878 #define REG_DVI_DTOP_DUAL_P2_79_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xF3) 4879 #define REG_DVI_DTOP_DUAL_P2_7A_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xF4) 4880 #define REG_DVI_DTOP_DUAL_P2_7A_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xF5) 4881 #define REG_DVI_DTOP_DUAL_P2_7B_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xF6) 4882 #define REG_DVI_DTOP_DUAL_P2_7B_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xF7) 4883 #define REG_DVI_DTOP_DUAL_P2_7C_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xF8) 4884 #define REG_DVI_DTOP_DUAL_P2_7C_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xF9) 4885 #define REG_DVI_DTOP_DUAL_P2_7D_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xFA) 4886 #define REG_DVI_DTOP_DUAL_P2_7D_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xFB) 4887 #define REG_DVI_DTOP_DUAL_P2_7E_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xFC) 4888 #define REG_DVI_DTOP_DUAL_P2_7E_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xFD) 4889 #define REG_DVI_DTOP_DUAL_P2_7F_L (REG_DVI_DTOP_DUAL_P2_BASE + 0xFE) 4890 #define REG_DVI_DTOP_DUAL_P2_7F_H (REG_DVI_DTOP_DUAL_P2_BASE + 0xFF) 4891 4892 // DVI_RSV_DUAL_P2 4893 #define REG_DVI_RSV_DUAL_P2_00_L (REG_DVI_RSV_DUAL_P2_BASE + 0x00) 4894 #define REG_DVI_RSV_DUAL_P2_00_H (REG_DVI_RSV_DUAL_P2_BASE + 0x01) 4895 #define REG_DVI_RSV_DUAL_P2_01_L (REG_DVI_RSV_DUAL_P2_BASE + 0x02) 4896 #define REG_DVI_RSV_DUAL_P2_01_H (REG_DVI_RSV_DUAL_P2_BASE + 0x03) 4897 #define REG_DVI_RSV_DUAL_P2_02_L (REG_DVI_RSV_DUAL_P2_BASE + 0x04) 4898 #define REG_DVI_RSV_DUAL_P2_02_H (REG_DVI_RSV_DUAL_P2_BASE + 0x05) 4899 #define REG_DVI_RSV_DUAL_P2_03_L (REG_DVI_RSV_DUAL_P2_BASE + 0x06) 4900 #define REG_DVI_RSV_DUAL_P2_03_H (REG_DVI_RSV_DUAL_P2_BASE + 0x07) 4901 #define REG_DVI_RSV_DUAL_P2_04_L (REG_DVI_RSV_DUAL_P2_BASE + 0x08) 4902 #define REG_DVI_RSV_DUAL_P2_04_H (REG_DVI_RSV_DUAL_P2_BASE + 0x09) 4903 #define REG_DVI_RSV_DUAL_P2_05_L (REG_DVI_RSV_DUAL_P2_BASE + 0x0A) 4904 #define REG_DVI_RSV_DUAL_P2_05_H (REG_DVI_RSV_DUAL_P2_BASE + 0x0B) 4905 #define REG_DVI_RSV_DUAL_P2_06_L (REG_DVI_RSV_DUAL_P2_BASE + 0x0C) 4906 #define REG_DVI_RSV_DUAL_P2_06_H (REG_DVI_RSV_DUAL_P2_BASE + 0x0D) 4907 #define REG_DVI_RSV_DUAL_P2_07_L (REG_DVI_RSV_DUAL_P2_BASE + 0x0E) 4908 #define REG_DVI_RSV_DUAL_P2_07_H (REG_DVI_RSV_DUAL_P2_BASE + 0x0F) 4909 #define REG_DVI_RSV_DUAL_P2_08_L (REG_DVI_RSV_DUAL_P2_BASE + 0x10) 4910 #define REG_DVI_RSV_DUAL_P2_08_H (REG_DVI_RSV_DUAL_P2_BASE + 0x11) 4911 #define REG_DVI_RSV_DUAL_P2_09_L (REG_DVI_RSV_DUAL_P2_BASE + 0x12) 4912 #define REG_DVI_RSV_DUAL_P2_09_H (REG_DVI_RSV_DUAL_P2_BASE + 0x13) 4913 #define REG_DVI_RSV_DUAL_P2_0A_L (REG_DVI_RSV_DUAL_P2_BASE + 0x14) 4914 #define REG_DVI_RSV_DUAL_P2_0A_H (REG_DVI_RSV_DUAL_P2_BASE + 0x15) 4915 #define REG_DVI_RSV_DUAL_P2_0B_L (REG_DVI_RSV_DUAL_P2_BASE + 0x16) 4916 #define REG_DVI_RSV_DUAL_P2_0B_H (REG_DVI_RSV_DUAL_P2_BASE + 0x17) 4917 #define REG_DVI_RSV_DUAL_P2_0C_L (REG_DVI_RSV_DUAL_P2_BASE + 0x18) 4918 #define REG_DVI_RSV_DUAL_P2_0C_H (REG_DVI_RSV_DUAL_P2_BASE + 0x19) 4919 #define REG_DVI_RSV_DUAL_P2_0D_L (REG_DVI_RSV_DUAL_P2_BASE + 0x1A) 4920 #define REG_DVI_RSV_DUAL_P2_0D_H (REG_DVI_RSV_DUAL_P2_BASE + 0x1B) 4921 #define REG_DVI_RSV_DUAL_P2_0E_L (REG_DVI_RSV_DUAL_P2_BASE + 0x1C) 4922 #define REG_DVI_RSV_DUAL_P2_0E_H (REG_DVI_RSV_DUAL_P2_BASE + 0x1D) 4923 #define REG_DVI_RSV_DUAL_P2_0F_L (REG_DVI_RSV_DUAL_P2_BASE + 0x1E) 4924 #define REG_DVI_RSV_DUAL_P2_0F_H (REG_DVI_RSV_DUAL_P2_BASE + 0x1F) 4925 #define REG_DVI_RSV_DUAL_P2_10_L (REG_DVI_RSV_DUAL_P2_BASE + 0x20) 4926 #define REG_DVI_RSV_DUAL_P2_10_H (REG_DVI_RSV_DUAL_P2_BASE + 0x21) 4927 #define REG_DVI_RSV_DUAL_P2_11_L (REG_DVI_RSV_DUAL_P2_BASE + 0x22) 4928 #define REG_DVI_RSV_DUAL_P2_11_H (REG_DVI_RSV_DUAL_P2_BASE + 0x23) 4929 #define REG_DVI_RSV_DUAL_P2_12_L (REG_DVI_RSV_DUAL_P2_BASE + 0x24) 4930 #define REG_DVI_RSV_DUAL_P2_12_H (REG_DVI_RSV_DUAL_P2_BASE + 0x25) 4931 #define REG_DVI_RSV_DUAL_P2_13_L (REG_DVI_RSV_DUAL_P2_BASE + 0x26) 4932 #define REG_DVI_RSV_DUAL_P2_13_H (REG_DVI_RSV_DUAL_P2_BASE + 0x27) 4933 #define REG_DVI_RSV_DUAL_P2_14_L (REG_DVI_RSV_DUAL_P2_BASE + 0x28) 4934 #define REG_DVI_RSV_DUAL_P2_14_H (REG_DVI_RSV_DUAL_P2_BASE + 0x29) 4935 #define REG_DVI_RSV_DUAL_P2_15_L (REG_DVI_RSV_DUAL_P2_BASE + 0x2A) 4936 #define REG_DVI_RSV_DUAL_P2_15_H (REG_DVI_RSV_DUAL_P2_BASE + 0x2B) 4937 #define REG_DVI_RSV_DUAL_P2_16_L (REG_DVI_RSV_DUAL_P2_BASE + 0x2C) 4938 #define REG_DVI_RSV_DUAL_P2_16_H (REG_DVI_RSV_DUAL_P2_BASE + 0x2D) 4939 #define REG_DVI_RSV_DUAL_P2_17_L (REG_DVI_RSV_DUAL_P2_BASE + 0x2E) 4940 #define REG_DVI_RSV_DUAL_P2_17_H (REG_DVI_RSV_DUAL_P2_BASE + 0x2F) 4941 #define REG_DVI_RSV_DUAL_P2_18_L (REG_DVI_RSV_DUAL_P2_BASE + 0x30) 4942 #define REG_DVI_RSV_DUAL_P2_18_H (REG_DVI_RSV_DUAL_P2_BASE + 0x31) 4943 #define REG_DVI_RSV_DUAL_P2_19_L (REG_DVI_RSV_DUAL_P2_BASE + 0x32) 4944 #define REG_DVI_RSV_DUAL_P2_19_H (REG_DVI_RSV_DUAL_P2_BASE + 0x33) 4945 #define REG_DVI_RSV_DUAL_P2_1A_L (REG_DVI_RSV_DUAL_P2_BASE + 0x34) 4946 #define REG_DVI_RSV_DUAL_P2_1A_H (REG_DVI_RSV_DUAL_P2_BASE + 0x35) 4947 #define REG_DVI_RSV_DUAL_P2_1B_L (REG_DVI_RSV_DUAL_P2_BASE + 0x36) 4948 #define REG_DVI_RSV_DUAL_P2_1B_H (REG_DVI_RSV_DUAL_P2_BASE + 0x37) 4949 #define REG_DVI_RSV_DUAL_P2_1C_L (REG_DVI_RSV_DUAL_P2_BASE + 0x38) 4950 #define REG_DVI_RSV_DUAL_P2_1C_H (REG_DVI_RSV_DUAL_P2_BASE + 0x39) 4951 #define REG_DVI_RSV_DUAL_P2_1D_L (REG_DVI_RSV_DUAL_P2_BASE + 0x3A) 4952 #define REG_DVI_RSV_DUAL_P2_1D_H (REG_DVI_RSV_DUAL_P2_BASE + 0x3B) 4953 #define REG_DVI_RSV_DUAL_P2_1E_L (REG_DVI_RSV_DUAL_P2_BASE + 0x3C) 4954 #define REG_DVI_RSV_DUAL_P2_1E_H (REG_DVI_RSV_DUAL_P2_BASE + 0x3D) 4955 #define REG_DVI_RSV_DUAL_P2_1F_L (REG_DVI_RSV_DUAL_P2_BASE + 0x3E) 4956 #define REG_DVI_RSV_DUAL_P2_1F_H (REG_DVI_RSV_DUAL_P2_BASE + 0x3F) 4957 4958 // HDCP_DUAL_P2 4959 #define REG_HDCP_DUAL_P2_00_L (REG_HDCP_DUAL_P2_BASE + 0x00) 4960 #define REG_HDCP_DUAL_P2_00_H (REG_HDCP_DUAL_P2_BASE + 0x01) 4961 #define REG_HDCP_DUAL_P2_01_L (REG_HDCP_DUAL_P2_BASE + 0x02) 4962 #define REG_HDCP_DUAL_P2_01_H (REG_HDCP_DUAL_P2_BASE + 0x03) 4963 #define REG_HDCP_DUAL_P2_02_L (REG_HDCP_DUAL_P2_BASE + 0x04) 4964 #define REG_HDCP_DUAL_P2_02_H (REG_HDCP_DUAL_P2_BASE + 0x05) 4965 #define REG_HDCP_DUAL_P2_03_L (REG_HDCP_DUAL_P2_BASE + 0x06) 4966 #define REG_HDCP_DUAL_P2_03_H (REG_HDCP_DUAL_P2_BASE + 0x07) 4967 #define REG_HDCP_DUAL_P2_04_L (REG_HDCP_DUAL_P2_BASE + 0x08) 4968 #define REG_HDCP_DUAL_P2_04_H (REG_HDCP_DUAL_P2_BASE + 0x09) 4969 #define REG_HDCP_DUAL_P2_05_L (REG_HDCP_DUAL_P2_BASE + 0x0A) 4970 #define REG_HDCP_DUAL_P2_05_H (REG_HDCP_DUAL_P2_BASE + 0x0B) 4971 #define REG_HDCP_DUAL_P2_06_L (REG_HDCP_DUAL_P2_BASE + 0x0C) 4972 #define REG_HDCP_DUAL_P2_06_H (REG_HDCP_DUAL_P2_BASE + 0x0D) 4973 #define REG_HDCP_DUAL_P2_07_L (REG_HDCP_DUAL_P2_BASE + 0x0E) 4974 #define REG_HDCP_DUAL_P2_07_H (REG_HDCP_DUAL_P2_BASE + 0x0F) 4975 #define REG_HDCP_DUAL_P2_08_L (REG_HDCP_DUAL_P2_BASE + 0x10) 4976 #define REG_HDCP_DUAL_P2_08_H (REG_HDCP_DUAL_P2_BASE + 0x11) 4977 #define REG_HDCP_DUAL_P2_09_L (REG_HDCP_DUAL_P2_BASE + 0x12) 4978 #define REG_HDCP_DUAL_P2_09_H (REG_HDCP_DUAL_P2_BASE + 0x13) 4979 #define REG_HDCP_DUAL_P2_0A_L (REG_HDCP_DUAL_P2_BASE + 0x14) 4980 #define REG_HDCP_DUAL_P2_0A_H (REG_HDCP_DUAL_P2_BASE + 0x15) 4981 #define REG_HDCP_DUAL_P2_0B_L (REG_HDCP_DUAL_P2_BASE + 0x16) 4982 #define REG_HDCP_DUAL_P2_0B_H (REG_HDCP_DUAL_P2_BASE + 0x17) 4983 #define REG_HDCP_DUAL_P2_0C_L (REG_HDCP_DUAL_P2_BASE + 0x18) 4984 #define REG_HDCP_DUAL_P2_0C_H (REG_HDCP_DUAL_P2_BASE + 0x19) 4985 #define REG_HDCP_DUAL_P2_0D_L (REG_HDCP_DUAL_P2_BASE + 0x1A) 4986 #define REG_HDCP_DUAL_P2_0D_H (REG_HDCP_DUAL_P2_BASE + 0x1B) 4987 #define REG_HDCP_DUAL_P2_0E_L (REG_HDCP_DUAL_P2_BASE + 0x1C) 4988 #define REG_HDCP_DUAL_P2_0E_H (REG_HDCP_DUAL_P2_BASE + 0x1D) 4989 #define REG_HDCP_DUAL_P2_0F_L (REG_HDCP_DUAL_P2_BASE + 0x1E) 4990 #define REG_HDCP_DUAL_P2_0F_H (REG_HDCP_DUAL_P2_BASE + 0x1F) 4991 #define REG_HDCP_DUAL_P2_10_L (REG_HDCP_DUAL_P2_BASE + 0x20) 4992 #define REG_HDCP_DUAL_P2_10_H (REG_HDCP_DUAL_P2_BASE + 0x21) 4993 #define REG_HDCP_DUAL_P2_11_L (REG_HDCP_DUAL_P2_BASE + 0x22) 4994 #define REG_HDCP_DUAL_P2_11_H (REG_HDCP_DUAL_P2_BASE + 0x23) 4995 #define REG_HDCP_DUAL_P2_12_L (REG_HDCP_DUAL_P2_BASE + 0x24) 4996 #define REG_HDCP_DUAL_P2_12_H (REG_HDCP_DUAL_P2_BASE + 0x25) 4997 #define REG_HDCP_DUAL_P2_13_L (REG_HDCP_DUAL_P2_BASE + 0x26) 4998 #define REG_HDCP_DUAL_P2_13_H (REG_HDCP_DUAL_P2_BASE + 0x27) 4999 #define REG_HDCP_DUAL_P2_14_L (REG_HDCP_DUAL_P2_BASE + 0x28) 5000 #define REG_HDCP_DUAL_P2_14_H (REG_HDCP_DUAL_P2_BASE + 0x29) 5001 #define REG_HDCP_DUAL_P2_15_L (REG_HDCP_DUAL_P2_BASE + 0x2A) 5002 #define REG_HDCP_DUAL_P2_15_H (REG_HDCP_DUAL_P2_BASE + 0x2B) 5003 #define REG_HDCP_DUAL_P2_16_L (REG_HDCP_DUAL_P2_BASE + 0x2C) 5004 #define REG_HDCP_DUAL_P2_16_H (REG_HDCP_DUAL_P2_BASE + 0x2D) 5005 #define REG_HDCP_DUAL_P2_17_L (REG_HDCP_DUAL_P2_BASE + 0x2E) 5006 #define REG_HDCP_DUAL_P2_17_H (REG_HDCP_DUAL_P2_BASE + 0x2F) 5007 #define REG_HDCP_DUAL_P2_18_L (REG_HDCP_DUAL_P2_BASE + 0x30) 5008 #define REG_HDCP_DUAL_P2_18_H (REG_HDCP_DUAL_P2_BASE + 0x31) 5009 #define REG_HDCP_DUAL_P2_19_L (REG_HDCP_DUAL_P2_BASE + 0x32) 5010 #define REG_HDCP_DUAL_P2_19_H (REG_HDCP_DUAL_P2_BASE + 0x33) 5011 #define REG_HDCP_DUAL_P2_1A_L (REG_HDCP_DUAL_P2_BASE + 0x34) 5012 #define REG_HDCP_DUAL_P2_1A_H (REG_HDCP_DUAL_P2_BASE + 0x35) 5013 #define REG_HDCP_DUAL_P2_1B_L (REG_HDCP_DUAL_P2_BASE + 0x36) 5014 #define REG_HDCP_DUAL_P2_1B_H (REG_HDCP_DUAL_P2_BASE + 0x37) 5015 #define REG_HDCP_DUAL_P2_1C_L (REG_HDCP_DUAL_P2_BASE + 0x38) 5016 #define REG_HDCP_DUAL_P2_1C_H (REG_HDCP_DUAL_P2_BASE + 0x39) 5017 #define REG_HDCP_DUAL_P2_1D_L (REG_HDCP_DUAL_P2_BASE + 0x3A) 5018 #define REG_HDCP_DUAL_P2_1D_H (REG_HDCP_DUAL_P2_BASE + 0x3B) 5019 #define REG_HDCP_DUAL_P2_1E_L (REG_HDCP_DUAL_P2_BASE + 0x3C) 5020 #define REG_HDCP_DUAL_P2_1E_H (REG_HDCP_DUAL_P2_BASE + 0x3D) 5021 #define REG_HDCP_DUAL_P2_1F_L (REG_HDCP_DUAL_P2_BASE + 0x3E) 5022 #define REG_HDCP_DUAL_P2_1F_H (REG_HDCP_DUAL_P2_BASE + 0x3F) 5023 #define REG_HDCP_DUAL_P2_20_L (REG_HDCP_DUAL_P2_BASE + 0x40) 5024 #define REG_HDCP_DUAL_P2_20_H (REG_HDCP_DUAL_P2_BASE + 0x41) 5025 #define REG_HDCP_DUAL_P2_21_L (REG_HDCP_DUAL_P2_BASE + 0x42) 5026 #define REG_HDCP_DUAL_P2_21_H (REG_HDCP_DUAL_P2_BASE + 0x43) 5027 #define REG_HDCP_DUAL_P2_22_L (REG_HDCP_DUAL_P2_BASE + 0x44) 5028 #define REG_HDCP_DUAL_P2_22_H (REG_HDCP_DUAL_P2_BASE + 0x45) 5029 #define REG_HDCP_DUAL_P2_23_L (REG_HDCP_DUAL_P2_BASE + 0x46) 5030 #define REG_HDCP_DUAL_P2_23_H (REG_HDCP_DUAL_P2_BASE + 0x47) 5031 #define REG_HDCP_DUAL_P2_24_L (REG_HDCP_DUAL_P2_BASE + 0x48) 5032 #define REG_HDCP_DUAL_P2_24_H (REG_HDCP_DUAL_P2_BASE + 0x49) 5033 #define REG_HDCP_DUAL_P2_25_L (REG_HDCP_DUAL_P2_BASE + 0x4A) 5034 #define REG_HDCP_DUAL_P2_25_H (REG_HDCP_DUAL_P2_BASE + 0x4B) 5035 #define REG_HDCP_DUAL_P2_26_L (REG_HDCP_DUAL_P2_BASE + 0x4C) 5036 #define REG_HDCP_DUAL_P2_26_H (REG_HDCP_DUAL_P2_BASE + 0x4D) 5037 #define REG_HDCP_DUAL_P2_27_L (REG_HDCP_DUAL_P2_BASE + 0x4E) 5038 #define REG_HDCP_DUAL_P2_27_H (REG_HDCP_DUAL_P2_BASE + 0x4F) 5039 #define REG_HDCP_DUAL_P2_28_L (REG_HDCP_DUAL_P2_BASE + 0x50) 5040 #define REG_HDCP_DUAL_P2_28_H (REG_HDCP_DUAL_P2_BASE + 0x51) 5041 #define REG_HDCP_DUAL_P2_29_L (REG_HDCP_DUAL_P2_BASE + 0x52) 5042 #define REG_HDCP_DUAL_P2_29_H (REG_HDCP_DUAL_P2_BASE + 0x53) 5043 #define REG_HDCP_DUAL_P2_2A_L (REG_HDCP_DUAL_P2_BASE + 0x54) 5044 #define REG_HDCP_DUAL_P2_2A_H (REG_HDCP_DUAL_P2_BASE + 0x55) 5045 #define REG_HDCP_DUAL_P2_2B_L (REG_HDCP_DUAL_P2_BASE + 0x56) 5046 #define REG_HDCP_DUAL_P2_2B_H (REG_HDCP_DUAL_P2_BASE + 0x57) 5047 #define REG_HDCP_DUAL_P2_2C_L (REG_HDCP_DUAL_P2_BASE + 0x58) 5048 #define REG_HDCP_DUAL_P2_2C_H (REG_HDCP_DUAL_P2_BASE + 0x59) 5049 #define REG_HDCP_DUAL_P2_2D_L (REG_HDCP_DUAL_P2_BASE + 0x5A) 5050 #define REG_HDCP_DUAL_P2_2D_H (REG_HDCP_DUAL_P2_BASE + 0x5B) 5051 #define REG_HDCP_DUAL_P2_2E_L (REG_HDCP_DUAL_P2_BASE + 0x5C) 5052 #define REG_HDCP_DUAL_P2_2E_H (REG_HDCP_DUAL_P2_BASE + 0x5D) 5053 #define REG_HDCP_DUAL_P2_2F_L (REG_HDCP_DUAL_P2_BASE + 0x5E) 5054 #define REG_HDCP_DUAL_P2_2F_H (REG_HDCP_DUAL_P2_BASE + 0x5F) 5055 #define REG_HDCP_DUAL_P2_30_L (REG_HDCP_DUAL_P2_BASE + 0x60) 5056 #define REG_HDCP_DUAL_P2_30_H (REG_HDCP_DUAL_P2_BASE + 0x61) 5057 #define REG_HDCP_DUAL_P2_31_L (REG_HDCP_DUAL_P2_BASE + 0x62) 5058 #define REG_HDCP_DUAL_P2_31_H (REG_HDCP_DUAL_P2_BASE + 0x63) 5059 #define REG_HDCP_DUAL_P2_32_L (REG_HDCP_DUAL_P2_BASE + 0x64) 5060 #define REG_HDCP_DUAL_P2_32_H (REG_HDCP_DUAL_P2_BASE + 0x65) 5061 #define REG_HDCP_DUAL_P2_33_L (REG_HDCP_DUAL_P2_BASE + 0x66) 5062 #define REG_HDCP_DUAL_P2_33_H (REG_HDCP_DUAL_P2_BASE + 0x67) 5063 #define REG_HDCP_DUAL_P2_34_L (REG_HDCP_DUAL_P2_BASE + 0x68) 5064 #define REG_HDCP_DUAL_P2_34_H (REG_HDCP_DUAL_P2_BASE + 0x69) 5065 #define REG_HDCP_DUAL_P2_35_L (REG_HDCP_DUAL_P2_BASE + 0x6A) 5066 #define REG_HDCP_DUAL_P2_35_H (REG_HDCP_DUAL_P2_BASE + 0x6B) 5067 #define REG_HDCP_DUAL_P2_36_L (REG_HDCP_DUAL_P2_BASE + 0x6C) 5068 #define REG_HDCP_DUAL_P2_36_H (REG_HDCP_DUAL_P2_BASE + 0x6D) 5069 #define REG_HDCP_DUAL_P2_37_L (REG_HDCP_DUAL_P2_BASE + 0x6E) 5070 #define REG_HDCP_DUAL_P2_37_H (REG_HDCP_DUAL_P2_BASE + 0x6F) 5071 #define REG_HDCP_DUAL_P2_38_L (REG_HDCP_DUAL_P2_BASE + 0x70) 5072 #define REG_HDCP_DUAL_P2_38_H (REG_HDCP_DUAL_P2_BASE + 0x71) 5073 #define REG_HDCP_DUAL_P2_39_L (REG_HDCP_DUAL_P2_BASE + 0x72) 5074 #define REG_HDCP_DUAL_P2_39_H (REG_HDCP_DUAL_P2_BASE + 0x73) 5075 #define REG_HDCP_DUAL_P2_3A_L (REG_HDCP_DUAL_P2_BASE + 0x74) 5076 #define REG_HDCP_DUAL_P2_3A_H (REG_HDCP_DUAL_P2_BASE + 0x75) 5077 #define REG_HDCP_DUAL_P2_3B_L (REG_HDCP_DUAL_P2_BASE + 0x76) 5078 #define REG_HDCP_DUAL_P2_3B_H (REG_HDCP_DUAL_P2_BASE + 0x77) 5079 #define REG_HDCP_DUAL_P2_3C_L (REG_HDCP_DUAL_P2_BASE + 0x78) 5080 #define REG_HDCP_DUAL_P2_3C_H (REG_HDCP_DUAL_P2_BASE + 0x79) 5081 #define REG_HDCP_DUAL_P2_3D_L (REG_HDCP_DUAL_P2_BASE + 0x7A) 5082 #define REG_HDCP_DUAL_P2_3D_H (REG_HDCP_DUAL_P2_BASE + 0x7B) 5083 #define REG_HDCP_DUAL_P2_3E_L (REG_HDCP_DUAL_P2_BASE + 0x7C) 5084 #define REG_HDCP_DUAL_P2_3E_H (REG_HDCP_DUAL_P2_BASE + 0x7D) 5085 #define REG_HDCP_DUAL_P2_3F_L (REG_HDCP_DUAL_P2_BASE + 0x7E) 5086 #define REG_HDCP_DUAL_P2_3F_H (REG_HDCP_DUAL_P2_BASE + 0x7F) 5087 #define REG_HDCP_DUAL_P2_40_L (REG_HDCP_DUAL_P2_BASE + 0x80) 5088 #define REG_HDCP_DUAL_P2_40_H (REG_HDCP_DUAL_P2_BASE + 0x81) 5089 #define REG_HDCP_DUAL_P2_41_L (REG_HDCP_DUAL_P2_BASE + 0x82) 5090 #define REG_HDCP_DUAL_P2_41_H (REG_HDCP_DUAL_P2_BASE + 0x83) 5091 #define REG_HDCP_DUAL_P2_42_L (REG_HDCP_DUAL_P2_BASE + 0x84) 5092 #define REG_HDCP_DUAL_P2_42_H (REG_HDCP_DUAL_P2_BASE + 0x85) 5093 #define REG_HDCP_DUAL_P2_43_L (REG_HDCP_DUAL_P2_BASE + 0x86) 5094 #define REG_HDCP_DUAL_P2_43_H (REG_HDCP_DUAL_P2_BASE + 0x87) 5095 #define REG_HDCP_DUAL_P2_44_L (REG_HDCP_DUAL_P2_BASE + 0x88) 5096 #define REG_HDCP_DUAL_P2_44_H (REG_HDCP_DUAL_P2_BASE + 0x89) 5097 #define REG_HDCP_DUAL_P2_45_L (REG_HDCP_DUAL_P2_BASE + 0x8A) 5098 #define REG_HDCP_DUAL_P2_45_H (REG_HDCP_DUAL_P2_BASE + 0x8B) 5099 #define REG_HDCP_DUAL_P2_46_L (REG_HDCP_DUAL_P2_BASE + 0x8C) 5100 #define REG_HDCP_DUAL_P2_46_H (REG_HDCP_DUAL_P2_BASE + 0x8D) 5101 #define REG_HDCP_DUAL_P2_47_L (REG_HDCP_DUAL_P2_BASE + 0x8E) 5102 #define REG_HDCP_DUAL_P2_47_H (REG_HDCP_DUAL_P2_BASE + 0x8F) 5103 #define REG_HDCP_DUAL_P2_48_L (REG_HDCP_DUAL_P2_BASE + 0x90) 5104 #define REG_HDCP_DUAL_P2_48_H (REG_HDCP_DUAL_P2_BASE + 0x91) 5105 #define REG_HDCP_DUAL_P2_49_L (REG_HDCP_DUAL_P2_BASE + 0x92) 5106 #define REG_HDCP_DUAL_P2_49_H (REG_HDCP_DUAL_P2_BASE + 0x93) 5107 #define REG_HDCP_DUAL_P2_4A_L (REG_HDCP_DUAL_P2_BASE + 0x94) 5108 #define REG_HDCP_DUAL_P2_4A_H (REG_HDCP_DUAL_P2_BASE + 0x95) 5109 #define REG_HDCP_DUAL_P2_4B_L (REG_HDCP_DUAL_P2_BASE + 0x96) 5110 #define REG_HDCP_DUAL_P2_4B_H (REG_HDCP_DUAL_P2_BASE + 0x97) 5111 #define REG_HDCP_DUAL_P2_4C_L (REG_HDCP_DUAL_P2_BASE + 0x98) 5112 #define REG_HDCP_DUAL_P2_4C_H (REG_HDCP_DUAL_P2_BASE + 0x99) 5113 #define REG_HDCP_DUAL_P2_4D_L (REG_HDCP_DUAL_P2_BASE + 0x9A) 5114 #define REG_HDCP_DUAL_P2_4D_H (REG_HDCP_DUAL_P2_BASE + 0x9B) 5115 #define REG_HDCP_DUAL_P2_4E_L (REG_HDCP_DUAL_P2_BASE + 0x9C) 5116 #define REG_HDCP_DUAL_P2_4E_H (REG_HDCP_DUAL_P2_BASE + 0x9D) 5117 #define REG_HDCP_DUAL_P2_4F_L (REG_HDCP_DUAL_P2_BASE + 0x9E) 5118 #define REG_HDCP_DUAL_P2_4F_H (REG_HDCP_DUAL_P2_BASE + 0x9F) 5119 #define REG_HDCP_DUAL_P2_50_L (REG_HDCP_DUAL_P2_BASE + 0xA0) 5120 #define REG_HDCP_DUAL_P2_50_H (REG_HDCP_DUAL_P2_BASE + 0xA1) 5121 #define REG_HDCP_DUAL_P2_51_L (REG_HDCP_DUAL_P2_BASE + 0xA2) 5122 #define REG_HDCP_DUAL_P2_51_H (REG_HDCP_DUAL_P2_BASE + 0xA3) 5123 #define REG_HDCP_DUAL_P2_52_L (REG_HDCP_DUAL_P2_BASE + 0xA4) 5124 #define REG_HDCP_DUAL_P2_52_H (REG_HDCP_DUAL_P2_BASE + 0xA5) 5125 #define REG_HDCP_DUAL_P2_53_L (REG_HDCP_DUAL_P2_BASE + 0xA6) 5126 #define REG_HDCP_DUAL_P2_53_H (REG_HDCP_DUAL_P2_BASE + 0xA7) 5127 #define REG_HDCP_DUAL_P2_54_L (REG_HDCP_DUAL_P2_BASE + 0xA8) 5128 #define REG_HDCP_DUAL_P2_54_H (REG_HDCP_DUAL_P2_BASE + 0xA9) 5129 #define REG_HDCP_DUAL_P2_55_L (REG_HDCP_DUAL_P2_BASE + 0xAA) 5130 #define REG_HDCP_DUAL_P2_55_H (REG_HDCP_DUAL_P2_BASE + 0xAB) 5131 #define REG_HDCP_DUAL_P2_56_L (REG_HDCP_DUAL_P2_BASE + 0xAC) 5132 #define REG_HDCP_DUAL_P2_56_H (REG_HDCP_DUAL_P2_BASE + 0xAD) 5133 #define REG_HDCP_DUAL_P2_57_L (REG_HDCP_DUAL_P2_BASE + 0xAE) 5134 #define REG_HDCP_DUAL_P2_57_H (REG_HDCP_DUAL_P2_BASE + 0xAF) 5135 #define REG_HDCP_DUAL_P2_58_L (REG_HDCP_DUAL_P2_BASE + 0xB0) 5136 #define REG_HDCP_DUAL_P2_58_H (REG_HDCP_DUAL_P2_BASE + 0xB1) 5137 #define REG_HDCP_DUAL_P2_59_L (REG_HDCP_DUAL_P2_BASE + 0xB2) 5138 #define REG_HDCP_DUAL_P2_59_H (REG_HDCP_DUAL_P2_BASE + 0xB3) 5139 #define REG_HDCP_DUAL_P2_5A_L (REG_HDCP_DUAL_P2_BASE + 0xB4) 5140 #define REG_HDCP_DUAL_P2_5A_H (REG_HDCP_DUAL_P2_BASE + 0xB5) 5141 #define REG_HDCP_DUAL_P2_5B_L (REG_HDCP_DUAL_P2_BASE + 0xB6) 5142 #define REG_HDCP_DUAL_P2_5B_H (REG_HDCP_DUAL_P2_BASE + 0xB7) 5143 #define REG_HDCP_DUAL_P2_5C_L (REG_HDCP_DUAL_P2_BASE + 0xB8) 5144 #define REG_HDCP_DUAL_P2_5C_H (REG_HDCP_DUAL_P2_BASE + 0xB9) 5145 #define REG_HDCP_DUAL_P2_5D_L (REG_HDCP_DUAL_P2_BASE + 0xBA) 5146 #define REG_HDCP_DUAL_P2_5D_H (REG_HDCP_DUAL_P2_BASE + 0xBB) 5147 #define REG_HDCP_DUAL_P2_5E_L (REG_HDCP_DUAL_P2_BASE + 0xBC) 5148 #define REG_HDCP_DUAL_P2_5E_H (REG_HDCP_DUAL_P2_BASE + 0xBD) 5149 #define REG_HDCP_DUAL_P2_5F_L (REG_HDCP_DUAL_P2_BASE + 0xBE) 5150 #define REG_HDCP_DUAL_P2_5F_H (REG_HDCP_DUAL_P2_BASE + 0xBF) 5151 #define REG_HDCP_DUAL_P2_60_L (REG_HDCP_DUAL_P2_BASE + 0xC0) 5152 #define REG_HDCP_DUAL_P2_60_H (REG_HDCP_DUAL_P2_BASE + 0xC1) 5153 #define REG_HDCP_DUAL_P2_61_L (REG_HDCP_DUAL_P2_BASE + 0xC2) 5154 #define REG_HDCP_DUAL_P2_61_H (REG_HDCP_DUAL_P2_BASE + 0xC3) 5155 #define REG_HDCP_DUAL_P2_62_L (REG_HDCP_DUAL_P2_BASE + 0xC4) 5156 #define REG_HDCP_DUAL_P2_62_H (REG_HDCP_DUAL_P2_BASE + 0xC5) 5157 #define REG_HDCP_DUAL_P2_63_L (REG_HDCP_DUAL_P2_BASE + 0xC6) 5158 #define REG_HDCP_DUAL_P2_63_H (REG_HDCP_DUAL_P2_BASE + 0xC7) 5159 #define REG_HDCP_DUAL_P2_64_L (REG_HDCP_DUAL_P2_BASE + 0xC8) 5160 #define REG_HDCP_DUAL_P2_64_H (REG_HDCP_DUAL_P2_BASE + 0xC9) 5161 #define REG_HDCP_DUAL_P2_65_L (REG_HDCP_DUAL_P2_BASE + 0xCA) 5162 #define REG_HDCP_DUAL_P2_65_H (REG_HDCP_DUAL_P2_BASE + 0xCB) 5163 #define REG_HDCP_DUAL_P2_66_L (REG_HDCP_DUAL_P2_BASE + 0xCC) 5164 #define REG_HDCP_DUAL_P2_66_H (REG_HDCP_DUAL_P2_BASE + 0xCD) 5165 #define REG_HDCP_DUAL_P2_67_L (REG_HDCP_DUAL_P2_BASE + 0xCE) 5166 #define REG_HDCP_DUAL_P2_67_H (REG_HDCP_DUAL_P2_BASE + 0xCF) 5167 #define REG_HDCP_DUAL_P2_68_L (REG_HDCP_DUAL_P2_BASE + 0xD0) 5168 #define REG_HDCP_DUAL_P2_68_H (REG_HDCP_DUAL_P2_BASE + 0xD1) 5169 5170 // DVI_DTOP_DUAL_P3 5171 #define REG_DVI_DTOP_DUAL_P3_00_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x00) 5172 #define REG_DVI_DTOP_DUAL_P3_00_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x01) 5173 #define REG_DVI_DTOP_DUAL_P3_01_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x02) 5174 #define REG_DVI_DTOP_DUAL_P3_01_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x03) 5175 #define REG_DVI_DTOP_DUAL_P3_02_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x04) 5176 #define REG_DVI_DTOP_DUAL_P3_02_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x05) 5177 #define REG_DVI_DTOP_DUAL_P3_03_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x06) 5178 #define REG_DVI_DTOP_DUAL_P3_03_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x07) 5179 #define REG_DVI_DTOP_DUAL_P3_04_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x08) 5180 #define REG_DVI_DTOP_DUAL_P3_04_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x09) 5181 #define REG_DVI_DTOP_DUAL_P3_05_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x0A) 5182 #define REG_DVI_DTOP_DUAL_P3_05_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x0B) 5183 #define REG_DVI_DTOP_DUAL_P3_06_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x0C) 5184 #define REG_DVI_DTOP_DUAL_P3_06_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x0D) 5185 #define REG_DVI_DTOP_DUAL_P3_07_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x0E) 5186 #define REG_DVI_DTOP_DUAL_P3_07_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x0F) 5187 #define REG_DVI_DTOP_DUAL_P3_08_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x10) 5188 #define REG_DVI_DTOP_DUAL_P3_08_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x11) 5189 #define REG_DVI_DTOP_DUAL_P3_09_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x12) 5190 #define REG_DVI_DTOP_DUAL_P3_09_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x13) 5191 #define REG_DVI_DTOP_DUAL_P3_0A_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x14) 5192 #define REG_DVI_DTOP_DUAL_P3_0A_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x15) 5193 #define REG_DVI_DTOP_DUAL_P3_0B_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x16) 5194 #define REG_DVI_DTOP_DUAL_P3_0B_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x17) 5195 #define REG_DVI_DTOP_DUAL_P3_0C_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x18) 5196 #define REG_DVI_DTOP_DUAL_P3_0C_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x19) 5197 #define REG_DVI_DTOP_DUAL_P3_0D_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x1A) 5198 #define REG_DVI_DTOP_DUAL_P3_0D_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x1B) 5199 #define REG_DVI_DTOP_DUAL_P3_0E_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x1C) 5200 #define REG_DVI_DTOP_DUAL_P3_0E_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x1D) 5201 #define REG_DVI_DTOP_DUAL_P3_0F_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x1E) 5202 #define REG_DVI_DTOP_DUAL_P3_0F_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x1F) 5203 #define REG_DVI_DTOP_DUAL_P3_10_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x20) 5204 #define REG_DVI_DTOP_DUAL_P3_10_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x21) 5205 #define REG_DVI_DTOP_DUAL_P3_11_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x22) 5206 #define REG_DVI_DTOP_DUAL_P3_11_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x23) 5207 #define REG_DVI_DTOP_DUAL_P3_12_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x24) 5208 #define REG_DVI_DTOP_DUAL_P3_12_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x25) 5209 #define REG_DVI_DTOP_DUAL_P3_13_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x26) 5210 #define REG_DVI_DTOP_DUAL_P3_13_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x27) 5211 #define REG_DVI_DTOP_DUAL_P3_14_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x28) 5212 #define REG_DVI_DTOP_DUAL_P3_14_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x29) 5213 #define REG_DVI_DTOP_DUAL_P3_15_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x2A) 5214 #define REG_DVI_DTOP_DUAL_P3_15_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x2B) 5215 #define REG_DVI_DTOP_DUAL_P3_16_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x2C) 5216 #define REG_DVI_DTOP_DUAL_P3_16_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x2D) 5217 #define REG_DVI_DTOP_DUAL_P3_17_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x2E) 5218 #define REG_DVI_DTOP_DUAL_P3_17_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x2F) 5219 #define REG_DVI_DTOP_DUAL_P3_18_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x30) 5220 #define REG_DVI_DTOP_DUAL_P3_18_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x31) 5221 #define REG_DVI_DTOP_DUAL_P3_19_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x32) 5222 #define REG_DVI_DTOP_DUAL_P3_19_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x33) 5223 #define REG_DVI_DTOP_DUAL_P3_1A_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x34) 5224 #define REG_DVI_DTOP_DUAL_P3_1A_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x35) 5225 #define REG_DVI_DTOP_DUAL_P3_1B_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x36) 5226 #define REG_DVI_DTOP_DUAL_P3_1B_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x37) 5227 #define REG_DVI_DTOP_DUAL_P3_1C_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x38) 5228 #define REG_DVI_DTOP_DUAL_P3_1C_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x39) 5229 #define REG_DVI_DTOP_DUAL_P3_1D_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x3A) 5230 #define REG_DVI_DTOP_DUAL_P3_1D_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x3B) 5231 #define REG_DVI_DTOP_DUAL_P3_1E_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x3C) 5232 #define REG_DVI_DTOP_DUAL_P3_1E_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x3D) 5233 #define REG_DVI_DTOP_DUAL_P3_1F_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x3E) 5234 #define REG_DVI_DTOP_DUAL_P3_1F_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x3F) 5235 #define REG_DVI_DTOP_DUAL_P3_20_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x40) 5236 #define REG_DVI_DTOP_DUAL_P3_20_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x41) 5237 #define REG_DVI_DTOP_DUAL_P3_21_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x42) 5238 #define REG_DVI_DTOP_DUAL_P3_21_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x43) 5239 #define REG_DVI_DTOP_DUAL_P3_22_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x44) 5240 #define REG_DVI_DTOP_DUAL_P3_22_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x45) 5241 #define REG_DVI_DTOP_DUAL_P3_23_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x46) 5242 #define REG_DVI_DTOP_DUAL_P3_23_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x47) 5243 #define REG_DVI_DTOP_DUAL_P3_24_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x48) 5244 #define REG_DVI_DTOP_DUAL_P3_24_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x49) 5245 #define REG_DVI_DTOP_DUAL_P3_25_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x4A) 5246 #define REG_DVI_DTOP_DUAL_P3_25_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x4B) 5247 #define REG_DVI_DTOP_DUAL_P3_26_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x4C) 5248 #define REG_DVI_DTOP_DUAL_P3_26_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x4D) 5249 #define REG_DVI_DTOP_DUAL_P3_27_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x4E) 5250 #define REG_DVI_DTOP_DUAL_P3_27_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x4F) 5251 #define REG_DVI_DTOP_DUAL_P3_28_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x50) 5252 #define REG_DVI_DTOP_DUAL_P3_28_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x51) 5253 #define REG_DVI_DTOP_DUAL_P3_29_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x52) 5254 #define REG_DVI_DTOP_DUAL_P3_29_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x53) 5255 #define REG_DVI_DTOP_DUAL_P3_2A_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x54) 5256 #define REG_DVI_DTOP_DUAL_P3_2A_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x55) 5257 #define REG_DVI_DTOP_DUAL_P3_2B_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x56) 5258 #define REG_DVI_DTOP_DUAL_P3_2B_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x57) 5259 #define REG_DVI_DTOP_DUAL_P3_2C_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x58) 5260 #define REG_DVI_DTOP_DUAL_P3_2C_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x59) 5261 #define REG_DVI_DTOP_DUAL_P3_2D_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x5A) 5262 #define REG_DVI_DTOP_DUAL_P3_2D_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x5B) 5263 #define REG_DVI_DTOP_DUAL_P3_2E_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x5C) 5264 #define REG_DVI_DTOP_DUAL_P3_2E_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x5D) 5265 #define REG_DVI_DTOP_DUAL_P3_2F_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x5E) 5266 #define REG_DVI_DTOP_DUAL_P3_2F_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x5F) 5267 #define REG_DVI_DTOP_DUAL_P3_30_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x60) 5268 #define REG_DVI_DTOP_DUAL_P3_30_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x61) 5269 #define REG_DVI_DTOP_DUAL_P3_31_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x62) 5270 #define REG_DVI_DTOP_DUAL_P3_31_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x63) 5271 #define REG_DVI_DTOP_DUAL_P3_32_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x64) 5272 #define REG_DVI_DTOP_DUAL_P3_32_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x65) 5273 #define REG_DVI_DTOP_DUAL_P3_33_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x66) 5274 #define REG_DVI_DTOP_DUAL_P3_33_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x67) 5275 #define REG_DVI_DTOP_DUAL_P3_34_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x68) 5276 #define REG_DVI_DTOP_DUAL_P3_34_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x69) 5277 #define REG_DVI_DTOP_DUAL_P3_35_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x6A) 5278 #define REG_DVI_DTOP_DUAL_P3_35_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x6B) 5279 #define REG_DVI_DTOP_DUAL_P3_36_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x6C) 5280 #define REG_DVI_DTOP_DUAL_P3_36_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x6D) 5281 #define REG_DVI_DTOP_DUAL_P3_37_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x6E) 5282 #define REG_DVI_DTOP_DUAL_P3_37_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x6F) 5283 #define REG_DVI_DTOP_DUAL_P3_38_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x70) 5284 #define REG_DVI_DTOP_DUAL_P3_38_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x71) 5285 #define REG_DVI_DTOP_DUAL_P3_39_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x72) 5286 #define REG_DVI_DTOP_DUAL_P3_39_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x73) 5287 #define REG_DVI_DTOP_DUAL_P3_3A_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x74) 5288 #define REG_DVI_DTOP_DUAL_P3_3A_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x75) 5289 #define REG_DVI_DTOP_DUAL_P3_3B_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x76) 5290 #define REG_DVI_DTOP_DUAL_P3_3B_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x77) 5291 #define REG_DVI_DTOP_DUAL_P3_3C_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x78) 5292 #define REG_DVI_DTOP_DUAL_P3_3C_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x79) 5293 #define REG_DVI_DTOP_DUAL_P3_3D_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x7A) 5294 #define REG_DVI_DTOP_DUAL_P3_3D_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x7B) 5295 #define REG_DVI_DTOP_DUAL_P3_3E_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x7C) 5296 #define REG_DVI_DTOP_DUAL_P3_3E_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x7D) 5297 #define REG_DVI_DTOP_DUAL_P3_3F_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x7E) 5298 #define REG_DVI_DTOP_DUAL_P3_3F_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x7F) 5299 #define REG_DVI_DTOP_DUAL_P3_40_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x80) 5300 #define REG_DVI_DTOP_DUAL_P3_40_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x81) 5301 #define REG_DVI_DTOP_DUAL_P3_41_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x82) 5302 #define REG_DVI_DTOP_DUAL_P3_41_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x83) 5303 #define REG_DVI_DTOP_DUAL_P3_42_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x84) 5304 #define REG_DVI_DTOP_DUAL_P3_42_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x85) 5305 #define REG_DVI_DTOP_DUAL_P3_43_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x86) 5306 #define REG_DVI_DTOP_DUAL_P3_43_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x87) 5307 #define REG_DVI_DTOP_DUAL_P3_44_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x88) 5308 #define REG_DVI_DTOP_DUAL_P3_44_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x89) 5309 #define REG_DVI_DTOP_DUAL_P3_45_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x8A) 5310 #define REG_DVI_DTOP_DUAL_P3_45_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x8B) 5311 #define REG_DVI_DTOP_DUAL_P3_46_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x8C) 5312 #define REG_DVI_DTOP_DUAL_P3_46_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x8D) 5313 #define REG_DVI_DTOP_DUAL_P3_47_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x8E) 5314 #define REG_DVI_DTOP_DUAL_P3_47_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x8F) 5315 #define REG_DVI_DTOP_DUAL_P3_48_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x90) 5316 #define REG_DVI_DTOP_DUAL_P3_48_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x91) 5317 #define REG_DVI_DTOP_DUAL_P3_49_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x92) 5318 #define REG_DVI_DTOP_DUAL_P3_49_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x93) 5319 #define REG_DVI_DTOP_DUAL_P3_4A_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x94) 5320 #define REG_DVI_DTOP_DUAL_P3_4A_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x95) 5321 #define REG_DVI_DTOP_DUAL_P3_4B_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x96) 5322 #define REG_DVI_DTOP_DUAL_P3_4B_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x97) 5323 #define REG_DVI_DTOP_DUAL_P3_4C_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x98) 5324 #define REG_DVI_DTOP_DUAL_P3_4C_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x99) 5325 #define REG_DVI_DTOP_DUAL_P3_4D_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x9A) 5326 #define REG_DVI_DTOP_DUAL_P3_4D_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x9B) 5327 #define REG_DVI_DTOP_DUAL_P3_4E_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x9C) 5328 #define REG_DVI_DTOP_DUAL_P3_4E_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x9D) 5329 #define REG_DVI_DTOP_DUAL_P3_4F_L (REG_DVI_DTOP_DUAL_P3_BASE + 0x9E) 5330 #define REG_DVI_DTOP_DUAL_P3_4F_H (REG_DVI_DTOP_DUAL_P3_BASE + 0x9F) 5331 #define REG_DVI_DTOP_DUAL_P3_50_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xA0) 5332 #define REG_DVI_DTOP_DUAL_P3_50_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xA1) 5333 #define REG_DVI_DTOP_DUAL_P3_51_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xA2) 5334 #define REG_DVI_DTOP_DUAL_P3_51_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xA3) 5335 #define REG_DVI_DTOP_DUAL_P3_52_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xA4) 5336 #define REG_DVI_DTOP_DUAL_P3_52_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xA5) 5337 #define REG_DVI_DTOP_DUAL_P3_53_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xA6) 5338 #define REG_DVI_DTOP_DUAL_P3_53_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xA7) 5339 #define REG_DVI_DTOP_DUAL_P3_54_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xA8) 5340 #define REG_DVI_DTOP_DUAL_P3_54_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xA9) 5341 #define REG_DVI_DTOP_DUAL_P3_55_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xAA) 5342 #define REG_DVI_DTOP_DUAL_P3_55_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xAB) 5343 #define REG_DVI_DTOP_DUAL_P3_56_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xAC) 5344 #define REG_DVI_DTOP_DUAL_P3_56_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xAD) 5345 #define REG_DVI_DTOP_DUAL_P3_57_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xAE) 5346 #define REG_DVI_DTOP_DUAL_P3_57_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xAF) 5347 #define REG_DVI_DTOP_DUAL_P3_58_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xB0) 5348 #define REG_DVI_DTOP_DUAL_P3_58_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xB1) 5349 #define REG_DVI_DTOP_DUAL_P3_59_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xB2) 5350 #define REG_DVI_DTOP_DUAL_P3_59_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xB3) 5351 #define REG_DVI_DTOP_DUAL_P3_5A_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xB4) 5352 #define REG_DVI_DTOP_DUAL_P3_5A_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xB5) 5353 #define REG_DVI_DTOP_DUAL_P3_5B_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xB6) 5354 #define REG_DVI_DTOP_DUAL_P3_5B_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xB7) 5355 #define REG_DVI_DTOP_DUAL_P3_5C_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xB8) 5356 #define REG_DVI_DTOP_DUAL_P3_5C_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xB9) 5357 #define REG_DVI_DTOP_DUAL_P3_5D_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xBA) 5358 #define REG_DVI_DTOP_DUAL_P3_5D_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xBB) 5359 #define REG_DVI_DTOP_DUAL_P3_5E_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xBC) 5360 #define REG_DVI_DTOP_DUAL_P3_5E_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xBD) 5361 #define REG_DVI_DTOP_DUAL_P3_5F_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xBE) 5362 #define REG_DVI_DTOP_DUAL_P3_5F_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xBF) 5363 #define REG_DVI_DTOP_DUAL_P3_60_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC0) 5364 #define REG_DVI_DTOP_DUAL_P3_60_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xC1) 5365 #define REG_DVI_DTOP_DUAL_P3_61_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC2) 5366 #define REG_DVI_DTOP_DUAL_P3_61_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xC3) 5367 #define REG_DVI_DTOP_DUAL_P3_62_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC4) 5368 #define REG_DVI_DTOP_DUAL_P3_62_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xC5) 5369 #define REG_DVI_DTOP_DUAL_P3_63_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC6) 5370 #define REG_DVI_DTOP_DUAL_P3_63_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xC7) 5371 #define REG_DVI_DTOP_DUAL_P3_64_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xC8) 5372 #define REG_DVI_DTOP_DUAL_P3_64_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xC9) 5373 #define REG_DVI_DTOP_DUAL_P3_65_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xCA) 5374 #define REG_DVI_DTOP_DUAL_P3_65_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xCB) 5375 #define REG_DVI_DTOP_DUAL_P3_66_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xCC) 5376 #define REG_DVI_DTOP_DUAL_P3_66_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xCD) 5377 #define REG_DVI_DTOP_DUAL_P3_67_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xCE) 5378 #define REG_DVI_DTOP_DUAL_P3_67_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xCF) 5379 #define REG_DVI_DTOP_DUAL_P3_68_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xD0) 5380 #define REG_DVI_DTOP_DUAL_P3_68_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xD1) 5381 #define REG_DVI_DTOP_DUAL_P3_69_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xD2) 5382 #define REG_DVI_DTOP_DUAL_P3_69_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xD3) 5383 #define REG_DVI_DTOP_DUAL_P3_6A_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xD4) 5384 #define REG_DVI_DTOP_DUAL_P3_6A_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xD5) 5385 #define REG_DVI_DTOP_DUAL_P3_6B_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xD6) 5386 #define REG_DVI_DTOP_DUAL_P3_6B_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xD7) 5387 #define REG_DVI_DTOP_DUAL_P3_6C_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xD8) 5388 #define REG_DVI_DTOP_DUAL_P3_6C_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xD9) 5389 #define REG_DVI_DTOP_DUAL_P3_6D_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xDA) 5390 #define REG_DVI_DTOP_DUAL_P3_6D_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xDB) 5391 #define REG_DVI_DTOP_DUAL_P3_6E_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xDC) 5392 #define REG_DVI_DTOP_DUAL_P3_6E_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xDD) 5393 #define REG_DVI_DTOP_DUAL_P3_6F_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xDE) 5394 #define REG_DVI_DTOP_DUAL_P3_6F_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xDF) 5395 #define REG_DVI_DTOP_DUAL_P3_70_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xE0) 5396 #define REG_DVI_DTOP_DUAL_P3_70_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xE1) 5397 #define REG_DVI_DTOP_DUAL_P3_71_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xE2) 5398 #define REG_DVI_DTOP_DUAL_P3_71_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xE3) 5399 #define REG_DVI_DTOP_DUAL_P3_72_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xE4) 5400 #define REG_DVI_DTOP_DUAL_P3_72_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xE5) 5401 #define REG_DVI_DTOP_DUAL_P3_73_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xE6) 5402 #define REG_DVI_DTOP_DUAL_P3_73_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xE7) 5403 #define REG_DVI_DTOP_DUAL_P3_74_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xE8) 5404 #define REG_DVI_DTOP_DUAL_P3_74_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xE9) 5405 #define REG_DVI_DTOP_DUAL_P3_75_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xEA) 5406 #define REG_DVI_DTOP_DUAL_P3_75_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xEB) 5407 #define REG_DVI_DTOP_DUAL_P3_76_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xEC) 5408 #define REG_DVI_DTOP_DUAL_P3_76_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xED) 5409 #define REG_DVI_DTOP_DUAL_P3_77_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xEE) 5410 #define REG_DVI_DTOP_DUAL_P3_77_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xEF) 5411 #define REG_DVI_DTOP_DUAL_P3_78_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xF0) 5412 #define REG_DVI_DTOP_DUAL_P3_78_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xF1) 5413 #define REG_DVI_DTOP_DUAL_P3_79_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xF2) 5414 #define REG_DVI_DTOP_DUAL_P3_79_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xF3) 5415 #define REG_DVI_DTOP_DUAL_P3_7A_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xF4) 5416 #define REG_DVI_DTOP_DUAL_P3_7A_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xF5) 5417 #define REG_DVI_DTOP_DUAL_P3_7B_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xF6) 5418 #define REG_DVI_DTOP_DUAL_P3_7B_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xF7) 5419 #define REG_DVI_DTOP_DUAL_P3_7C_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xF8) 5420 #define REG_DVI_DTOP_DUAL_P3_7C_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xF9) 5421 #define REG_DVI_DTOP_DUAL_P3_7D_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xFA) 5422 #define REG_DVI_DTOP_DUAL_P3_7D_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xFB) 5423 #define REG_DVI_DTOP_DUAL_P3_7E_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xFC) 5424 #define REG_DVI_DTOP_DUAL_P3_7E_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xFD) 5425 #define REG_DVI_DTOP_DUAL_P3_7F_L (REG_DVI_DTOP_DUAL_P3_BASE + 0xFE) 5426 #define REG_DVI_DTOP_DUAL_P3_7F_H (REG_DVI_DTOP_DUAL_P3_BASE + 0xFF) 5427 5428 // DVI_RSV_DUAL_P3 5429 #define REG_DVI_RSV_DUAL_P3_00_L (REG_DVI_RSV_DUAL_P3_BASE + 0x00) 5430 #define REG_DVI_RSV_DUAL_P3_00_H (REG_DVI_RSV_DUAL_P3_BASE + 0x01) 5431 #define REG_DVI_RSV_DUAL_P3_01_L (REG_DVI_RSV_DUAL_P3_BASE + 0x02) 5432 #define REG_DVI_RSV_DUAL_P3_01_H (REG_DVI_RSV_DUAL_P3_BASE + 0x03) 5433 #define REG_DVI_RSV_DUAL_P3_02_L (REG_DVI_RSV_DUAL_P3_BASE + 0x04) 5434 #define REG_DVI_RSV_DUAL_P3_02_H (REG_DVI_RSV_DUAL_P3_BASE + 0x05) 5435 #define REG_DVI_RSV_DUAL_P3_03_L (REG_DVI_RSV_DUAL_P3_BASE + 0x06) 5436 #define REG_DVI_RSV_DUAL_P3_03_H (REG_DVI_RSV_DUAL_P3_BASE + 0x07) 5437 #define REG_DVI_RSV_DUAL_P3_04_L (REG_DVI_RSV_DUAL_P3_BASE + 0x08) 5438 #define REG_DVI_RSV_DUAL_P3_04_H (REG_DVI_RSV_DUAL_P3_BASE + 0x09) 5439 #define REG_DVI_RSV_DUAL_P3_05_L (REG_DVI_RSV_DUAL_P3_BASE + 0x0A) 5440 #define REG_DVI_RSV_DUAL_P3_05_H (REG_DVI_RSV_DUAL_P3_BASE + 0x0B) 5441 #define REG_DVI_RSV_DUAL_P3_06_L (REG_DVI_RSV_DUAL_P3_BASE + 0x0C) 5442 #define REG_DVI_RSV_DUAL_P3_06_H (REG_DVI_RSV_DUAL_P3_BASE + 0x0D) 5443 #define REG_DVI_RSV_DUAL_P3_07_L (REG_DVI_RSV_DUAL_P3_BASE + 0x0E) 5444 #define REG_DVI_RSV_DUAL_P3_07_H (REG_DVI_RSV_DUAL_P3_BASE + 0x0F) 5445 #define REG_DVI_RSV_DUAL_P3_08_L (REG_DVI_RSV_DUAL_P3_BASE + 0x10) 5446 #define REG_DVI_RSV_DUAL_P3_08_H (REG_DVI_RSV_DUAL_P3_BASE + 0x11) 5447 #define REG_DVI_RSV_DUAL_P3_09_L (REG_DVI_RSV_DUAL_P3_BASE + 0x12) 5448 #define REG_DVI_RSV_DUAL_P3_09_H (REG_DVI_RSV_DUAL_P3_BASE + 0x13) 5449 #define REG_DVI_RSV_DUAL_P3_0A_L (REG_DVI_RSV_DUAL_P3_BASE + 0x14) 5450 #define REG_DVI_RSV_DUAL_P3_0A_H (REG_DVI_RSV_DUAL_P3_BASE + 0x15) 5451 #define REG_DVI_RSV_DUAL_P3_0B_L (REG_DVI_RSV_DUAL_P3_BASE + 0x16) 5452 #define REG_DVI_RSV_DUAL_P3_0B_H (REG_DVI_RSV_DUAL_P3_BASE + 0x17) 5453 #define REG_DVI_RSV_DUAL_P3_0C_L (REG_DVI_RSV_DUAL_P3_BASE + 0x18) 5454 #define REG_DVI_RSV_DUAL_P3_0C_H (REG_DVI_RSV_DUAL_P3_BASE + 0x19) 5455 #define REG_DVI_RSV_DUAL_P3_0D_L (REG_DVI_RSV_DUAL_P3_BASE + 0x1A) 5456 #define REG_DVI_RSV_DUAL_P3_0D_H (REG_DVI_RSV_DUAL_P3_BASE + 0x1B) 5457 #define REG_DVI_RSV_DUAL_P3_0E_L (REG_DVI_RSV_DUAL_P3_BASE + 0x1C) 5458 #define REG_DVI_RSV_DUAL_P3_0E_H (REG_DVI_RSV_DUAL_P3_BASE + 0x1D) 5459 #define REG_DVI_RSV_DUAL_P3_0F_L (REG_DVI_RSV_DUAL_P3_BASE + 0x1E) 5460 #define REG_DVI_RSV_DUAL_P3_0F_H (REG_DVI_RSV_DUAL_P3_BASE + 0x1F) 5461 #define REG_DVI_RSV_DUAL_P3_10_L (REG_DVI_RSV_DUAL_P3_BASE + 0x20) 5462 #define REG_DVI_RSV_DUAL_P3_10_H (REG_DVI_RSV_DUAL_P3_BASE + 0x21) 5463 #define REG_DVI_RSV_DUAL_P3_11_L (REG_DVI_RSV_DUAL_P3_BASE + 0x22) 5464 #define REG_DVI_RSV_DUAL_P3_11_H (REG_DVI_RSV_DUAL_P3_BASE + 0x23) 5465 #define REG_DVI_RSV_DUAL_P3_12_L (REG_DVI_RSV_DUAL_P3_BASE + 0x24) 5466 #define REG_DVI_RSV_DUAL_P3_12_H (REG_DVI_RSV_DUAL_P3_BASE + 0x25) 5467 #define REG_DVI_RSV_DUAL_P3_13_L (REG_DVI_RSV_DUAL_P3_BASE + 0x26) 5468 #define REG_DVI_RSV_DUAL_P3_13_H (REG_DVI_RSV_DUAL_P3_BASE + 0x27) 5469 #define REG_DVI_RSV_DUAL_P3_14_L (REG_DVI_RSV_DUAL_P3_BASE + 0x28) 5470 #define REG_DVI_RSV_DUAL_P3_14_H (REG_DVI_RSV_DUAL_P3_BASE + 0x29) 5471 #define REG_DVI_RSV_DUAL_P3_15_L (REG_DVI_RSV_DUAL_P3_BASE + 0x2A) 5472 #define REG_DVI_RSV_DUAL_P3_15_H (REG_DVI_RSV_DUAL_P3_BASE + 0x2B) 5473 #define REG_DVI_RSV_DUAL_P3_16_L (REG_DVI_RSV_DUAL_P3_BASE + 0x2C) 5474 #define REG_DVI_RSV_DUAL_P3_16_H (REG_DVI_RSV_DUAL_P3_BASE + 0x2D) 5475 #define REG_DVI_RSV_DUAL_P3_17_L (REG_DVI_RSV_DUAL_P3_BASE + 0x2E) 5476 #define REG_DVI_RSV_DUAL_P3_17_H (REG_DVI_RSV_DUAL_P3_BASE + 0x2F) 5477 #define REG_DVI_RSV_DUAL_P3_18_L (REG_DVI_RSV_DUAL_P3_BASE + 0x30) 5478 #define REG_DVI_RSV_DUAL_P3_18_H (REG_DVI_RSV_DUAL_P3_BASE + 0x31) 5479 #define REG_DVI_RSV_DUAL_P3_19_L (REG_DVI_RSV_DUAL_P3_BASE + 0x32) 5480 #define REG_DVI_RSV_DUAL_P3_19_H (REG_DVI_RSV_DUAL_P3_BASE + 0x33) 5481 #define REG_DVI_RSV_DUAL_P3_1A_L (REG_DVI_RSV_DUAL_P3_BASE + 0x34) 5482 #define REG_DVI_RSV_DUAL_P3_1A_H (REG_DVI_RSV_DUAL_P3_BASE + 0x35) 5483 #define REG_DVI_RSV_DUAL_P3_1B_L (REG_DVI_RSV_DUAL_P3_BASE + 0x36) 5484 #define REG_DVI_RSV_DUAL_P3_1B_H (REG_DVI_RSV_DUAL_P3_BASE + 0x37) 5485 #define REG_DVI_RSV_DUAL_P3_1C_L (REG_DVI_RSV_DUAL_P3_BASE + 0x38) 5486 #define REG_DVI_RSV_DUAL_P3_1C_H (REG_DVI_RSV_DUAL_P3_BASE + 0x39) 5487 #define REG_DVI_RSV_DUAL_P3_1D_L (REG_DVI_RSV_DUAL_P3_BASE + 0x3A) 5488 #define REG_DVI_RSV_DUAL_P3_1D_H (REG_DVI_RSV_DUAL_P3_BASE + 0x3B) 5489 #define REG_DVI_RSV_DUAL_P3_1E_L (REG_DVI_RSV_DUAL_P3_BASE + 0x3C) 5490 #define REG_DVI_RSV_DUAL_P3_1E_H (REG_DVI_RSV_DUAL_P3_BASE + 0x3D) 5491 #define REG_DVI_RSV_DUAL_P3_1F_L (REG_DVI_RSV_DUAL_P3_BASE + 0x3E) 5492 #define REG_DVI_RSV_DUAL_P3_1F_H (REG_DVI_RSV_DUAL_P3_BASE + 0x3F) 5493 5494 // HDCP_DUAL_P3 5495 #define REG_HDCP_DUAL_P3_00_L (REG_HDCP_DUAL_P3_BASE + 0x00) 5496 #define REG_HDCP_DUAL_P3_00_H (REG_HDCP_DUAL_P3_BASE + 0x01) 5497 #define REG_HDCP_DUAL_P3_01_L (REG_HDCP_DUAL_P3_BASE + 0x02) 5498 #define REG_HDCP_DUAL_P3_01_H (REG_HDCP_DUAL_P3_BASE + 0x03) 5499 #define REG_HDCP_DUAL_P3_02_L (REG_HDCP_DUAL_P3_BASE + 0x04) 5500 #define REG_HDCP_DUAL_P3_02_H (REG_HDCP_DUAL_P3_BASE + 0x05) 5501 #define REG_HDCP_DUAL_P3_03_L (REG_HDCP_DUAL_P3_BASE + 0x06) 5502 #define REG_HDCP_DUAL_P3_03_H (REG_HDCP_DUAL_P3_BASE + 0x07) 5503 #define REG_HDCP_DUAL_P3_04_L (REG_HDCP_DUAL_P3_BASE + 0x08) 5504 #define REG_HDCP_DUAL_P3_04_H (REG_HDCP_DUAL_P3_BASE + 0x09) 5505 #define REG_HDCP_DUAL_P3_05_L (REG_HDCP_DUAL_P3_BASE + 0x0A) 5506 #define REG_HDCP_DUAL_P3_05_H (REG_HDCP_DUAL_P3_BASE + 0x0B) 5507 #define REG_HDCP_DUAL_P3_06_L (REG_HDCP_DUAL_P3_BASE + 0x0C) 5508 #define REG_HDCP_DUAL_P3_06_H (REG_HDCP_DUAL_P3_BASE + 0x0D) 5509 #define REG_HDCP_DUAL_P3_07_L (REG_HDCP_DUAL_P3_BASE + 0x0E) 5510 #define REG_HDCP_DUAL_P3_07_H (REG_HDCP_DUAL_P3_BASE + 0x0F) 5511 #define REG_HDCP_DUAL_P3_08_L (REG_HDCP_DUAL_P3_BASE + 0x10) 5512 #define REG_HDCP_DUAL_P3_08_H (REG_HDCP_DUAL_P3_BASE + 0x11) 5513 #define REG_HDCP_DUAL_P3_09_L (REG_HDCP_DUAL_P3_BASE + 0x12) 5514 #define REG_HDCP_DUAL_P3_09_H (REG_HDCP_DUAL_P3_BASE + 0x13) 5515 #define REG_HDCP_DUAL_P3_0A_L (REG_HDCP_DUAL_P3_BASE + 0x14) 5516 #define REG_HDCP_DUAL_P3_0A_H (REG_HDCP_DUAL_P3_BASE + 0x15) 5517 #define REG_HDCP_DUAL_P3_0B_L (REG_HDCP_DUAL_P3_BASE + 0x16) 5518 #define REG_HDCP_DUAL_P3_0B_H (REG_HDCP_DUAL_P3_BASE + 0x17) 5519 #define REG_HDCP_DUAL_P3_0C_L (REG_HDCP_DUAL_P3_BASE + 0x18) 5520 #define REG_HDCP_DUAL_P3_0C_H (REG_HDCP_DUAL_P3_BASE + 0x19) 5521 #define REG_HDCP_DUAL_P3_0D_L (REG_HDCP_DUAL_P3_BASE + 0x1A) 5522 #define REG_HDCP_DUAL_P3_0D_H (REG_HDCP_DUAL_P3_BASE + 0x1B) 5523 #define REG_HDCP_DUAL_P3_0E_L (REG_HDCP_DUAL_P3_BASE + 0x1C) 5524 #define REG_HDCP_DUAL_P3_0E_H (REG_HDCP_DUAL_P3_BASE + 0x1D) 5525 #define REG_HDCP_DUAL_P3_0F_L (REG_HDCP_DUAL_P3_BASE + 0x1E) 5526 #define REG_HDCP_DUAL_P3_0F_H (REG_HDCP_DUAL_P3_BASE + 0x1F) 5527 #define REG_HDCP_DUAL_P3_10_L (REG_HDCP_DUAL_P3_BASE + 0x20) 5528 #define REG_HDCP_DUAL_P3_10_H (REG_HDCP_DUAL_P3_BASE + 0x21) 5529 #define REG_HDCP_DUAL_P3_11_L (REG_HDCP_DUAL_P3_BASE + 0x22) 5530 #define REG_HDCP_DUAL_P3_11_H (REG_HDCP_DUAL_P3_BASE + 0x23) 5531 #define REG_HDCP_DUAL_P3_12_L (REG_HDCP_DUAL_P3_BASE + 0x24) 5532 #define REG_HDCP_DUAL_P3_12_H (REG_HDCP_DUAL_P3_BASE + 0x25) 5533 #define REG_HDCP_DUAL_P3_13_L (REG_HDCP_DUAL_P3_BASE + 0x26) 5534 #define REG_HDCP_DUAL_P3_13_H (REG_HDCP_DUAL_P3_BASE + 0x27) 5535 #define REG_HDCP_DUAL_P3_14_L (REG_HDCP_DUAL_P3_BASE + 0x28) 5536 #define REG_HDCP_DUAL_P3_14_H (REG_HDCP_DUAL_P3_BASE + 0x29) 5537 #define REG_HDCP_DUAL_P3_15_L (REG_HDCP_DUAL_P3_BASE + 0x2A) 5538 #define REG_HDCP_DUAL_P3_15_H (REG_HDCP_DUAL_P3_BASE + 0x2B) 5539 #define REG_HDCP_DUAL_P3_16_L (REG_HDCP_DUAL_P3_BASE + 0x2C) 5540 #define REG_HDCP_DUAL_P3_16_H (REG_HDCP_DUAL_P3_BASE + 0x2D) 5541 #define REG_HDCP_DUAL_P3_17_L (REG_HDCP_DUAL_P3_BASE + 0x2E) 5542 #define REG_HDCP_DUAL_P3_17_H (REG_HDCP_DUAL_P3_BASE + 0x2F) 5543 #define REG_HDCP_DUAL_P3_18_L (REG_HDCP_DUAL_P3_BASE + 0x30) 5544 #define REG_HDCP_DUAL_P3_18_H (REG_HDCP_DUAL_P3_BASE + 0x31) 5545 #define REG_HDCP_DUAL_P3_19_L (REG_HDCP_DUAL_P3_BASE + 0x32) 5546 #define REG_HDCP_DUAL_P3_19_H (REG_HDCP_DUAL_P3_BASE + 0x33) 5547 #define REG_HDCP_DUAL_P3_1A_L (REG_HDCP_DUAL_P3_BASE + 0x34) 5548 #define REG_HDCP_DUAL_P3_1A_H (REG_HDCP_DUAL_P3_BASE + 0x35) 5549 #define REG_HDCP_DUAL_P3_1B_L (REG_HDCP_DUAL_P3_BASE + 0x36) 5550 #define REG_HDCP_DUAL_P3_1B_H (REG_HDCP_DUAL_P3_BASE + 0x37) 5551 #define REG_HDCP_DUAL_P3_1C_L (REG_HDCP_DUAL_P3_BASE + 0x38) 5552 #define REG_HDCP_DUAL_P3_1C_H (REG_HDCP_DUAL_P3_BASE + 0x39) 5553 #define REG_HDCP_DUAL_P3_1D_L (REG_HDCP_DUAL_P3_BASE + 0x3A) 5554 #define REG_HDCP_DUAL_P3_1D_H (REG_HDCP_DUAL_P3_BASE + 0x3B) 5555 #define REG_HDCP_DUAL_P3_1E_L (REG_HDCP_DUAL_P3_BASE + 0x3C) 5556 #define REG_HDCP_DUAL_P3_1E_H (REG_HDCP_DUAL_P3_BASE + 0x3D) 5557 #define REG_HDCP_DUAL_P3_1F_L (REG_HDCP_DUAL_P3_BASE + 0x3E) 5558 #define REG_HDCP_DUAL_P3_1F_H (REG_HDCP_DUAL_P3_BASE + 0x3F) 5559 #define REG_HDCP_DUAL_P3_20_L (REG_HDCP_DUAL_P3_BASE + 0x40) 5560 #define REG_HDCP_DUAL_P3_20_H (REG_HDCP_DUAL_P3_BASE + 0x41) 5561 #define REG_HDCP_DUAL_P3_21_L (REG_HDCP_DUAL_P3_BASE + 0x42) 5562 #define REG_HDCP_DUAL_P3_21_H (REG_HDCP_DUAL_P3_BASE + 0x43) 5563 #define REG_HDCP_DUAL_P3_22_L (REG_HDCP_DUAL_P3_BASE + 0x44) 5564 #define REG_HDCP_DUAL_P3_22_H (REG_HDCP_DUAL_P3_BASE + 0x45) 5565 #define REG_HDCP_DUAL_P3_23_L (REG_HDCP_DUAL_P3_BASE + 0x46) 5566 #define REG_HDCP_DUAL_P3_23_H (REG_HDCP_DUAL_P3_BASE + 0x47) 5567 #define REG_HDCP_DUAL_P3_24_L (REG_HDCP_DUAL_P3_BASE + 0x48) 5568 #define REG_HDCP_DUAL_P3_24_H (REG_HDCP_DUAL_P3_BASE + 0x49) 5569 #define REG_HDCP_DUAL_P3_25_L (REG_HDCP_DUAL_P3_BASE + 0x4A) 5570 #define REG_HDCP_DUAL_P3_25_H (REG_HDCP_DUAL_P3_BASE + 0x4B) 5571 #define REG_HDCP_DUAL_P3_26_L (REG_HDCP_DUAL_P3_BASE + 0x4C) 5572 #define REG_HDCP_DUAL_P3_26_H (REG_HDCP_DUAL_P3_BASE + 0x4D) 5573 #define REG_HDCP_DUAL_P3_27_L (REG_HDCP_DUAL_P3_BASE + 0x4E) 5574 #define REG_HDCP_DUAL_P3_27_H (REG_HDCP_DUAL_P3_BASE + 0x4F) 5575 #define REG_HDCP_DUAL_P3_28_L (REG_HDCP_DUAL_P3_BASE + 0x50) 5576 #define REG_HDCP_DUAL_P3_28_H (REG_HDCP_DUAL_P3_BASE + 0x51) 5577 #define REG_HDCP_DUAL_P3_29_L (REG_HDCP_DUAL_P3_BASE + 0x52) 5578 #define REG_HDCP_DUAL_P3_29_H (REG_HDCP_DUAL_P3_BASE + 0x53) 5579 #define REG_HDCP_DUAL_P3_2A_L (REG_HDCP_DUAL_P3_BASE + 0x54) 5580 #define REG_HDCP_DUAL_P3_2A_H (REG_HDCP_DUAL_P3_BASE + 0x55) 5581 #define REG_HDCP_DUAL_P3_2B_L (REG_HDCP_DUAL_P3_BASE + 0x56) 5582 #define REG_HDCP_DUAL_P3_2B_H (REG_HDCP_DUAL_P3_BASE + 0x57) 5583 #define REG_HDCP_DUAL_P3_2C_L (REG_HDCP_DUAL_P3_BASE + 0x58) 5584 #define REG_HDCP_DUAL_P3_2C_H (REG_HDCP_DUAL_P3_BASE + 0x59) 5585 #define REG_HDCP_DUAL_P3_2D_L (REG_HDCP_DUAL_P3_BASE + 0x5A) 5586 #define REG_HDCP_DUAL_P3_2D_H (REG_HDCP_DUAL_P3_BASE + 0x5B) 5587 #define REG_HDCP_DUAL_P3_2E_L (REG_HDCP_DUAL_P3_BASE + 0x5C) 5588 #define REG_HDCP_DUAL_P3_2E_H (REG_HDCP_DUAL_P3_BASE + 0x5D) 5589 #define REG_HDCP_DUAL_P3_2F_L (REG_HDCP_DUAL_P3_BASE + 0x5E) 5590 #define REG_HDCP_DUAL_P3_2F_H (REG_HDCP_DUAL_P3_BASE + 0x5F) 5591 #define REG_HDCP_DUAL_P3_30_L (REG_HDCP_DUAL_P3_BASE + 0x60) 5592 #define REG_HDCP_DUAL_P3_30_H (REG_HDCP_DUAL_P3_BASE + 0x61) 5593 #define REG_HDCP_DUAL_P3_31_L (REG_HDCP_DUAL_P3_BASE + 0x62) 5594 #define REG_HDCP_DUAL_P3_31_H (REG_HDCP_DUAL_P3_BASE + 0x63) 5595 #define REG_HDCP_DUAL_P3_32_L (REG_HDCP_DUAL_P3_BASE + 0x64) 5596 #define REG_HDCP_DUAL_P3_32_H (REG_HDCP_DUAL_P3_BASE + 0x65) 5597 #define REG_HDCP_DUAL_P3_33_L (REG_HDCP_DUAL_P3_BASE + 0x66) 5598 #define REG_HDCP_DUAL_P3_33_H (REG_HDCP_DUAL_P3_BASE + 0x67) 5599 #define REG_HDCP_DUAL_P3_34_L (REG_HDCP_DUAL_P3_BASE + 0x68) 5600 #define REG_HDCP_DUAL_P3_34_H (REG_HDCP_DUAL_P3_BASE + 0x69) 5601 #define REG_HDCP_DUAL_P3_35_L (REG_HDCP_DUAL_P3_BASE + 0x6A) 5602 #define REG_HDCP_DUAL_P3_35_H (REG_HDCP_DUAL_P3_BASE + 0x6B) 5603 #define REG_HDCP_DUAL_P3_36_L (REG_HDCP_DUAL_P3_BASE + 0x6C) 5604 #define REG_HDCP_DUAL_P3_36_H (REG_HDCP_DUAL_P3_BASE + 0x6D) 5605 #define REG_HDCP_DUAL_P3_37_L (REG_HDCP_DUAL_P3_BASE + 0x6E) 5606 #define REG_HDCP_DUAL_P3_37_H (REG_HDCP_DUAL_P3_BASE + 0x6F) 5607 #define REG_HDCP_DUAL_P3_38_L (REG_HDCP_DUAL_P3_BASE + 0x70) 5608 #define REG_HDCP_DUAL_P3_38_H (REG_HDCP_DUAL_P3_BASE + 0x71) 5609 #define REG_HDCP_DUAL_P3_39_L (REG_HDCP_DUAL_P3_BASE + 0x72) 5610 #define REG_HDCP_DUAL_P3_39_H (REG_HDCP_DUAL_P3_BASE + 0x73) 5611 #define REG_HDCP_DUAL_P3_3A_L (REG_HDCP_DUAL_P3_BASE + 0x74) 5612 #define REG_HDCP_DUAL_P3_3A_H (REG_HDCP_DUAL_P3_BASE + 0x75) 5613 #define REG_HDCP_DUAL_P3_3B_L (REG_HDCP_DUAL_P3_BASE + 0x76) 5614 #define REG_HDCP_DUAL_P3_3B_H (REG_HDCP_DUAL_P3_BASE + 0x77) 5615 #define REG_HDCP_DUAL_P3_3C_L (REG_HDCP_DUAL_P3_BASE + 0x78) 5616 #define REG_HDCP_DUAL_P3_3C_H (REG_HDCP_DUAL_P3_BASE + 0x79) 5617 #define REG_HDCP_DUAL_P3_3D_L (REG_HDCP_DUAL_P3_BASE + 0x7A) 5618 #define REG_HDCP_DUAL_P3_3D_H (REG_HDCP_DUAL_P3_BASE + 0x7B) 5619 #define REG_HDCP_DUAL_P3_3E_L (REG_HDCP_DUAL_P3_BASE + 0x7C) 5620 #define REG_HDCP_DUAL_P3_3E_H (REG_HDCP_DUAL_P3_BASE + 0x7D) 5621 #define REG_HDCP_DUAL_P3_3F_L (REG_HDCP_DUAL_P3_BASE + 0x7E) 5622 #define REG_HDCP_DUAL_P3_3F_H (REG_HDCP_DUAL_P3_BASE + 0x7F) 5623 #define REG_HDCP_DUAL_P3_40_L (REG_HDCP_DUAL_P3_BASE + 0x80) 5624 #define REG_HDCP_DUAL_P3_40_H (REG_HDCP_DUAL_P3_BASE + 0x81) 5625 #define REG_HDCP_DUAL_P3_41_L (REG_HDCP_DUAL_P3_BASE + 0x82) 5626 #define REG_HDCP_DUAL_P3_41_H (REG_HDCP_DUAL_P3_BASE + 0x83) 5627 #define REG_HDCP_DUAL_P3_42_L (REG_HDCP_DUAL_P3_BASE + 0x84) 5628 #define REG_HDCP_DUAL_P3_42_H (REG_HDCP_DUAL_P3_BASE + 0x85) 5629 #define REG_HDCP_DUAL_P3_43_L (REG_HDCP_DUAL_P3_BASE + 0x86) 5630 #define REG_HDCP_DUAL_P3_43_H (REG_HDCP_DUAL_P3_BASE + 0x87) 5631 #define REG_HDCP_DUAL_P3_44_L (REG_HDCP_DUAL_P3_BASE + 0x88) 5632 #define REG_HDCP_DUAL_P3_44_H (REG_HDCP_DUAL_P3_BASE + 0x89) 5633 #define REG_HDCP_DUAL_P3_45_L (REG_HDCP_DUAL_P3_BASE + 0x8A) 5634 #define REG_HDCP_DUAL_P3_45_H (REG_HDCP_DUAL_P3_BASE + 0x8B) 5635 #define REG_HDCP_DUAL_P3_46_L (REG_HDCP_DUAL_P3_BASE + 0x8C) 5636 #define REG_HDCP_DUAL_P3_46_H (REG_HDCP_DUAL_P3_BASE + 0x8D) 5637 #define REG_HDCP_DUAL_P3_47_L (REG_HDCP_DUAL_P3_BASE + 0x8E) 5638 #define REG_HDCP_DUAL_P3_47_H (REG_HDCP_DUAL_P3_BASE + 0x8F) 5639 #define REG_HDCP_DUAL_P3_48_L (REG_HDCP_DUAL_P3_BASE + 0x90) 5640 #define REG_HDCP_DUAL_P3_48_H (REG_HDCP_DUAL_P3_BASE + 0x91) 5641 #define REG_HDCP_DUAL_P3_49_L (REG_HDCP_DUAL_P3_BASE + 0x92) 5642 #define REG_HDCP_DUAL_P3_49_H (REG_HDCP_DUAL_P3_BASE + 0x93) 5643 #define REG_HDCP_DUAL_P3_4A_L (REG_HDCP_DUAL_P3_BASE + 0x94) 5644 #define REG_HDCP_DUAL_P3_4A_H (REG_HDCP_DUAL_P3_BASE + 0x95) 5645 #define REG_HDCP_DUAL_P3_4B_L (REG_HDCP_DUAL_P3_BASE + 0x96) 5646 #define REG_HDCP_DUAL_P3_4B_H (REG_HDCP_DUAL_P3_BASE + 0x97) 5647 #define REG_HDCP_DUAL_P3_4C_L (REG_HDCP_DUAL_P3_BASE + 0x98) 5648 #define REG_HDCP_DUAL_P3_4C_H (REG_HDCP_DUAL_P3_BASE + 0x99) 5649 #define REG_HDCP_DUAL_P3_4D_L (REG_HDCP_DUAL_P3_BASE + 0x9A) 5650 #define REG_HDCP_DUAL_P3_4D_H (REG_HDCP_DUAL_P3_BASE + 0x9B) 5651 #define REG_HDCP_DUAL_P3_4E_L (REG_HDCP_DUAL_P3_BASE + 0x9C) 5652 #define REG_HDCP_DUAL_P3_4E_H (REG_HDCP_DUAL_P3_BASE + 0x9D) 5653 #define REG_HDCP_DUAL_P3_4F_L (REG_HDCP_DUAL_P3_BASE + 0x9E) 5654 #define REG_HDCP_DUAL_P3_4F_H (REG_HDCP_DUAL_P3_BASE + 0x9F) 5655 #define REG_HDCP_DUAL_P3_50_L (REG_HDCP_DUAL_P3_BASE + 0xA0) 5656 #define REG_HDCP_DUAL_P3_50_H (REG_HDCP_DUAL_P3_BASE + 0xA1) 5657 #define REG_HDCP_DUAL_P3_51_L (REG_HDCP_DUAL_P3_BASE + 0xA2) 5658 #define REG_HDCP_DUAL_P3_51_H (REG_HDCP_DUAL_P3_BASE + 0xA3) 5659 #define REG_HDCP_DUAL_P3_52_L (REG_HDCP_DUAL_P3_BASE + 0xA4) 5660 #define REG_HDCP_DUAL_P3_52_H (REG_HDCP_DUAL_P3_BASE + 0xA5) 5661 #define REG_HDCP_DUAL_P3_53_L (REG_HDCP_DUAL_P3_BASE + 0xA6) 5662 #define REG_HDCP_DUAL_P3_53_H (REG_HDCP_DUAL_P3_BASE + 0xA7) 5663 #define REG_HDCP_DUAL_P3_54_L (REG_HDCP_DUAL_P3_BASE + 0xA8) 5664 #define REG_HDCP_DUAL_P3_54_H (REG_HDCP_DUAL_P3_BASE + 0xA9) 5665 #define REG_HDCP_DUAL_P3_55_L (REG_HDCP_DUAL_P3_BASE + 0xAA) 5666 #define REG_HDCP_DUAL_P3_55_H (REG_HDCP_DUAL_P3_BASE + 0xAB) 5667 #define REG_HDCP_DUAL_P3_56_L (REG_HDCP_DUAL_P3_BASE + 0xAC) 5668 #define REG_HDCP_DUAL_P3_56_H (REG_HDCP_DUAL_P3_BASE + 0xAD) 5669 #define REG_HDCP_DUAL_P3_57_L (REG_HDCP_DUAL_P3_BASE + 0xAE) 5670 #define REG_HDCP_DUAL_P3_57_H (REG_HDCP_DUAL_P3_BASE + 0xAF) 5671 #define REG_HDCP_DUAL_P3_58_L (REG_HDCP_DUAL_P3_BASE + 0xB0) 5672 #define REG_HDCP_DUAL_P3_58_H (REG_HDCP_DUAL_P3_BASE + 0xB1) 5673 #define REG_HDCP_DUAL_P3_59_L (REG_HDCP_DUAL_P3_BASE + 0xB2) 5674 #define REG_HDCP_DUAL_P3_59_H (REG_HDCP_DUAL_P3_BASE + 0xB3) 5675 #define REG_HDCP_DUAL_P3_5A_L (REG_HDCP_DUAL_P3_BASE + 0xB4) 5676 #define REG_HDCP_DUAL_P3_5A_H (REG_HDCP_DUAL_P3_BASE + 0xB5) 5677 #define REG_HDCP_DUAL_P3_5B_L (REG_HDCP_DUAL_P3_BASE + 0xB6) 5678 #define REG_HDCP_DUAL_P3_5B_H (REG_HDCP_DUAL_P3_BASE + 0xB7) 5679 #define REG_HDCP_DUAL_P3_5C_L (REG_HDCP_DUAL_P3_BASE + 0xB8) 5680 #define REG_HDCP_DUAL_P3_5C_H (REG_HDCP_DUAL_P3_BASE + 0xB9) 5681 #define REG_HDCP_DUAL_P3_5D_L (REG_HDCP_DUAL_P3_BASE + 0xBA) 5682 #define REG_HDCP_DUAL_P3_5D_H (REG_HDCP_DUAL_P3_BASE + 0xBB) 5683 #define REG_HDCP_DUAL_P3_5E_L (REG_HDCP_DUAL_P3_BASE + 0xBC) 5684 #define REG_HDCP_DUAL_P3_5E_H (REG_HDCP_DUAL_P3_BASE + 0xBD) 5685 #define REG_HDCP_DUAL_P3_5F_L (REG_HDCP_DUAL_P3_BASE + 0xBE) 5686 #define REG_HDCP_DUAL_P3_5F_H (REG_HDCP_DUAL_P3_BASE + 0xBF) 5687 #define REG_HDCP_DUAL_P3_60_L (REG_HDCP_DUAL_P3_BASE + 0xC0) 5688 #define REG_HDCP_DUAL_P3_60_H (REG_HDCP_DUAL_P3_BASE + 0xC1) 5689 #define REG_HDCP_DUAL_P3_61_L (REG_HDCP_DUAL_P3_BASE + 0xC2) 5690 #define REG_HDCP_DUAL_P3_61_H (REG_HDCP_DUAL_P3_BASE + 0xC3) 5691 #define REG_HDCP_DUAL_P3_62_L (REG_HDCP_DUAL_P3_BASE + 0xC4) 5692 #define REG_HDCP_DUAL_P3_62_H (REG_HDCP_DUAL_P3_BASE + 0xC5) 5693 #define REG_HDCP_DUAL_P3_63_L (REG_HDCP_DUAL_P3_BASE + 0xC6) 5694 #define REG_HDCP_DUAL_P3_63_H (REG_HDCP_DUAL_P3_BASE + 0xC7) 5695 #define REG_HDCP_DUAL_P3_64_L (REG_HDCP_DUAL_P3_BASE + 0xC8) 5696 #define REG_HDCP_DUAL_P3_64_H (REG_HDCP_DUAL_P3_BASE + 0xC9) 5697 #define REG_HDCP_DUAL_P3_65_L (REG_HDCP_DUAL_P3_BASE + 0xCA) 5698 #define REG_HDCP_DUAL_P3_65_H (REG_HDCP_DUAL_P3_BASE + 0xCB) 5699 #define REG_HDCP_DUAL_P3_66_L (REG_HDCP_DUAL_P3_BASE + 0xCC) 5700 #define REG_HDCP_DUAL_P3_66_H (REG_HDCP_DUAL_P3_BASE + 0xCD) 5701 #define REG_HDCP_DUAL_P3_67_L (REG_HDCP_DUAL_P3_BASE + 0xCE) 5702 #define REG_HDCP_DUAL_P3_67_H (REG_HDCP_DUAL_P3_BASE + 0xCF) 5703 #define REG_HDCP_DUAL_P3_68_L (REG_HDCP_DUAL_P3_BASE + 0xD0) 5704 #define REG_HDCP_DUAL_P3_68_H (REG_HDCP_DUAL_P3_BASE + 0xD1) 5705 5706 //============================================================= 5707 5708 // HDMI_DUAL_0 5709 #define REG_HDMI_DUAL_0_00_L (REG_HDMI_DUAL_0_BASE + 0x00) 5710 #define REG_HDMI_DUAL_0_00_H (REG_HDMI_DUAL_0_BASE + 0x01) 5711 #define REG_HDMI_DUAL_0_01_L (REG_HDMI_DUAL_0_BASE + 0x02) 5712 #define REG_HDMI_DUAL_0_01_H (REG_HDMI_DUAL_0_BASE + 0x03) 5713 #define REG_HDMI_DUAL_0_02_L (REG_HDMI_DUAL_0_BASE + 0x04) 5714 #define REG_HDMI_DUAL_0_02_H (REG_HDMI_DUAL_0_BASE + 0x05) 5715 #define REG_HDMI_DUAL_0_03_L (REG_HDMI_DUAL_0_BASE + 0x06) 5716 #define REG_HDMI_DUAL_0_03_H (REG_HDMI_DUAL_0_BASE + 0x07) 5717 #define REG_HDMI_DUAL_0_04_L (REG_HDMI_DUAL_0_BASE + 0x08) 5718 #define REG_HDMI_DUAL_0_04_H (REG_HDMI_DUAL_0_BASE + 0x09) 5719 #define REG_HDMI_DUAL_0_05_L (REG_HDMI_DUAL_0_BASE + 0x0A) 5720 #define REG_HDMI_DUAL_0_05_H (REG_HDMI_DUAL_0_BASE + 0x0B) 5721 #define REG_HDMI_DUAL_0_06_L (REG_HDMI_DUAL_0_BASE + 0x0C) 5722 #define REG_HDMI_DUAL_0_06_H (REG_HDMI_DUAL_0_BASE + 0x0D) 5723 #define REG_HDMI_DUAL_0_07_L (REG_HDMI_DUAL_0_BASE + 0x0E) 5724 #define REG_HDMI_DUAL_0_07_H (REG_HDMI_DUAL_0_BASE + 0x0F) 5725 #define REG_HDMI_DUAL_0_08_L (REG_HDMI_DUAL_0_BASE + 0x10) 5726 #define REG_HDMI_DUAL_0_08_H (REG_HDMI_DUAL_0_BASE + 0x11) 5727 #define REG_HDMI_DUAL_0_09_L (REG_HDMI_DUAL_0_BASE + 0x12) 5728 #define REG_HDMI_DUAL_0_09_H (REG_HDMI_DUAL_0_BASE + 0x13) 5729 #define REG_HDMI_DUAL_0_0A_L (REG_HDMI_DUAL_0_BASE + 0x14) 5730 #define REG_HDMI_DUAL_0_0A_H (REG_HDMI_DUAL_0_BASE + 0x15) 5731 #define REG_HDMI_DUAL_0_0B_L (REG_HDMI_DUAL_0_BASE + 0x16) 5732 #define REG_HDMI_DUAL_0_0B_H (REG_HDMI_DUAL_0_BASE + 0x17) 5733 #define REG_HDMI_DUAL_0_0C_L (REG_HDMI_DUAL_0_BASE + 0x18) 5734 #define REG_HDMI_DUAL_0_0C_H (REG_HDMI_DUAL_0_BASE + 0x19) 5735 #define REG_HDMI_DUAL_0_0D_L (REG_HDMI_DUAL_0_BASE + 0x1A) 5736 #define REG_HDMI_DUAL_0_0D_H (REG_HDMI_DUAL_0_BASE + 0x1B) 5737 #define REG_HDMI_DUAL_0_0E_L (REG_HDMI_DUAL_0_BASE + 0x1C) 5738 #define REG_HDMI_DUAL_0_0E_H (REG_HDMI_DUAL_0_BASE + 0x1D) 5739 #define REG_HDMI_DUAL_0_0F_L (REG_HDMI_DUAL_0_BASE + 0x1E) 5740 #define REG_HDMI_DUAL_0_0F_H (REG_HDMI_DUAL_0_BASE + 0x1F) 5741 #define REG_HDMI_DUAL_0_10_L (REG_HDMI_DUAL_0_BASE + 0x20) 5742 #define REG_HDMI_DUAL_0_10_H (REG_HDMI_DUAL_0_BASE + 0x21) 5743 #define REG_HDMI_DUAL_0_11_L (REG_HDMI_DUAL_0_BASE + 0x22) 5744 #define REG_HDMI_DUAL_0_11_H (REG_HDMI_DUAL_0_BASE + 0x23) 5745 #define REG_HDMI_DUAL_0_12_L (REG_HDMI_DUAL_0_BASE + 0x24) 5746 #define REG_HDMI_DUAL_0_12_H (REG_HDMI_DUAL_0_BASE + 0x25) 5747 #define REG_HDMI_DUAL_0_13_L (REG_HDMI_DUAL_0_BASE + 0x26) 5748 #define REG_HDMI_DUAL_0_13_H (REG_HDMI_DUAL_0_BASE + 0x27) 5749 #define REG_HDMI_DUAL_0_14_L (REG_HDMI_DUAL_0_BASE + 0x28) 5750 #define REG_HDMI_DUAL_0_14_H (REG_HDMI_DUAL_0_BASE + 0x29) 5751 #define REG_HDMI_DUAL_0_15_L (REG_HDMI_DUAL_0_BASE + 0x2A) 5752 #define REG_HDMI_DUAL_0_15_H (REG_HDMI_DUAL_0_BASE + 0x2B) 5753 #define REG_HDMI_DUAL_0_16_L (REG_HDMI_DUAL_0_BASE + 0x2C) 5754 #define REG_HDMI_DUAL_0_16_H (REG_HDMI_DUAL_0_BASE + 0x2D) 5755 #define REG_HDMI_DUAL_0_17_L (REG_HDMI_DUAL_0_BASE + 0x2E) 5756 #define REG_HDMI_DUAL_0_17_H (REG_HDMI_DUAL_0_BASE + 0x2F) 5757 #define REG_HDMI_DUAL_0_18_L (REG_HDMI_DUAL_0_BASE + 0x30) 5758 #define REG_HDMI_DUAL_0_18_H (REG_HDMI_DUAL_0_BASE + 0x31) 5759 #define REG_HDMI_DUAL_0_19_L (REG_HDMI_DUAL_0_BASE + 0x32) 5760 #define REG_HDMI_DUAL_0_19_H (REG_HDMI_DUAL_0_BASE + 0x33) 5761 #define REG_HDMI_DUAL_0_1A_L (REG_HDMI_DUAL_0_BASE + 0x34) 5762 #define REG_HDMI_DUAL_0_1A_H (REG_HDMI_DUAL_0_BASE + 0x35) 5763 #define REG_HDMI_DUAL_0_1B_L (REG_HDMI_DUAL_0_BASE + 0x36) 5764 #define REG_HDMI_DUAL_0_1B_H (REG_HDMI_DUAL_0_BASE + 0x37) 5765 #define REG_HDMI_DUAL_0_1C_L (REG_HDMI_DUAL_0_BASE + 0x38) 5766 #define REG_HDMI_DUAL_0_1C_H (REG_HDMI_DUAL_0_BASE + 0x39) 5767 #define REG_HDMI_DUAL_0_1D_L (REG_HDMI_DUAL_0_BASE + 0x3A) 5768 #define REG_HDMI_DUAL_0_1D_H (REG_HDMI_DUAL_0_BASE + 0x3B) 5769 #define REG_HDMI_DUAL_0_1E_L (REG_HDMI_DUAL_0_BASE + 0x3C) 5770 #define REG_HDMI_DUAL_0_1E_H (REG_HDMI_DUAL_0_BASE + 0x3D) 5771 #define REG_HDMI_DUAL_0_1F_L (REG_HDMI_DUAL_0_BASE + 0x3E) 5772 #define REG_HDMI_DUAL_0_1F_H (REG_HDMI_DUAL_0_BASE + 0x3F) 5773 #define REG_HDMI_DUAL_0_20_L (REG_HDMI_DUAL_0_BASE + 0x40) 5774 #define REG_HDMI_DUAL_0_20_H (REG_HDMI_DUAL_0_BASE + 0x41) 5775 #define REG_HDMI_DUAL_0_21_L (REG_HDMI_DUAL_0_BASE + 0x42) 5776 #define REG_HDMI_DUAL_0_21_H (REG_HDMI_DUAL_0_BASE + 0x43) 5777 #define REG_HDMI_DUAL_0_22_L (REG_HDMI_DUAL_0_BASE + 0x44) 5778 #define REG_HDMI_DUAL_0_22_H (REG_HDMI_DUAL_0_BASE + 0x45) 5779 #define REG_HDMI_DUAL_0_23_L (REG_HDMI_DUAL_0_BASE + 0x46) 5780 #define REG_HDMI_DUAL_0_23_H (REG_HDMI_DUAL_0_BASE + 0x47) 5781 #define REG_HDMI_DUAL_0_24_L (REG_HDMI_DUAL_0_BASE + 0x48) 5782 #define REG_HDMI_DUAL_0_24_H (REG_HDMI_DUAL_0_BASE + 0x49) 5783 #define REG_HDMI_DUAL_0_25_L (REG_HDMI_DUAL_0_BASE + 0x4A) 5784 #define REG_HDMI_DUAL_0_25_H (REG_HDMI_DUAL_0_BASE + 0x4B) 5785 #define REG_HDMI_DUAL_0_26_L (REG_HDMI_DUAL_0_BASE + 0x4C) 5786 #define REG_HDMI_DUAL_0_26_H (REG_HDMI_DUAL_0_BASE + 0x4D) 5787 #define REG_HDMI_DUAL_0_27_L (REG_HDMI_DUAL_0_BASE + 0x4E) 5788 #define REG_HDMI_DUAL_0_27_H (REG_HDMI_DUAL_0_BASE + 0x4F) 5789 #define REG_HDMI_DUAL_0_28_L (REG_HDMI_DUAL_0_BASE + 0x50) 5790 #define REG_HDMI_DUAL_0_28_H (REG_HDMI_DUAL_0_BASE + 0x51) 5791 #define REG_HDMI_DUAL_0_29_L (REG_HDMI_DUAL_0_BASE + 0x52) 5792 #define REG_HDMI_DUAL_0_29_H (REG_HDMI_DUAL_0_BASE + 0x53) 5793 #define REG_HDMI_DUAL_0_2A_L (REG_HDMI_DUAL_0_BASE + 0x54) 5794 #define REG_HDMI_DUAL_0_2A_H (REG_HDMI_DUAL_0_BASE + 0x55) 5795 #define REG_HDMI_DUAL_0_2B_L (REG_HDMI_DUAL_0_BASE + 0x56) 5796 #define REG_HDMI_DUAL_0_2B_H (REG_HDMI_DUAL_0_BASE + 0x57) 5797 #define REG_HDMI_DUAL_0_2C_L (REG_HDMI_DUAL_0_BASE + 0x58) 5798 #define REG_HDMI_DUAL_0_2C_H (REG_HDMI_DUAL_0_BASE + 0x59) 5799 #define REG_HDMI_DUAL_0_2D_L (REG_HDMI_DUAL_0_BASE + 0x5A) 5800 #define REG_HDMI_DUAL_0_2D_H (REG_HDMI_DUAL_0_BASE + 0x5B) 5801 #define REG_HDMI_DUAL_0_2E_L (REG_HDMI_DUAL_0_BASE + 0x5C) 5802 #define REG_HDMI_DUAL_0_2E_H (REG_HDMI_DUAL_0_BASE + 0x5D) 5803 #define REG_HDMI_DUAL_0_2F_L (REG_HDMI_DUAL_0_BASE + 0x5E) 5804 #define REG_HDMI_DUAL_0_2F_H (REG_HDMI_DUAL_0_BASE + 0x5F) 5805 #define REG_HDMI_DUAL_0_30_L (REG_HDMI_DUAL_0_BASE + 0x60) 5806 #define REG_HDMI_DUAL_0_30_H (REG_HDMI_DUAL_0_BASE + 0x61) 5807 #define REG_HDMI_DUAL_0_31_L (REG_HDMI_DUAL_0_BASE + 0x62) 5808 #define REG_HDMI_DUAL_0_31_H (REG_HDMI_DUAL_0_BASE + 0x63) 5809 #define REG_HDMI_DUAL_0_32_L (REG_HDMI_DUAL_0_BASE + 0x64) 5810 #define REG_HDMI_DUAL_0_32_H (REG_HDMI_DUAL_0_BASE + 0x65) 5811 #define REG_HDMI_DUAL_0_33_L (REG_HDMI_DUAL_0_BASE + 0x66) 5812 #define REG_HDMI_DUAL_0_33_H (REG_HDMI_DUAL_0_BASE + 0x67) 5813 #define REG_HDMI_DUAL_0_34_L (REG_HDMI_DUAL_0_BASE + 0x68) 5814 #define REG_HDMI_DUAL_0_34_H (REG_HDMI_DUAL_0_BASE + 0x69) 5815 #define REG_HDMI_DUAL_0_35_L (REG_HDMI_DUAL_0_BASE + 0x6A) 5816 #define REG_HDMI_DUAL_0_35_H (REG_HDMI_DUAL_0_BASE + 0x6B) 5817 #define REG_HDMI_DUAL_0_36_L (REG_HDMI_DUAL_0_BASE + 0x6C) 5818 #define REG_HDMI_DUAL_0_36_H (REG_HDMI_DUAL_0_BASE + 0x6D) 5819 #define REG_HDMI_DUAL_0_37_L (REG_HDMI_DUAL_0_BASE + 0x6E) 5820 #define REG_HDMI_DUAL_0_37_H (REG_HDMI_DUAL_0_BASE + 0x6F) 5821 #define REG_HDMI_DUAL_0_38_L (REG_HDMI_DUAL_0_BASE + 0x70) 5822 #define REG_HDMI_DUAL_0_38_H (REG_HDMI_DUAL_0_BASE + 0x71) 5823 #define REG_HDMI_DUAL_0_39_L (REG_HDMI_DUAL_0_BASE + 0x72) 5824 #define REG_HDMI_DUAL_0_39_H (REG_HDMI_DUAL_0_BASE + 0x73) 5825 #define REG_HDMI_DUAL_0_3A_L (REG_HDMI_DUAL_0_BASE + 0x74) 5826 #define REG_HDMI_DUAL_0_3A_H (REG_HDMI_DUAL_0_BASE + 0x75) 5827 #define REG_HDMI_DUAL_0_3B_L (REG_HDMI_DUAL_0_BASE + 0x76) 5828 #define REG_HDMI_DUAL_0_3B_H (REG_HDMI_DUAL_0_BASE + 0x77) 5829 #define REG_HDMI_DUAL_0_3C_L (REG_HDMI_DUAL_0_BASE + 0x78) 5830 #define REG_HDMI_DUAL_0_3C_H (REG_HDMI_DUAL_0_BASE + 0x79) 5831 #define REG_HDMI_DUAL_0_3D_L (REG_HDMI_DUAL_0_BASE + 0x7A) 5832 #define REG_HDMI_DUAL_0_3D_H (REG_HDMI_DUAL_0_BASE + 0x7B) 5833 #define REG_HDMI_DUAL_0_3E_L (REG_HDMI_DUAL_0_BASE + 0x7C) 5834 #define REG_HDMI_DUAL_0_3E_H (REG_HDMI_DUAL_0_BASE + 0x7D) 5835 #define REG_HDMI_DUAL_0_3F_L (REG_HDMI_DUAL_0_BASE + 0x7E) 5836 #define REG_HDMI_DUAL_0_3F_H (REG_HDMI_DUAL_0_BASE + 0x7F) 5837 #define REG_HDMI_DUAL_0_40_L (REG_HDMI_DUAL_0_BASE + 0x80) 5838 #define REG_HDMI_DUAL_0_40_H (REG_HDMI_DUAL_0_BASE + 0x81) 5839 #define REG_HDMI_DUAL_0_41_L (REG_HDMI_DUAL_0_BASE + 0x82) 5840 #define REG_HDMI_DUAL_0_41_H (REG_HDMI_DUAL_0_BASE + 0x83) 5841 #define REG_HDMI_DUAL_0_42_L (REG_HDMI_DUAL_0_BASE + 0x84) 5842 #define REG_HDMI_DUAL_0_42_H (REG_HDMI_DUAL_0_BASE + 0x85) 5843 #define REG_HDMI_DUAL_0_43_L (REG_HDMI_DUAL_0_BASE + 0x86) 5844 #define REG_HDMI_DUAL_0_43_H (REG_HDMI_DUAL_0_BASE + 0x87) 5845 #define REG_HDMI_DUAL_0_44_L (REG_HDMI_DUAL_0_BASE + 0x88) 5846 #define REG_HDMI_DUAL_0_44_H (REG_HDMI_DUAL_0_BASE + 0x89) 5847 #define REG_HDMI_DUAL_0_45_L (REG_HDMI_DUAL_0_BASE + 0x8A) 5848 #define REG_HDMI_DUAL_0_45_H (REG_HDMI_DUAL_0_BASE + 0x8B) 5849 #define REG_HDMI_DUAL_0_46_L (REG_HDMI_DUAL_0_BASE + 0x8C) 5850 #define REG_HDMI_DUAL_0_46_H (REG_HDMI_DUAL_0_BASE + 0x8D) 5851 #define REG_HDMI_DUAL_0_47_L (REG_HDMI_DUAL_0_BASE + 0x8E) 5852 #define REG_HDMI_DUAL_0_47_H (REG_HDMI_DUAL_0_BASE + 0x8F) 5853 #define REG_HDMI_DUAL_0_48_L (REG_HDMI_DUAL_0_BASE + 0x90) 5854 #define REG_HDMI_DUAL_0_48_H (REG_HDMI_DUAL_0_BASE + 0x91) 5855 #define REG_HDMI_DUAL_0_49_L (REG_HDMI_DUAL_0_BASE + 0x92) 5856 #define REG_HDMI_DUAL_0_49_H (REG_HDMI_DUAL_0_BASE + 0x93) 5857 #define REG_HDMI_DUAL_0_4A_L (REG_HDMI_DUAL_0_BASE + 0x94) 5858 #define REG_HDMI_DUAL_0_4A_H (REG_HDMI_DUAL_0_BASE + 0x95) 5859 #define REG_HDMI_DUAL_0_4B_L (REG_HDMI_DUAL_0_BASE + 0x96) 5860 #define REG_HDMI_DUAL_0_4B_H (REG_HDMI_DUAL_0_BASE + 0x97) 5861 #define REG_HDMI_DUAL_0_4C_L (REG_HDMI_DUAL_0_BASE + 0x98) 5862 #define REG_HDMI_DUAL_0_4C_H (REG_HDMI_DUAL_0_BASE + 0x99) 5863 #define REG_HDMI_DUAL_0_4D_L (REG_HDMI_DUAL_0_BASE + 0x9A) 5864 #define REG_HDMI_DUAL_0_4D_H (REG_HDMI_DUAL_0_BASE + 0x9B) 5865 #define REG_HDMI_DUAL_0_4E_L (REG_HDMI_DUAL_0_BASE + 0x9C) 5866 #define REG_HDMI_DUAL_0_4E_H (REG_HDMI_DUAL_0_BASE + 0x9D) 5867 #define REG_HDMI_DUAL_0_4F_L (REG_HDMI_DUAL_0_BASE + 0x9E) 5868 #define REG_HDMI_DUAL_0_4F_H (REG_HDMI_DUAL_0_BASE + 0x9F) 5869 #define REG_HDMI_DUAL_0_50_L (REG_HDMI_DUAL_0_BASE + 0xA0) 5870 #define REG_HDMI_DUAL_0_50_H (REG_HDMI_DUAL_0_BASE + 0xA1) 5871 #define REG_HDMI_DUAL_0_51_L (REG_HDMI_DUAL_0_BASE + 0xA2) 5872 #define REG_HDMI_DUAL_0_51_H (REG_HDMI_DUAL_0_BASE + 0xA3) 5873 #define REG_HDMI_DUAL_0_52_L (REG_HDMI_DUAL_0_BASE + 0xA4) 5874 #define REG_HDMI_DUAL_0_52_H (REG_HDMI_DUAL_0_BASE + 0xA5) 5875 #define REG_HDMI_DUAL_0_53_L (REG_HDMI_DUAL_0_BASE + 0xA6) 5876 #define REG_HDMI_DUAL_0_53_H (REG_HDMI_DUAL_0_BASE + 0xA7) 5877 #define REG_HDMI_DUAL_0_54_L (REG_HDMI_DUAL_0_BASE + 0xA8) 5878 #define REG_HDMI_DUAL_0_54_H (REG_HDMI_DUAL_0_BASE + 0xA9) 5879 #define REG_HDMI_DUAL_0_55_L (REG_HDMI_DUAL_0_BASE + 0xAA) 5880 #define REG_HDMI_DUAL_0_55_H (REG_HDMI_DUAL_0_BASE + 0xAB) 5881 #define REG_HDMI_DUAL_0_56_L (REG_HDMI_DUAL_0_BASE + 0xAC) 5882 #define REG_HDMI_DUAL_0_56_H (REG_HDMI_DUAL_0_BASE + 0xAD) 5883 #define REG_HDMI_DUAL_0_57_L (REG_HDMI_DUAL_0_BASE + 0xAE) 5884 #define REG_HDMI_DUAL_0_57_H (REG_HDMI_DUAL_0_BASE + 0xAF) 5885 #define REG_HDMI_DUAL_0_58_L (REG_HDMI_DUAL_0_BASE + 0xB0) 5886 #define REG_HDMI_DUAL_0_58_H (REG_HDMI_DUAL_0_BASE + 0xB1) 5887 #define REG_HDMI_DUAL_0_59_L (REG_HDMI_DUAL_0_BASE + 0xB2) 5888 #define REG_HDMI_DUAL_0_59_H (REG_HDMI_DUAL_0_BASE + 0xB3) 5889 #define REG_HDMI_DUAL_0_5A_L (REG_HDMI_DUAL_0_BASE + 0xB4) 5890 #define REG_HDMI_DUAL_0_5A_H (REG_HDMI_DUAL_0_BASE + 0xB5) 5891 #define REG_HDMI_DUAL_0_5B_L (REG_HDMI_DUAL_0_BASE + 0xB6) 5892 #define REG_HDMI_DUAL_0_5B_H (REG_HDMI_DUAL_0_BASE + 0xB7) 5893 #define REG_HDMI_DUAL_0_5C_L (REG_HDMI_DUAL_0_BASE + 0xB8) 5894 #define REG_HDMI_DUAL_0_5C_H (REG_HDMI_DUAL_0_BASE + 0xB9) 5895 #define REG_HDMI_DUAL_0_5D_L (REG_HDMI_DUAL_0_BASE + 0xBA) 5896 #define REG_HDMI_DUAL_0_5D_H (REG_HDMI_DUAL_0_BASE + 0xBB) 5897 #define REG_HDMI_DUAL_0_5E_L (REG_HDMI_DUAL_0_BASE + 0xBC) 5898 #define REG_HDMI_DUAL_0_5E_H (REG_HDMI_DUAL_0_BASE + 0xBD) 5899 #define REG_HDMI_DUAL_0_5F_L (REG_HDMI_DUAL_0_BASE + 0xBE) 5900 #define REG_HDMI_DUAL_0_5F_H (REG_HDMI_DUAL_0_BASE + 0xBF) 5901 #define REG_HDMI_DUAL_0_60_L (REG_HDMI_DUAL_0_BASE + 0xC0) 5902 #define REG_HDMI_DUAL_0_60_H (REG_HDMI_DUAL_0_BASE + 0xC1) 5903 #define REG_HDMI_DUAL_0_61_L (REG_HDMI_DUAL_0_BASE + 0xC2) 5904 #define REG_HDMI_DUAL_0_61_H (REG_HDMI_DUAL_0_BASE + 0xC3) 5905 #define REG_HDMI_DUAL_0_62_L (REG_HDMI_DUAL_0_BASE + 0xC4) 5906 #define REG_HDMI_DUAL_0_62_H (REG_HDMI_DUAL_0_BASE + 0xC5) 5907 #define REG_HDMI_DUAL_0_63_L (REG_HDMI_DUAL_0_BASE + 0xC6) 5908 #define REG_HDMI_DUAL_0_63_H (REG_HDMI_DUAL_0_BASE + 0xC7) 5909 #define REG_HDMI_DUAL_0_64_L (REG_HDMI_DUAL_0_BASE + 0xC8) 5910 #define REG_HDMI_DUAL_0_64_H (REG_HDMI_DUAL_0_BASE + 0xC9) 5911 #define REG_HDMI_DUAL_0_65_L (REG_HDMI_DUAL_0_BASE + 0xCA) 5912 #define REG_HDMI_DUAL_0_65_H (REG_HDMI_DUAL_0_BASE + 0xCB) 5913 #define REG_HDMI_DUAL_0_66_L (REG_HDMI_DUAL_0_BASE + 0xCC) 5914 #define REG_HDMI_DUAL_0_66_H (REG_HDMI_DUAL_0_BASE + 0xCD) 5915 #define REG_HDMI_DUAL_0_67_L (REG_HDMI_DUAL_0_BASE + 0xCE) 5916 #define REG_HDMI_DUAL_0_67_H (REG_HDMI_DUAL_0_BASE + 0xCF) 5917 #define REG_HDMI_DUAL_0_68_L (REG_HDMI_DUAL_0_BASE + 0xD0) 5918 #define REG_HDMI_DUAL_0_68_H (REG_HDMI_DUAL_0_BASE + 0xD1) 5919 #define REG_HDMI_DUAL_0_69_L (REG_HDMI_DUAL_0_BASE + 0xD2) 5920 #define REG_HDMI_DUAL_0_69_H (REG_HDMI_DUAL_0_BASE + 0xD3) 5921 #define REG_HDMI_DUAL_0_6A_L (REG_HDMI_DUAL_0_BASE + 0xD4) 5922 #define REG_HDMI_DUAL_0_6A_H (REG_HDMI_DUAL_0_BASE + 0xD5) 5923 #define REG_HDMI_DUAL_0_6B_L (REG_HDMI_DUAL_0_BASE + 0xD6) 5924 #define REG_HDMI_DUAL_0_6B_H (REG_HDMI_DUAL_0_BASE + 0xD7) 5925 #define REG_HDMI_DUAL_0_6C_L (REG_HDMI_DUAL_0_BASE + 0xD8) 5926 #define REG_HDMI_DUAL_0_6C_H (REG_HDMI_DUAL_0_BASE + 0xD9) 5927 #define REG_HDMI_DUAL_0_6D_L (REG_HDMI_DUAL_0_BASE + 0xDA) 5928 #define REG_HDMI_DUAL_0_6D_H (REG_HDMI_DUAL_0_BASE + 0xDB) 5929 #define REG_HDMI_DUAL_0_6E_L (REG_HDMI_DUAL_0_BASE + 0xDC) 5930 #define REG_HDMI_DUAL_0_6E_H (REG_HDMI_DUAL_0_BASE + 0xDD) 5931 #define REG_HDMI_DUAL_0_6F_L (REG_HDMI_DUAL_0_BASE + 0xDE) 5932 #define REG_HDMI_DUAL_0_6F_H (REG_HDMI_DUAL_0_BASE + 0xDF) 5933 #define REG_HDMI_DUAL_0_70_L (REG_HDMI_DUAL_0_BASE + 0xE0) 5934 #define REG_HDMI_DUAL_0_70_H (REG_HDMI_DUAL_0_BASE + 0xE1) 5935 #define REG_HDMI_DUAL_0_71_L (REG_HDMI_DUAL_0_BASE + 0xE2) 5936 #define REG_HDMI_DUAL_0_71_H (REG_HDMI_DUAL_0_BASE + 0xE3) 5937 #define REG_HDMI_DUAL_0_72_L (REG_HDMI_DUAL_0_BASE + 0xE4) 5938 #define REG_HDMI_DUAL_0_72_H (REG_HDMI_DUAL_0_BASE + 0xE5) 5939 #define REG_HDMI_DUAL_0_73_L (REG_HDMI_DUAL_0_BASE + 0xE6) 5940 #define REG_HDMI_DUAL_0_73_H (REG_HDMI_DUAL_0_BASE + 0xE7) 5941 #define REG_HDMI_DUAL_0_74_L (REG_HDMI_DUAL_0_BASE + 0xE8) 5942 #define REG_HDMI_DUAL_0_74_H (REG_HDMI_DUAL_0_BASE + 0xE9) 5943 #define REG_HDMI_DUAL_0_75_L (REG_HDMI_DUAL_0_BASE + 0xEA) 5944 #define REG_HDMI_DUAL_0_75_H (REG_HDMI_DUAL_0_BASE + 0xEB) 5945 #define REG_HDMI_DUAL_0_76_L (REG_HDMI_DUAL_0_BASE + 0xEC) 5946 #define REG_HDMI_DUAL_0_76_H (REG_HDMI_DUAL_0_BASE + 0xED) 5947 #define REG_HDMI_DUAL_0_77_L (REG_HDMI_DUAL_0_BASE + 0xEE) 5948 #define REG_HDMI_DUAL_0_77_H (REG_HDMI_DUAL_0_BASE + 0xEF) 5949 #define REG_HDMI_DUAL_0_78_L (REG_HDMI_DUAL_0_BASE + 0xF0) 5950 #define REG_HDMI_DUAL_0_78_H (REG_HDMI_DUAL_0_BASE + 0xF1) 5951 #define REG_HDMI_DUAL_0_79_L (REG_HDMI_DUAL_0_BASE + 0xF2) 5952 #define REG_HDMI_DUAL_0_79_H (REG_HDMI_DUAL_0_BASE + 0xF3) 5953 #define REG_HDMI_DUAL_0_7A_L (REG_HDMI_DUAL_0_BASE + 0xF4) 5954 #define REG_HDMI_DUAL_0_7A_H (REG_HDMI_DUAL_0_BASE + 0xF5) 5955 #define REG_HDMI_DUAL_0_7B_L (REG_HDMI_DUAL_0_BASE + 0xF6) 5956 #define REG_HDMI_DUAL_0_7B_H (REG_HDMI_DUAL_0_BASE + 0xF7) 5957 #define REG_HDMI_DUAL_0_7C_L (REG_HDMI_DUAL_0_BASE + 0xF8) 5958 #define REG_HDMI_DUAL_0_7C_H (REG_HDMI_DUAL_0_BASE + 0xF9) 5959 #define REG_HDMI_DUAL_0_7D_L (REG_HDMI_DUAL_0_BASE + 0xFA) 5960 #define REG_HDMI_DUAL_0_7D_H (REG_HDMI_DUAL_0_BASE + 0xFB) 5961 #define REG_HDMI_DUAL_0_7E_L (REG_HDMI_DUAL_0_BASE + 0xFC) 5962 #define REG_HDMI_DUAL_0_7E_H (REG_HDMI_DUAL_0_BASE + 0xFD) 5963 #define REG_HDMI_DUAL_0_7F_L (REG_HDMI_DUAL_0_BASE + 0xFE) 5964 #define REG_HDMI_DUAL_0_7F_H (REG_HDMI_DUAL_0_BASE + 0xFF) 5965 5966 // HDMI2_DUAL_0 5967 #define REG_HDMI2_DUAL_0_00_L (REG_HDMI2_DUAL_0_BASE + 0x00) 5968 #define REG_HDMI2_DUAL_0_00_H (REG_HDMI2_DUAL_0_BASE + 0x01) 5969 #define REG_HDMI2_DUAL_0_01_L (REG_HDMI2_DUAL_0_BASE + 0x02) 5970 #define REG_HDMI2_DUAL_0_01_H (REG_HDMI2_DUAL_0_BASE + 0x03) 5971 #define REG_HDMI2_DUAL_0_02_L (REG_HDMI2_DUAL_0_BASE + 0x04) 5972 #define REG_HDMI2_DUAL_0_02_H (REG_HDMI2_DUAL_0_BASE + 0x05) 5973 #define REG_HDMI2_DUAL_0_03_L (REG_HDMI2_DUAL_0_BASE + 0x06) 5974 #define REG_HDMI2_DUAL_0_03_H (REG_HDMI2_DUAL_0_BASE + 0x07) 5975 #define REG_HDMI2_DUAL_0_04_L (REG_HDMI2_DUAL_0_BASE + 0x08) 5976 #define REG_HDMI2_DUAL_0_04_H (REG_HDMI2_DUAL_0_BASE + 0x09) 5977 #define REG_HDMI2_DUAL_0_05_L (REG_HDMI2_DUAL_0_BASE + 0x0A) 5978 #define REG_HDMI2_DUAL_0_05_H (REG_HDMI2_DUAL_0_BASE + 0x0B) 5979 #define REG_HDMI2_DUAL_0_06_L (REG_HDMI2_DUAL_0_BASE + 0x0C) 5980 #define REG_HDMI2_DUAL_0_06_H (REG_HDMI2_DUAL_0_BASE + 0x0D) 5981 #define REG_HDMI2_DUAL_0_07_L (REG_HDMI2_DUAL_0_BASE + 0x0E) 5982 #define REG_HDMI2_DUAL_0_07_H (REG_HDMI2_DUAL_0_BASE + 0x0F) 5983 #define REG_HDMI2_DUAL_0_08_L (REG_HDMI2_DUAL_0_BASE + 0x10) 5984 #define REG_HDMI2_DUAL_0_08_H (REG_HDMI2_DUAL_0_BASE + 0x11) 5985 #define REG_HDMI2_DUAL_0_09_L (REG_HDMI2_DUAL_0_BASE + 0x12) 5986 #define REG_HDMI2_DUAL_0_09_H (REG_HDMI2_DUAL_0_BASE + 0x13) 5987 #define REG_HDMI2_DUAL_0_0A_L (REG_HDMI2_DUAL_0_BASE + 0x14) 5988 #define REG_HDMI2_DUAL_0_0A_H (REG_HDMI2_DUAL_0_BASE + 0x15) 5989 #define REG_HDMI2_DUAL_0_0B_L (REG_HDMI2_DUAL_0_BASE + 0x16) 5990 #define REG_HDMI2_DUAL_0_0B_H (REG_HDMI2_DUAL_0_BASE + 0x17) 5991 #define REG_HDMI2_DUAL_0_0C_L (REG_HDMI2_DUAL_0_BASE + 0x18) 5992 #define REG_HDMI2_DUAL_0_0C_H (REG_HDMI2_DUAL_0_BASE + 0x19) 5993 #define REG_HDMI2_DUAL_0_0D_L (REG_HDMI2_DUAL_0_BASE + 0x1A) 5994 #define REG_HDMI2_DUAL_0_0D_H (REG_HDMI2_DUAL_0_BASE + 0x1B) 5995 #define REG_HDMI2_DUAL_0_0E_L (REG_HDMI2_DUAL_0_BASE + 0x1C) 5996 #define REG_HDMI2_DUAL_0_0E_H (REG_HDMI2_DUAL_0_BASE + 0x1D) 5997 #define REG_HDMI2_DUAL_0_0F_L (REG_HDMI2_DUAL_0_BASE + 0x1E) 5998 #define REG_HDMI2_DUAL_0_0F_H (REG_HDMI2_DUAL_0_BASE + 0x1F) 5999 #define REG_HDMI2_DUAL_0_10_L (REG_HDMI2_DUAL_0_BASE + 0x20) 6000 #define REG_HDMI2_DUAL_0_10_H (REG_HDMI2_DUAL_0_BASE + 0x21) 6001 #define REG_HDMI2_DUAL_0_11_L (REG_HDMI2_DUAL_0_BASE + 0x22) 6002 #define REG_HDMI2_DUAL_0_11_H (REG_HDMI2_DUAL_0_BASE + 0x23) 6003 #define REG_HDMI2_DUAL_0_12_L (REG_HDMI2_DUAL_0_BASE + 0x24) 6004 #define REG_HDMI2_DUAL_0_12_H (REG_HDMI2_DUAL_0_BASE + 0x25) 6005 #define REG_HDMI2_DUAL_0_13_L (REG_HDMI2_DUAL_0_BASE + 0x26) 6006 #define REG_HDMI2_DUAL_0_13_H (REG_HDMI2_DUAL_0_BASE + 0x27) 6007 #define REG_HDMI2_DUAL_0_14_L (REG_HDMI2_DUAL_0_BASE + 0x28) 6008 #define REG_HDMI2_DUAL_0_14_H (REG_HDMI2_DUAL_0_BASE + 0x29) 6009 #define REG_HDMI2_DUAL_0_15_L (REG_HDMI2_DUAL_0_BASE + 0x2A) 6010 #define REG_HDMI2_DUAL_0_15_H (REG_HDMI2_DUAL_0_BASE + 0x2B) 6011 #define REG_HDMI2_DUAL_0_16_L (REG_HDMI2_DUAL_0_BASE + 0x2C) 6012 #define REG_HDMI2_DUAL_0_16_H (REG_HDMI2_DUAL_0_BASE + 0x2D) 6013 #define REG_HDMI2_DUAL_0_17_L (REG_HDMI2_DUAL_0_BASE + 0x2E) 6014 #define REG_HDMI2_DUAL_0_17_H (REG_HDMI2_DUAL_0_BASE + 0x2F) 6015 #define REG_HDMI2_DUAL_0_18_L (REG_HDMI2_DUAL_0_BASE + 0x30) 6016 #define REG_HDMI2_DUAL_0_18_H (REG_HDMI2_DUAL_0_BASE + 0x31) 6017 #define REG_HDMI2_DUAL_0_19_L (REG_HDMI2_DUAL_0_BASE + 0x32) 6018 #define REG_HDMI2_DUAL_0_19_H (REG_HDMI2_DUAL_0_BASE + 0x33) 6019 #define REG_HDMI2_DUAL_0_1A_L (REG_HDMI2_DUAL_0_BASE + 0x34) 6020 #define REG_HDMI2_DUAL_0_1A_H (REG_HDMI2_DUAL_0_BASE + 0x35) 6021 #define REG_HDMI2_DUAL_0_1B_L (REG_HDMI2_DUAL_0_BASE + 0x36) 6022 #define REG_HDMI2_DUAL_0_1B_H (REG_HDMI2_DUAL_0_BASE + 0x37) 6023 #define REG_HDMI2_DUAL_0_1C_L (REG_HDMI2_DUAL_0_BASE + 0x38) 6024 #define REG_HDMI2_DUAL_0_1C_H (REG_HDMI2_DUAL_0_BASE + 0x39) 6025 #define REG_HDMI2_DUAL_0_1D_L (REG_HDMI2_DUAL_0_BASE + 0x3A) 6026 #define REG_HDMI2_DUAL_0_1D_H (REG_HDMI2_DUAL_0_BASE + 0x3B) 6027 #define REG_HDMI2_DUAL_0_1E_L (REG_HDMI2_DUAL_0_BASE + 0x3C) 6028 #define REG_HDMI2_DUAL_0_1E_H (REG_HDMI2_DUAL_0_BASE + 0x3D) 6029 #define REG_HDMI2_DUAL_0_1F_L (REG_HDMI2_DUAL_0_BASE + 0x3E) 6030 #define REG_HDMI2_DUAL_0_1F_H (REG_HDMI2_DUAL_0_BASE + 0x3F) 6031 #define REG_HDMI2_DUAL_0_20_L (REG_HDMI2_DUAL_0_BASE + 0x40) 6032 #define REG_HDMI2_DUAL_0_20_H (REG_HDMI2_DUAL_0_BASE + 0x41) 6033 #define REG_HDMI2_DUAL_0_21_L (REG_HDMI2_DUAL_0_BASE + 0x42) 6034 #define REG_HDMI2_DUAL_0_21_H (REG_HDMI2_DUAL_0_BASE + 0x43) 6035 #define REG_HDMI2_DUAL_0_22_L (REG_HDMI2_DUAL_0_BASE + 0x44) 6036 #define REG_HDMI2_DUAL_0_22_H (REG_HDMI2_DUAL_0_BASE + 0x45) 6037 #define REG_HDMI2_DUAL_0_23_L (REG_HDMI2_DUAL_0_BASE + 0x46) 6038 #define REG_HDMI2_DUAL_0_23_H (REG_HDMI2_DUAL_0_BASE + 0x47) 6039 #define REG_HDMI2_DUAL_0_24_L (REG_HDMI2_DUAL_0_BASE + 0x48) 6040 #define REG_HDMI2_DUAL_0_24_H (REG_HDMI2_DUAL_0_BASE + 0x49) 6041 #define REG_HDMI2_DUAL_0_25_L (REG_HDMI2_DUAL_0_BASE + 0x4A) 6042 #define REG_HDMI2_DUAL_0_25_H (REG_HDMI2_DUAL_0_BASE + 0x4B) 6043 #define REG_HDMI2_DUAL_0_26_L (REG_HDMI2_DUAL_0_BASE + 0x4C) 6044 #define REG_HDMI2_DUAL_0_26_H (REG_HDMI2_DUAL_0_BASE + 0x4D) 6045 #define REG_HDMI2_DUAL_0_27_L (REG_HDMI2_DUAL_0_BASE + 0x4E) 6046 #define REG_HDMI2_DUAL_0_27_H (REG_HDMI2_DUAL_0_BASE + 0x4F) 6047 #define REG_HDMI2_DUAL_0_28_L (REG_HDMI2_DUAL_0_BASE + 0x50) 6048 #define REG_HDMI2_DUAL_0_28_H (REG_HDMI2_DUAL_0_BASE + 0x51) 6049 #define REG_HDMI2_DUAL_0_29_L (REG_HDMI2_DUAL_0_BASE + 0x52) 6050 #define REG_HDMI2_DUAL_0_29_H (REG_HDMI2_DUAL_0_BASE + 0x53) 6051 #define REG_HDMI2_DUAL_0_2A_L (REG_HDMI2_DUAL_0_BASE + 0x54) 6052 #define REG_HDMI2_DUAL_0_2A_H (REG_HDMI2_DUAL_0_BASE + 0x55) 6053 #define REG_HDMI2_DUAL_0_2B_L (REG_HDMI2_DUAL_0_BASE + 0x56) 6054 #define REG_HDMI2_DUAL_0_2B_H (REG_HDMI2_DUAL_0_BASE + 0x57) 6055 #define REG_HDMI2_DUAL_0_2C_L (REG_HDMI2_DUAL_0_BASE + 0x58) 6056 #define REG_HDMI2_DUAL_0_2C_H (REG_HDMI2_DUAL_0_BASE + 0x59) 6057 #define REG_HDMI2_DUAL_0_2D_L (REG_HDMI2_DUAL_0_BASE + 0x5A) 6058 #define REG_HDMI2_DUAL_0_2D_H (REG_HDMI2_DUAL_0_BASE + 0x5B) 6059 #define REG_HDMI2_DUAL_0_2E_L (REG_HDMI2_DUAL_0_BASE + 0x5C) 6060 #define REG_HDMI2_DUAL_0_2E_H (REG_HDMI2_DUAL_0_BASE + 0x5D) 6061 #define REG_HDMI2_DUAL_0_2F_L (REG_HDMI2_DUAL_0_BASE + 0x5E) 6062 #define REG_HDMI2_DUAL_0_2F_H (REG_HDMI2_DUAL_0_BASE + 0x5F) 6063 #define REG_HDMI2_DUAL_0_30_L (REG_HDMI2_DUAL_0_BASE + 0x60) 6064 #define REG_HDMI2_DUAL_0_30_H (REG_HDMI2_DUAL_0_BASE + 0x61) 6065 #define REG_HDMI2_DUAL_0_31_L (REG_HDMI2_DUAL_0_BASE + 0x62) 6066 #define REG_HDMI2_DUAL_0_31_H (REG_HDMI2_DUAL_0_BASE + 0x63) 6067 #define REG_HDMI2_DUAL_0_32_L (REG_HDMI2_DUAL_0_BASE + 0x64) 6068 #define REG_HDMI2_DUAL_0_32_H (REG_HDMI2_DUAL_0_BASE + 0x65) 6069 #define REG_HDMI2_DUAL_0_33_L (REG_HDMI2_DUAL_0_BASE + 0x66) 6070 #define REG_HDMI2_DUAL_0_33_H (REG_HDMI2_DUAL_0_BASE + 0x67) 6071 #define REG_HDMI2_DUAL_0_34_L (REG_HDMI2_DUAL_0_BASE + 0x68) 6072 #define REG_HDMI2_DUAL_0_34_H (REG_HDMI2_DUAL_0_BASE + 0x69) 6073 #define REG_HDMI2_DUAL_0_35_L (REG_HDMI2_DUAL_0_BASE + 0x6A) 6074 #define REG_HDMI2_DUAL_0_35_H (REG_HDMI2_DUAL_0_BASE + 0x6B) 6075 #define REG_HDMI2_DUAL_0_36_L (REG_HDMI2_DUAL_0_BASE + 0x6C) 6076 #define REG_HDMI2_DUAL_0_36_H (REG_HDMI2_DUAL_0_BASE + 0x6D) 6077 #define REG_HDMI2_DUAL_0_37_L (REG_HDMI2_DUAL_0_BASE + 0x6E) 6078 #define REG_HDMI2_DUAL_0_37_H (REG_HDMI2_DUAL_0_BASE + 0x6F) 6079 #define REG_HDMI2_DUAL_0_38_L (REG_HDMI2_DUAL_0_BASE + 0x70) 6080 #define REG_HDMI2_DUAL_0_38_H (REG_HDMI2_DUAL_0_BASE + 0x71) 6081 #define REG_HDMI2_DUAL_0_39_L (REG_HDMI2_DUAL_0_BASE + 0x72) 6082 #define REG_HDMI2_DUAL_0_39_H (REG_HDMI2_DUAL_0_BASE + 0x73) 6083 #define REG_HDMI2_DUAL_0_3A_L (REG_HDMI2_DUAL_0_BASE + 0x74) 6084 #define REG_HDMI2_DUAL_0_3A_H (REG_HDMI2_DUAL_0_BASE + 0x75) 6085 #define REG_HDMI2_DUAL_0_3B_L (REG_HDMI2_DUAL_0_BASE + 0x76) 6086 #define REG_HDMI2_DUAL_0_3B_H (REG_HDMI2_DUAL_0_BASE + 0x77) 6087 #define REG_HDMI2_DUAL_0_3C_L (REG_HDMI2_DUAL_0_BASE + 0x78) 6088 #define REG_HDMI2_DUAL_0_3C_H (REG_HDMI2_DUAL_0_BASE + 0x79) 6089 #define REG_HDMI2_DUAL_0_3D_L (REG_HDMI2_DUAL_0_BASE + 0x7A) 6090 #define REG_HDMI2_DUAL_0_3D_H (REG_HDMI2_DUAL_0_BASE + 0x7B) 6091 #define REG_HDMI2_DUAL_0_3E_L (REG_HDMI2_DUAL_0_BASE + 0x7C) 6092 #define REG_HDMI2_DUAL_0_3E_H (REG_HDMI2_DUAL_0_BASE + 0x7D) 6093 #define REG_HDMI2_DUAL_0_3F_L (REG_HDMI2_DUAL_0_BASE + 0x7E) 6094 #define REG_HDMI2_DUAL_0_3F_H (REG_HDMI2_DUAL_0_BASE + 0x7F) 6095 #define REG_HDMI2_DUAL_0_40_L (REG_HDMI2_DUAL_0_BASE + 0x80) 6096 #define REG_HDMI2_DUAL_0_40_H (REG_HDMI2_DUAL_0_BASE + 0x81) 6097 #define REG_HDMI2_DUAL_0_41_L (REG_HDMI2_DUAL_0_BASE + 0x82) 6098 #define REG_HDMI2_DUAL_0_41_H (REG_HDMI2_DUAL_0_BASE + 0x83) 6099 #define REG_HDMI2_DUAL_0_42_L (REG_HDMI2_DUAL_0_BASE + 0x84) 6100 #define REG_HDMI2_DUAL_0_42_H (REG_HDMI2_DUAL_0_BASE + 0x85) 6101 #define REG_HDMI2_DUAL_0_43_L (REG_HDMI2_DUAL_0_BASE + 0x86) 6102 #define REG_HDMI2_DUAL_0_43_H (REG_HDMI2_DUAL_0_BASE + 0x87) 6103 #define REG_HDMI2_DUAL_0_44_L (REG_HDMI2_DUAL_0_BASE + 0x88) 6104 #define REG_HDMI2_DUAL_0_44_H (REG_HDMI2_DUAL_0_BASE + 0x89) 6105 #define REG_HDMI2_DUAL_0_45_L (REG_HDMI2_DUAL_0_BASE + 0x8A) 6106 #define REG_HDMI2_DUAL_0_45_H (REG_HDMI2_DUAL_0_BASE + 0x8B) 6107 #define REG_HDMI2_DUAL_0_46_L (REG_HDMI2_DUAL_0_BASE + 0x8C) 6108 #define REG_HDMI2_DUAL_0_46_H (REG_HDMI2_DUAL_0_BASE + 0x8D) 6109 #define REG_HDMI2_DUAL_0_47_L (REG_HDMI2_DUAL_0_BASE + 0x8E) 6110 #define REG_HDMI2_DUAL_0_47_H (REG_HDMI2_DUAL_0_BASE + 0x8F) 6111 #define REG_HDMI2_DUAL_0_48_L (REG_HDMI2_DUAL_0_BASE + 0x90) 6112 #define REG_HDMI2_DUAL_0_48_H (REG_HDMI2_DUAL_0_BASE + 0x91) 6113 #define REG_HDMI2_DUAL_0_49_L (REG_HDMI2_DUAL_0_BASE + 0x92) 6114 #define REG_HDMI2_DUAL_0_49_H (REG_HDMI2_DUAL_0_BASE + 0x93) 6115 #define REG_HDMI2_DUAL_0_4A_L (REG_HDMI2_DUAL_0_BASE + 0x94) 6116 #define REG_HDMI2_DUAL_0_4A_H (REG_HDMI2_DUAL_0_BASE + 0x95) 6117 #define REG_HDMI2_DUAL_0_4B_L (REG_HDMI2_DUAL_0_BASE + 0x96) 6118 #define REG_HDMI2_DUAL_0_4B_H (REG_HDMI2_DUAL_0_BASE + 0x97) 6119 #define REG_HDMI2_DUAL_0_4C_L (REG_HDMI2_DUAL_0_BASE + 0x98) 6120 #define REG_HDMI2_DUAL_0_4C_H (REG_HDMI2_DUAL_0_BASE + 0x99) 6121 #define REG_HDMI2_DUAL_0_4D_L (REG_HDMI2_DUAL_0_BASE + 0x9A) 6122 #define REG_HDMI2_DUAL_0_4D_H (REG_HDMI2_DUAL_0_BASE + 0x9B) 6123 #define REG_HDMI2_DUAL_0_4E_L (REG_HDMI2_DUAL_0_BASE + 0x9C) 6124 #define REG_HDMI2_DUAL_0_4E_H (REG_HDMI2_DUAL_0_BASE + 0x9D) 6125 #define REG_HDMI2_DUAL_0_4F_L (REG_HDMI2_DUAL_0_BASE + 0x9E) 6126 #define REG_HDMI2_DUAL_0_4F_H (REG_HDMI2_DUAL_0_BASE + 0x9F) 6127 #define REG_HDMI2_DUAL_0_50_L (REG_HDMI2_DUAL_0_BASE + 0xA0) 6128 #define REG_HDMI2_DUAL_0_50_H (REG_HDMI2_DUAL_0_BASE + 0xA1) 6129 #define REG_HDMI2_DUAL_0_51_L (REG_HDMI2_DUAL_0_BASE + 0xA2) 6130 #define REG_HDMI2_DUAL_0_51_H (REG_HDMI2_DUAL_0_BASE + 0xA3) 6131 #define REG_HDMI2_DUAL_0_52_L (REG_HDMI2_DUAL_0_BASE + 0xA4) 6132 #define REG_HDMI2_DUAL_0_52_H (REG_HDMI2_DUAL_0_BASE + 0xA5) 6133 #define REG_HDMI2_DUAL_0_53_L (REG_HDMI2_DUAL_0_BASE + 0xA6) 6134 #define REG_HDMI2_DUAL_0_53_H (REG_HDMI2_DUAL_0_BASE + 0xA7) 6135 #define REG_HDMI2_DUAL_0_54_L (REG_HDMI2_DUAL_0_BASE + 0xA8) 6136 #define REG_HDMI2_DUAL_0_54_H (REG_HDMI2_DUAL_0_BASE + 0xA9) 6137 #define REG_HDMI2_DUAL_0_55_L (REG_HDMI2_DUAL_0_BASE + 0xAA) 6138 #define REG_HDMI2_DUAL_0_55_H (REG_HDMI2_DUAL_0_BASE + 0xAB) 6139 #define REG_HDMI2_DUAL_0_56_L (REG_HDMI2_DUAL_0_BASE + 0xAC) 6140 #define REG_HDMI2_DUAL_0_56_H (REG_HDMI2_DUAL_0_BASE + 0xAD) 6141 #define REG_HDMI2_DUAL_0_57_L (REG_HDMI2_DUAL_0_BASE + 0xAE) 6142 #define REG_HDMI2_DUAL_0_57_H (REG_HDMI2_DUAL_0_BASE + 0xAF) 6143 #define REG_HDMI2_DUAL_0_58_L (REG_HDMI2_DUAL_0_BASE + 0xB0) 6144 #define REG_HDMI2_DUAL_0_58_H (REG_HDMI2_DUAL_0_BASE + 0xB1) 6145 #define REG_HDMI2_DUAL_0_59_L (REG_HDMI2_DUAL_0_BASE + 0xB2) 6146 #define REG_HDMI2_DUAL_0_59_H (REG_HDMI2_DUAL_0_BASE + 0xB3) 6147 #define REG_HDMI2_DUAL_0_5A_L (REG_HDMI2_DUAL_0_BASE + 0xB4) 6148 #define REG_HDMI2_DUAL_0_5A_H (REG_HDMI2_DUAL_0_BASE + 0xB5) 6149 #define REG_HDMI2_DUAL_0_5B_L (REG_HDMI2_DUAL_0_BASE + 0xB6) 6150 #define REG_HDMI2_DUAL_0_5B_H (REG_HDMI2_DUAL_0_BASE + 0xB7) 6151 #define REG_HDMI2_DUAL_0_5C_L (REG_HDMI2_DUAL_0_BASE + 0xB8) 6152 #define REG_HDMI2_DUAL_0_5C_H (REG_HDMI2_DUAL_0_BASE + 0xB9) 6153 #define REG_HDMI2_DUAL_0_5D_L (REG_HDMI2_DUAL_0_BASE + 0xBA) 6154 #define REG_HDMI2_DUAL_0_5D_H (REG_HDMI2_DUAL_0_BASE + 0xBB) 6155 #define REG_HDMI2_DUAL_0_5E_L (REG_HDMI2_DUAL_0_BASE + 0xBC) 6156 #define REG_HDMI2_DUAL_0_5E_H (REG_HDMI2_DUAL_0_BASE + 0xBD) 6157 #define REG_HDMI2_DUAL_0_5F_L (REG_HDMI2_DUAL_0_BASE + 0xBE) 6158 #define REG_HDMI2_DUAL_0_5F_H (REG_HDMI2_DUAL_0_BASE + 0xBF) 6159 #define REG_HDMI2_DUAL_0_60_L (REG_HDMI2_DUAL_0_BASE + 0xC0) 6160 #define REG_HDMI2_DUAL_0_60_H (REG_HDMI2_DUAL_0_BASE + 0xC1) 6161 #define REG_HDMI2_DUAL_0_61_L (REG_HDMI2_DUAL_0_BASE + 0xC2) 6162 #define REG_HDMI2_DUAL_0_61_H (REG_HDMI2_DUAL_0_BASE + 0xC3) 6163 #define REG_HDMI2_DUAL_0_62_L (REG_HDMI2_DUAL_0_BASE + 0xC4) 6164 #define REG_HDMI2_DUAL_0_62_H (REG_HDMI2_DUAL_0_BASE + 0xC5) 6165 #define REG_HDMI2_DUAL_0_63_L (REG_HDMI2_DUAL_0_BASE + 0xC6) 6166 #define REG_HDMI2_DUAL_0_63_H (REG_HDMI2_DUAL_0_BASE + 0xC7) 6167 #define REG_HDMI2_DUAL_0_64_L (REG_HDMI2_DUAL_0_BASE + 0xC8) 6168 #define REG_HDMI2_DUAL_0_64_H (REG_HDMI2_DUAL_0_BASE + 0xC9) 6169 #define REG_HDMI2_DUAL_0_65_L (REG_HDMI2_DUAL_0_BASE + 0xCA) 6170 #define REG_HDMI2_DUAL_0_65_H (REG_HDMI2_DUAL_0_BASE + 0xCB) 6171 #define REG_HDMI2_DUAL_0_66_L (REG_HDMI2_DUAL_0_BASE + 0xCC) 6172 #define REG_HDMI2_DUAL_0_66_H (REG_HDMI2_DUAL_0_BASE + 0xCD) 6173 #define REG_HDMI2_DUAL_0_67_L (REG_HDMI2_DUAL_0_BASE + 0xCE) 6174 #define REG_HDMI2_DUAL_0_67_H (REG_HDMI2_DUAL_0_BASE + 0xCF) 6175 #define REG_HDMI2_DUAL_0_68_L (REG_HDMI2_DUAL_0_BASE + 0xD0) 6176 #define REG_HDMI2_DUAL_0_68_H (REG_HDMI2_DUAL_0_BASE + 0xD1) 6177 #define REG_HDMI2_DUAL_0_69_L (REG_HDMI2_DUAL_0_BASE + 0xD2) 6178 #define REG_HDMI2_DUAL_0_69_H (REG_HDMI2_DUAL_0_BASE + 0xD3) 6179 #define REG_HDMI2_DUAL_0_6A_L (REG_HDMI2_DUAL_0_BASE + 0xD4) 6180 #define REG_HDMI2_DUAL_0_6A_H (REG_HDMI2_DUAL_0_BASE + 0xD5) 6181 #define REG_HDMI2_DUAL_0_6B_L (REG_HDMI2_DUAL_0_BASE + 0xD6) 6182 #define REG_HDMI2_DUAL_0_6B_H (REG_HDMI2_DUAL_0_BASE + 0xD7) 6183 #define REG_HDMI2_DUAL_0_6C_L (REG_HDMI2_DUAL_0_BASE + 0xD8) 6184 #define REG_HDMI2_DUAL_0_6C_H (REG_HDMI2_DUAL_0_BASE + 0xD9) 6185 #define REG_HDMI2_DUAL_0_6D_L (REG_HDMI2_DUAL_0_BASE + 0xDA) 6186 #define REG_HDMI2_DUAL_0_6D_H (REG_HDMI2_DUAL_0_BASE + 0xDB) 6187 #define REG_HDMI2_DUAL_0_6E_L (REG_HDMI2_DUAL_0_BASE + 0xDC) 6188 #define REG_HDMI2_DUAL_0_6E_H (REG_HDMI2_DUAL_0_BASE + 0xDD) 6189 #define REG_HDMI2_DUAL_0_6F_L (REG_HDMI2_DUAL_0_BASE + 0xDE) 6190 #define REG_HDMI2_DUAL_0_6F_H (REG_HDMI2_DUAL_0_BASE + 0xDF) 6191 #define REG_HDMI2_DUAL_0_70_L (REG_HDMI2_DUAL_0_BASE + 0xE0) 6192 #define REG_HDMI2_DUAL_0_70_H (REG_HDMI2_DUAL_0_BASE + 0xE1) 6193 #define REG_HDMI2_DUAL_0_71_L (REG_HDMI2_DUAL_0_BASE + 0xE2) 6194 #define REG_HDMI2_DUAL_0_71_H (REG_HDMI2_DUAL_0_BASE + 0xE3) 6195 #define REG_HDMI2_DUAL_0_72_L (REG_HDMI2_DUAL_0_BASE + 0xE4) 6196 #define REG_HDMI2_DUAL_0_72_H (REG_HDMI2_DUAL_0_BASE + 0xE5) 6197 #define REG_HDMI2_DUAL_0_73_L (REG_HDMI2_DUAL_0_BASE + 0xE6) 6198 #define REG_HDMI2_DUAL_0_73_H (REG_HDMI2_DUAL_0_BASE + 0xE7) 6199 #define REG_HDMI2_DUAL_0_74_L (REG_HDMI2_DUAL_0_BASE + 0xE8) 6200 #define REG_HDMI2_DUAL_0_74_H (REG_HDMI2_DUAL_0_BASE + 0xE9) 6201 #define REG_HDMI2_DUAL_0_75_L (REG_HDMI2_DUAL_0_BASE + 0xEA) 6202 #define REG_HDMI2_DUAL_0_75_H (REG_HDMI2_DUAL_0_BASE + 0xEB) 6203 #define REG_HDMI2_DUAL_0_76_L (REG_HDMI2_DUAL_0_BASE + 0xEC) 6204 #define REG_HDMI2_DUAL_0_76_H (REG_HDMI2_DUAL_0_BASE + 0xED) 6205 #define REG_HDMI2_DUAL_0_77_L (REG_HDMI2_DUAL_0_BASE + 0xEE) 6206 #define REG_HDMI2_DUAL_0_77_H (REG_HDMI2_DUAL_0_BASE + 0xEF) 6207 #define REG_HDMI2_DUAL_0_78_L (REG_HDMI2_DUAL_0_BASE + 0xF0) 6208 #define REG_HDMI2_DUAL_0_78_H (REG_HDMI2_DUAL_0_BASE + 0xF1) 6209 #define REG_HDMI2_DUAL_0_79_L (REG_HDMI2_DUAL_0_BASE + 0xF2) 6210 #define REG_HDMI2_DUAL_0_79_H (REG_HDMI2_DUAL_0_BASE + 0xF3) 6211 #define REG_HDMI2_DUAL_0_7A_L (REG_HDMI2_DUAL_0_BASE + 0xF4) 6212 #define REG_HDMI2_DUAL_0_7A_H (REG_HDMI2_DUAL_0_BASE + 0xF5) 6213 #define REG_HDMI2_DUAL_0_7B_L (REG_HDMI2_DUAL_0_BASE + 0xF6) 6214 #define REG_HDMI2_DUAL_0_7B_H (REG_HDMI2_DUAL_0_BASE + 0xF7) 6215 #define REG_HDMI2_DUAL_0_7C_L (REG_HDMI2_DUAL_0_BASE + 0xF8) 6216 #define REG_HDMI2_DUAL_0_7C_H (REG_HDMI2_DUAL_0_BASE + 0xF9) 6217 #define REG_HDMI2_DUAL_0_7D_L (REG_HDMI2_DUAL_0_BASE + 0xFA) 6218 #define REG_HDMI2_DUAL_0_7D_H (REG_HDMI2_DUAL_0_BASE + 0xFB) 6219 #define REG_HDMI2_DUAL_0_7E_L (REG_HDMI2_DUAL_0_BASE + 0xFC) 6220 #define REG_HDMI2_DUAL_0_7E_H (REG_HDMI2_DUAL_0_BASE + 0xFD) 6221 #define REG_HDMI2_DUAL_0_7F_L (REG_HDMI2_DUAL_0_BASE + 0xFE) 6222 #define REG_HDMI2_DUAL_0_7F_H (REG_HDMI2_DUAL_0_BASE + 0xFF) 6223 6224 // HDMI3_DUAL_0 6225 #define REG_HDMI3_DUAL_0_00_L (REG_HDMI3_DUAL_0_BASE + 0x00) 6226 #define REG_HDMI3_DUAL_0_00_H (REG_HDMI3_DUAL_0_BASE + 0x01) 6227 #define REG_HDMI3_DUAL_0_01_L (REG_HDMI3_DUAL_0_BASE + 0x02) 6228 #define REG_HDMI3_DUAL_0_01_H (REG_HDMI3_DUAL_0_BASE + 0x03) 6229 #define REG_HDMI3_DUAL_0_02_L (REG_HDMI3_DUAL_0_BASE + 0x04) 6230 #define REG_HDMI3_DUAL_0_02_H (REG_HDMI3_DUAL_0_BASE + 0x05) 6231 #define REG_HDMI3_DUAL_0_03_L (REG_HDMI3_DUAL_0_BASE + 0x06) 6232 #define REG_HDMI3_DUAL_0_03_H (REG_HDMI3_DUAL_0_BASE + 0x07) 6233 #define REG_HDMI3_DUAL_0_04_L (REG_HDMI3_DUAL_0_BASE + 0x08) 6234 #define REG_HDMI3_DUAL_0_04_H (REG_HDMI3_DUAL_0_BASE + 0x09) 6235 #define REG_HDMI3_DUAL_0_05_L (REG_HDMI3_DUAL_0_BASE + 0x0A) 6236 #define REG_HDMI3_DUAL_0_05_H (REG_HDMI3_DUAL_0_BASE + 0x0B) 6237 #define REG_HDMI3_DUAL_0_06_L (REG_HDMI3_DUAL_0_BASE + 0x0C) 6238 #define REG_HDMI3_DUAL_0_06_H (REG_HDMI3_DUAL_0_BASE + 0x0D) 6239 #define REG_HDMI3_DUAL_0_07_L (REG_HDMI3_DUAL_0_BASE + 0x0E) 6240 #define REG_HDMI3_DUAL_0_07_H (REG_HDMI3_DUAL_0_BASE + 0x0F) 6241 #define REG_HDMI3_DUAL_0_08_L (REG_HDMI3_DUAL_0_BASE + 0x10) 6242 #define REG_HDMI3_DUAL_0_08_H (REG_HDMI3_DUAL_0_BASE + 0x11) 6243 #define REG_HDMI3_DUAL_0_09_L (REG_HDMI3_DUAL_0_BASE + 0x12) 6244 #define REG_HDMI3_DUAL_0_09_H (REG_HDMI3_DUAL_0_BASE + 0x13) 6245 #define REG_HDMI3_DUAL_0_0A_L (REG_HDMI3_DUAL_0_BASE + 0x14) 6246 #define REG_HDMI3_DUAL_0_0A_H (REG_HDMI3_DUAL_0_BASE + 0x15) 6247 #define REG_HDMI3_DUAL_0_0B_L (REG_HDMI3_DUAL_0_BASE + 0x16) 6248 #define REG_HDMI3_DUAL_0_0B_H (REG_HDMI3_DUAL_0_BASE + 0x17) 6249 #define REG_HDMI3_DUAL_0_0C_L (REG_HDMI3_DUAL_0_BASE + 0x18) 6250 #define REG_HDMI3_DUAL_0_0C_H (REG_HDMI3_DUAL_0_BASE + 0x19) 6251 #define REG_HDMI3_DUAL_0_0D_L (REG_HDMI3_DUAL_0_BASE + 0x1A) 6252 #define REG_HDMI3_DUAL_0_0D_H (REG_HDMI3_DUAL_0_BASE + 0x1B) 6253 #define REG_HDMI3_DUAL_0_0E_L (REG_HDMI3_DUAL_0_BASE + 0x1C) 6254 #define REG_HDMI3_DUAL_0_0E_H (REG_HDMI3_DUAL_0_BASE + 0x1D) 6255 #define REG_HDMI3_DUAL_0_0F_L (REG_HDMI3_DUAL_0_BASE + 0x1E) 6256 #define REG_HDMI3_DUAL_0_0F_H (REG_HDMI3_DUAL_0_BASE + 0x1F) 6257 #define REG_HDMI3_DUAL_0_10_L (REG_HDMI3_DUAL_0_BASE + 0x20) 6258 #define REG_HDMI3_DUAL_0_10_H (REG_HDMI3_DUAL_0_BASE + 0x21) 6259 #define REG_HDMI3_DUAL_0_11_L (REG_HDMI3_DUAL_0_BASE + 0x22) 6260 #define REG_HDMI3_DUAL_0_11_H (REG_HDMI3_DUAL_0_BASE + 0x23) 6261 #define REG_HDMI3_DUAL_0_12_L (REG_HDMI3_DUAL_0_BASE + 0x24) 6262 #define REG_HDMI3_DUAL_0_12_H (REG_HDMI3_DUAL_0_BASE + 0x25) 6263 #define REG_HDMI3_DUAL_0_13_L (REG_HDMI3_DUAL_0_BASE + 0x26) 6264 #define REG_HDMI3_DUAL_0_13_H (REG_HDMI3_DUAL_0_BASE + 0x27) 6265 #define REG_HDMI3_DUAL_0_14_L (REG_HDMI3_DUAL_0_BASE + 0x28) 6266 #define REG_HDMI3_DUAL_0_14_H (REG_HDMI3_DUAL_0_BASE + 0x29) 6267 #define REG_HDMI3_DUAL_0_15_L (REG_HDMI3_DUAL_0_BASE + 0x2A) 6268 #define REG_HDMI3_DUAL_0_15_H (REG_HDMI3_DUAL_0_BASE + 0x2B) 6269 #define REG_HDMI3_DUAL_0_16_L (REG_HDMI3_DUAL_0_BASE + 0x2C) 6270 #define REG_HDMI3_DUAL_0_16_H (REG_HDMI3_DUAL_0_BASE + 0x2D) 6271 #define REG_HDMI3_DUAL_0_17_L (REG_HDMI3_DUAL_0_BASE + 0x2E) 6272 #define REG_HDMI3_DUAL_0_17_H (REG_HDMI3_DUAL_0_BASE + 0x2F) 6273 #define REG_HDMI3_DUAL_0_18_L (REG_HDMI3_DUAL_0_BASE + 0x30) 6274 #define REG_HDMI3_DUAL_0_18_H (REG_HDMI3_DUAL_0_BASE + 0x31) 6275 #define REG_HDMI3_DUAL_0_19_L (REG_HDMI3_DUAL_0_BASE + 0x32) 6276 #define REG_HDMI3_DUAL_0_19_H (REG_HDMI3_DUAL_0_BASE + 0x33) 6277 #define REG_HDMI3_DUAL_0_1A_L (REG_HDMI3_DUAL_0_BASE + 0x34) 6278 #define REG_HDMI3_DUAL_0_1A_H (REG_HDMI3_DUAL_0_BASE + 0x35) 6279 #define REG_HDMI3_DUAL_0_1B_L (REG_HDMI3_DUAL_0_BASE + 0x36) 6280 #define REG_HDMI3_DUAL_0_1B_H (REG_HDMI3_DUAL_0_BASE + 0x37) 6281 #define REG_HDMI3_DUAL_0_1C_L (REG_HDMI3_DUAL_0_BASE + 0x38) 6282 #define REG_HDMI3_DUAL_0_1C_H (REG_HDMI3_DUAL_0_BASE + 0x39) 6283 #define REG_HDMI3_DUAL_0_1D_L (REG_HDMI3_DUAL_0_BASE + 0x3A) 6284 #define REG_HDMI3_DUAL_0_1D_H (REG_HDMI3_DUAL_0_BASE + 0x3B) 6285 #define REG_HDMI3_DUAL_0_1E_L (REG_HDMI3_DUAL_0_BASE + 0x3C) 6286 #define REG_HDMI3_DUAL_0_1E_H (REG_HDMI3_DUAL_0_BASE + 0x3D) 6287 #define REG_HDMI3_DUAL_0_1F_L (REG_HDMI3_DUAL_0_BASE + 0x3E) 6288 #define REG_HDMI3_DUAL_0_1F_H (REG_HDMI3_DUAL_0_BASE + 0x3F) 6289 #define REG_HDMI3_DUAL_0_20_L (REG_HDMI3_DUAL_0_BASE + 0x40) 6290 #define REG_HDMI3_DUAL_0_20_H (REG_HDMI3_DUAL_0_BASE + 0x41) 6291 #define REG_HDMI3_DUAL_0_21_L (REG_HDMI3_DUAL_0_BASE + 0x42) 6292 #define REG_HDMI3_DUAL_0_21_H (REG_HDMI3_DUAL_0_BASE + 0x43) 6293 #define REG_HDMI3_DUAL_0_22_L (REG_HDMI3_DUAL_0_BASE + 0x44) 6294 #define REG_HDMI3_DUAL_0_22_H (REG_HDMI3_DUAL_0_BASE + 0x45) 6295 #define REG_HDMI3_DUAL_0_23_L (REG_HDMI3_DUAL_0_BASE + 0x46) 6296 #define REG_HDMI3_DUAL_0_23_H (REG_HDMI3_DUAL_0_BASE + 0x47) 6297 #define REG_HDMI3_DUAL_0_24_L (REG_HDMI3_DUAL_0_BASE + 0x48) 6298 #define REG_HDMI3_DUAL_0_24_H (REG_HDMI3_DUAL_0_BASE + 0x49) 6299 #define REG_HDMI3_DUAL_0_25_L (REG_HDMI3_DUAL_0_BASE + 0x4A) 6300 #define REG_HDMI3_DUAL_0_25_H (REG_HDMI3_DUAL_0_BASE + 0x4B) 6301 #define REG_HDMI3_DUAL_0_26_L (REG_HDMI3_DUAL_0_BASE + 0x4C) 6302 #define REG_HDMI3_DUAL_0_26_H (REG_HDMI3_DUAL_0_BASE + 0x4D) 6303 #define REG_HDMI3_DUAL_0_27_L (REG_HDMI3_DUAL_0_BASE + 0x4E) 6304 #define REG_HDMI3_DUAL_0_27_H (REG_HDMI3_DUAL_0_BASE + 0x4F) 6305 #define REG_HDMI3_DUAL_0_28_L (REG_HDMI3_DUAL_0_BASE + 0x50) 6306 #define REG_HDMI3_DUAL_0_28_H (REG_HDMI3_DUAL_0_BASE + 0x51) 6307 #define REG_HDMI3_DUAL_0_29_L (REG_HDMI3_DUAL_0_BASE + 0x52) 6308 #define REG_HDMI3_DUAL_0_29_H (REG_HDMI3_DUAL_0_BASE + 0x53) 6309 #define REG_HDMI3_DUAL_0_2A_L (REG_HDMI3_DUAL_0_BASE + 0x54) 6310 #define REG_HDMI3_DUAL_0_2A_H (REG_HDMI3_DUAL_0_BASE + 0x55) 6311 #define REG_HDMI3_DUAL_0_2B_L (REG_HDMI3_DUAL_0_BASE + 0x56) 6312 #define REG_HDMI3_DUAL_0_2B_H (REG_HDMI3_DUAL_0_BASE + 0x57) 6313 #define REG_HDMI3_DUAL_0_2C_L (REG_HDMI3_DUAL_0_BASE + 0x58) 6314 #define REG_HDMI3_DUAL_0_2C_H (REG_HDMI3_DUAL_0_BASE + 0x59) 6315 #define REG_HDMI3_DUAL_0_2D_L (REG_HDMI3_DUAL_0_BASE + 0x5A) 6316 #define REG_HDMI3_DUAL_0_2D_H (REG_HDMI3_DUAL_0_BASE + 0x5B) 6317 #define REG_HDMI3_DUAL_0_2E_L (REG_HDMI3_DUAL_0_BASE + 0x5C) 6318 #define REG_HDMI3_DUAL_0_2E_H (REG_HDMI3_DUAL_0_BASE + 0x5D) 6319 #define REG_HDMI3_DUAL_0_2F_L (REG_HDMI3_DUAL_0_BASE + 0x5E) 6320 #define REG_HDMI3_DUAL_0_2F_H (REG_HDMI3_DUAL_0_BASE + 0x5F) 6321 #define REG_HDMI3_DUAL_0_30_L (REG_HDMI3_DUAL_0_BASE + 0x60) 6322 #define REG_HDMI3_DUAL_0_30_H (REG_HDMI3_DUAL_0_BASE + 0x61) 6323 #define REG_HDMI3_DUAL_0_31_L (REG_HDMI3_DUAL_0_BASE + 0x62) 6324 #define REG_HDMI3_DUAL_0_31_H (REG_HDMI3_DUAL_0_BASE + 0x63) 6325 #define REG_HDMI3_DUAL_0_32_L (REG_HDMI3_DUAL_0_BASE + 0x64) 6326 #define REG_HDMI3_DUAL_0_32_H (REG_HDMI3_DUAL_0_BASE + 0x65) 6327 #define REG_HDMI3_DUAL_0_33_L (REG_HDMI3_DUAL_0_BASE + 0x66) 6328 #define REG_HDMI3_DUAL_0_33_H (REG_HDMI3_DUAL_0_BASE + 0x67) 6329 #define REG_HDMI3_DUAL_0_34_L (REG_HDMI3_DUAL_0_BASE + 0x68) 6330 #define REG_HDMI3_DUAL_0_34_H (REG_HDMI3_DUAL_0_BASE + 0x69) 6331 #define REG_HDMI3_DUAL_0_35_L (REG_HDMI3_DUAL_0_BASE + 0x6A) 6332 #define REG_HDMI3_DUAL_0_35_H (REG_HDMI3_DUAL_0_BASE + 0x6B) 6333 #define REG_HDMI3_DUAL_0_36_L (REG_HDMI3_DUAL_0_BASE + 0x6C) 6334 #define REG_HDMI3_DUAL_0_36_H (REG_HDMI3_DUAL_0_BASE + 0x6D) 6335 #define REG_HDMI3_DUAL_0_37_L (REG_HDMI3_DUAL_0_BASE + 0x6E) 6336 #define REG_HDMI3_DUAL_0_37_H (REG_HDMI3_DUAL_0_BASE + 0x6F) 6337 #define REG_HDMI3_DUAL_0_38_L (REG_HDMI3_DUAL_0_BASE + 0x70) 6338 #define REG_HDMI3_DUAL_0_38_H (REG_HDMI3_DUAL_0_BASE + 0x71) 6339 #define REG_HDMI3_DUAL_0_39_L (REG_HDMI3_DUAL_0_BASE + 0x72) 6340 #define REG_HDMI3_DUAL_0_39_H (REG_HDMI3_DUAL_0_BASE + 0x73) 6341 #define REG_HDMI3_DUAL_0_3A_L (REG_HDMI3_DUAL_0_BASE + 0x74) 6342 #define REG_HDMI3_DUAL_0_3A_H (REG_HDMI3_DUAL_0_BASE + 0x75) 6343 #define REG_HDMI3_DUAL_0_3B_L (REG_HDMI3_DUAL_0_BASE + 0x76) 6344 #define REG_HDMI3_DUAL_0_3B_H (REG_HDMI3_DUAL_0_BASE + 0x77) 6345 #define REG_HDMI3_DUAL_0_3C_L (REG_HDMI3_DUAL_0_BASE + 0x78) 6346 #define REG_HDMI3_DUAL_0_3C_H (REG_HDMI3_DUAL_0_BASE + 0x79) 6347 #define REG_HDMI3_DUAL_0_3D_L (REG_HDMI3_DUAL_0_BASE + 0x7A) 6348 #define REG_HDMI3_DUAL_0_3D_H (REG_HDMI3_DUAL_0_BASE + 0x7B) 6349 #define REG_HDMI3_DUAL_0_3E_L (REG_HDMI3_DUAL_0_BASE + 0x7C) 6350 #define REG_HDMI3_DUAL_0_3E_H (REG_HDMI3_DUAL_0_BASE + 0x7D) 6351 #define REG_HDMI3_DUAL_0_3F_L (REG_HDMI3_DUAL_0_BASE + 0x7E) 6352 #define REG_HDMI3_DUAL_0_3F_H (REG_HDMI3_DUAL_0_BASE + 0x7F) 6353 #define REG_HDMI3_DUAL_0_40_L (REG_HDMI3_DUAL_0_BASE + 0x80) 6354 #define REG_HDMI3_DUAL_0_40_H (REG_HDMI3_DUAL_0_BASE + 0x81) 6355 #define REG_HDMI3_DUAL_0_41_L (REG_HDMI3_DUAL_0_BASE + 0x82) 6356 #define REG_HDMI3_DUAL_0_41_H (REG_HDMI3_DUAL_0_BASE + 0x83) 6357 #define REG_HDMI3_DUAL_0_42_L (REG_HDMI3_DUAL_0_BASE + 0x84) 6358 #define REG_HDMI3_DUAL_0_42_H (REG_HDMI3_DUAL_0_BASE + 0x85) 6359 #define REG_HDMI3_DUAL_0_43_L (REG_HDMI3_DUAL_0_BASE + 0x86) 6360 #define REG_HDMI3_DUAL_0_43_H (REG_HDMI3_DUAL_0_BASE + 0x87) 6361 #define REG_HDMI3_DUAL_0_44_L (REG_HDMI3_DUAL_0_BASE + 0x88) 6362 #define REG_HDMI3_DUAL_0_44_H (REG_HDMI3_DUAL_0_BASE + 0x89) 6363 #define REG_HDMI3_DUAL_0_45_L (REG_HDMI3_DUAL_0_BASE + 0x8A) 6364 #define REG_HDMI3_DUAL_0_45_H (REG_HDMI3_DUAL_0_BASE + 0x8B) 6365 #define REG_HDMI3_DUAL_0_46_L (REG_HDMI3_DUAL_0_BASE + 0x8C) 6366 #define REG_HDMI3_DUAL_0_46_H (REG_HDMI3_DUAL_0_BASE + 0x8D) 6367 #define REG_HDMI3_DUAL_0_47_L (REG_HDMI3_DUAL_0_BASE + 0x8E) 6368 #define REG_HDMI3_DUAL_0_47_H (REG_HDMI3_DUAL_0_BASE + 0x8F) 6369 #define REG_HDMI3_DUAL_0_48_L (REG_HDMI3_DUAL_0_BASE + 0x90) 6370 #define REG_HDMI3_DUAL_0_48_H (REG_HDMI3_DUAL_0_BASE + 0x91) 6371 #define REG_HDMI3_DUAL_0_49_L (REG_HDMI3_DUAL_0_BASE + 0x92) 6372 #define REG_HDMI3_DUAL_0_49_H (REG_HDMI3_DUAL_0_BASE + 0x93) 6373 #define REG_HDMI3_DUAL_0_4A_L (REG_HDMI3_DUAL_0_BASE + 0x94) 6374 #define REG_HDMI3_DUAL_0_4A_H (REG_HDMI3_DUAL_0_BASE + 0x95) 6375 #define REG_HDMI3_DUAL_0_4B_L (REG_HDMI3_DUAL_0_BASE + 0x96) 6376 #define REG_HDMI3_DUAL_0_4B_H (REG_HDMI3_DUAL_0_BASE + 0x97) 6377 #define REG_HDMI3_DUAL_0_4C_L (REG_HDMI3_DUAL_0_BASE + 0x98) 6378 #define REG_HDMI3_DUAL_0_4C_H (REG_HDMI3_DUAL_0_BASE + 0x99) 6379 #define REG_HDMI3_DUAL_0_4D_L (REG_HDMI3_DUAL_0_BASE + 0x9A) 6380 #define REG_HDMI3_DUAL_0_4D_H (REG_HDMI3_DUAL_0_BASE + 0x9B) 6381 #define REG_HDMI3_DUAL_0_4E_L (REG_HDMI3_DUAL_0_BASE + 0x9C) 6382 #define REG_HDMI3_DUAL_0_4E_H (REG_HDMI3_DUAL_0_BASE + 0x9D) 6383 #define REG_HDMI3_DUAL_0_4F_L (REG_HDMI3_DUAL_0_BASE + 0x9E) 6384 #define REG_HDMI3_DUAL_0_4F_H (REG_HDMI3_DUAL_0_BASE + 0x9F) 6385 #define REG_HDMI3_DUAL_0_50_L (REG_HDMI3_DUAL_0_BASE + 0xA0) 6386 #define REG_HDMI3_DUAL_0_50_H (REG_HDMI3_DUAL_0_BASE + 0xA1) 6387 #define REG_HDMI3_DUAL_0_51_L (REG_HDMI3_DUAL_0_BASE + 0xA2) 6388 #define REG_HDMI3_DUAL_0_51_H (REG_HDMI3_DUAL_0_BASE + 0xA3) 6389 #define REG_HDMI3_DUAL_0_52_L (REG_HDMI3_DUAL_0_BASE + 0xA4) 6390 #define REG_HDMI3_DUAL_0_52_H (REG_HDMI3_DUAL_0_BASE + 0xA5) 6391 #define REG_HDMI3_DUAL_0_53_L (REG_HDMI3_DUAL_0_BASE + 0xA6) 6392 #define REG_HDMI3_DUAL_0_53_H (REG_HDMI3_DUAL_0_BASE + 0xA7) 6393 #define REG_HDMI3_DUAL_0_54_L (REG_HDMI3_DUAL_0_BASE + 0xA8) 6394 #define REG_HDMI3_DUAL_0_54_H (REG_HDMI3_DUAL_0_BASE + 0xA9) 6395 #define REG_HDMI3_DUAL_0_55_L (REG_HDMI3_DUAL_0_BASE + 0xAA) 6396 #define REG_HDMI3_DUAL_0_55_H (REG_HDMI3_DUAL_0_BASE + 0xAB) 6397 #define REG_HDMI3_DUAL_0_56_L (REG_HDMI3_DUAL_0_BASE + 0xAC) 6398 #define REG_HDMI3_DUAL_0_56_H (REG_HDMI3_DUAL_0_BASE + 0xAD) 6399 #define REG_HDMI3_DUAL_0_57_L (REG_HDMI3_DUAL_0_BASE + 0xAE) 6400 #define REG_HDMI3_DUAL_0_57_H (REG_HDMI3_DUAL_0_BASE + 0xAF) 6401 #define REG_HDMI3_DUAL_0_58_L (REG_HDMI3_DUAL_0_BASE + 0xB0) 6402 #define REG_HDMI3_DUAL_0_58_H (REG_HDMI3_DUAL_0_BASE + 0xB1) 6403 #define REG_HDMI3_DUAL_0_59_L (REG_HDMI3_DUAL_0_BASE + 0xB2) 6404 #define REG_HDMI3_DUAL_0_59_H (REG_HDMI3_DUAL_0_BASE + 0xB3) 6405 #define REG_HDMI3_DUAL_0_5A_L (REG_HDMI3_DUAL_0_BASE + 0xB4) 6406 #define REG_HDMI3_DUAL_0_5A_H (REG_HDMI3_DUAL_0_BASE + 0xB5) 6407 #define REG_HDMI3_DUAL_0_5B_L (REG_HDMI3_DUAL_0_BASE + 0xB6) 6408 #define REG_HDMI3_DUAL_0_5B_H (REG_HDMI3_DUAL_0_BASE + 0xB7) 6409 #define REG_HDMI3_DUAL_0_5C_L (REG_HDMI3_DUAL_0_BASE + 0xB8) 6410 #define REG_HDMI3_DUAL_0_5C_H (REG_HDMI3_DUAL_0_BASE + 0xB9) 6411 #define REG_HDMI3_DUAL_0_5D_L (REG_HDMI3_DUAL_0_BASE + 0xBA) 6412 #define REG_HDMI3_DUAL_0_5D_H (REG_HDMI3_DUAL_0_BASE + 0xBB) 6413 #define REG_HDMI3_DUAL_0_5E_L (REG_HDMI3_DUAL_0_BASE + 0xBC) 6414 #define REG_HDMI3_DUAL_0_5E_H (REG_HDMI3_DUAL_0_BASE + 0xBD) 6415 #define REG_HDMI3_DUAL_0_5F_L (REG_HDMI3_DUAL_0_BASE + 0xBE) 6416 #define REG_HDMI3_DUAL_0_5F_H (REG_HDMI3_DUAL_0_BASE + 0xBF) 6417 #define REG_HDMI3_DUAL_0_60_L (REG_HDMI3_DUAL_0_BASE + 0xC0) 6418 #define REG_HDMI3_DUAL_0_60_H (REG_HDMI3_DUAL_0_BASE + 0xC1) 6419 #define REG_HDMI3_DUAL_0_61_L (REG_HDMI3_DUAL_0_BASE + 0xC2) 6420 #define REG_HDMI3_DUAL_0_61_H (REG_HDMI3_DUAL_0_BASE + 0xC3) 6421 #define REG_HDMI3_DUAL_0_62_L (REG_HDMI3_DUAL_0_BASE + 0xC4) 6422 #define REG_HDMI3_DUAL_0_62_H (REG_HDMI3_DUAL_0_BASE + 0xC5) 6423 #define REG_HDMI3_DUAL_0_63_L (REG_HDMI3_DUAL_0_BASE + 0xC6) 6424 #define REG_HDMI3_DUAL_0_63_H (REG_HDMI3_DUAL_0_BASE + 0xC7) 6425 #define REG_HDMI3_DUAL_0_64_L (REG_HDMI3_DUAL_0_BASE + 0xC8) 6426 #define REG_HDMI3_DUAL_0_64_H (REG_HDMI3_DUAL_0_BASE + 0xC9) 6427 #define REG_HDMI3_DUAL_0_65_L (REG_HDMI3_DUAL_0_BASE + 0xCA) 6428 #define REG_HDMI3_DUAL_0_65_H (REG_HDMI3_DUAL_0_BASE + 0xCB) 6429 #define REG_HDMI3_DUAL_0_66_L (REG_HDMI3_DUAL_0_BASE + 0xCC) 6430 #define REG_HDMI3_DUAL_0_66_H (REG_HDMI3_DUAL_0_BASE + 0xCD) 6431 #define REG_HDMI3_DUAL_0_67_L (REG_HDMI3_DUAL_0_BASE + 0xCE) 6432 #define REG_HDMI3_DUAL_0_67_H (REG_HDMI3_DUAL_0_BASE + 0xCF) 6433 #define REG_HDMI3_DUAL_0_68_L (REG_HDMI3_DUAL_0_BASE + 0xD0) 6434 #define REG_HDMI3_DUAL_0_68_H (REG_HDMI3_DUAL_0_BASE + 0xD1) 6435 #define REG_HDMI3_DUAL_0_69_L (REG_HDMI3_DUAL_0_BASE + 0xD2) 6436 #define REG_HDMI3_DUAL_0_69_H (REG_HDMI3_DUAL_0_BASE + 0xD3) 6437 #define REG_HDMI3_DUAL_0_6A_L (REG_HDMI3_DUAL_0_BASE + 0xD4) 6438 #define REG_HDMI3_DUAL_0_6A_H (REG_HDMI3_DUAL_0_BASE + 0xD5) 6439 #define REG_HDMI3_DUAL_0_6B_L (REG_HDMI3_DUAL_0_BASE + 0xD6) 6440 #define REG_HDMI3_DUAL_0_6B_H (REG_HDMI3_DUAL_0_BASE + 0xD7) 6441 #define REG_HDMI3_DUAL_0_6C_L (REG_HDMI3_DUAL_0_BASE + 0xD8) 6442 #define REG_HDMI3_DUAL_0_6C_H (REG_HDMI3_DUAL_0_BASE + 0xD9) 6443 #define REG_HDMI3_DUAL_0_6D_L (REG_HDMI3_DUAL_0_BASE + 0xDA) 6444 #define REG_HDMI3_DUAL_0_6D_H (REG_HDMI3_DUAL_0_BASE + 0xDB) 6445 #define REG_HDMI3_DUAL_0_6E_L (REG_HDMI3_DUAL_0_BASE + 0xDC) 6446 #define REG_HDMI3_DUAL_0_6E_H (REG_HDMI3_DUAL_0_BASE + 0xDD) 6447 #define REG_HDMI3_DUAL_0_6F_L (REG_HDMI3_DUAL_0_BASE + 0xDE) 6448 #define REG_HDMI3_DUAL_0_6F_H (REG_HDMI3_DUAL_0_BASE + 0xDF) 6449 #define REG_HDMI3_DUAL_0_70_L (REG_HDMI3_DUAL_0_BASE + 0xE0) 6450 #define REG_HDMI3_DUAL_0_70_H (REG_HDMI3_DUAL_0_BASE + 0xE1) 6451 #define REG_HDMI3_DUAL_0_71_L (REG_HDMI3_DUAL_0_BASE + 0xE2) 6452 #define REG_HDMI3_DUAL_0_71_H (REG_HDMI3_DUAL_0_BASE + 0xE3) 6453 #define REG_HDMI3_DUAL_0_72_L (REG_HDMI3_DUAL_0_BASE + 0xE4) 6454 #define REG_HDMI3_DUAL_0_72_H (REG_HDMI3_DUAL_0_BASE + 0xE5) 6455 #define REG_HDMI3_DUAL_0_73_L (REG_HDMI3_DUAL_0_BASE + 0xE6) 6456 #define REG_HDMI3_DUAL_0_73_H (REG_HDMI3_DUAL_0_BASE + 0xE7) 6457 #define REG_HDMI3_DUAL_0_74_L (REG_HDMI3_DUAL_0_BASE + 0xE8) 6458 #define REG_HDMI3_DUAL_0_74_H (REG_HDMI3_DUAL_0_BASE + 0xE9) 6459 #define REG_HDMI3_DUAL_0_75_L (REG_HDMI3_DUAL_0_BASE + 0xEA) 6460 #define REG_HDMI3_DUAL_0_75_H (REG_HDMI3_DUAL_0_BASE + 0xEB) 6461 #define REG_HDMI3_DUAL_0_76_L (REG_HDMI3_DUAL_0_BASE + 0xEC) 6462 #define REG_HDMI3_DUAL_0_76_H (REG_HDMI3_DUAL_0_BASE + 0xED) 6463 #define REG_HDMI3_DUAL_0_77_L (REG_HDMI3_DUAL_0_BASE + 0xEE) 6464 #define REG_HDMI3_DUAL_0_77_H (REG_HDMI3_DUAL_0_BASE + 0xEF) 6465 #define REG_HDMI3_DUAL_0_78_L (REG_HDMI3_DUAL_0_BASE + 0xF0) 6466 #define REG_HDMI3_DUAL_0_78_H (REG_HDMI3_DUAL_0_BASE + 0xF1) 6467 #define REG_HDMI3_DUAL_0_79_L (REG_HDMI3_DUAL_0_BASE + 0xF2) 6468 #define REG_HDMI3_DUAL_0_79_H (REG_HDMI3_DUAL_0_BASE + 0xF3) 6469 #define REG_HDMI3_DUAL_0_7A_L (REG_HDMI3_DUAL_0_BASE + 0xF4) 6470 #define REG_HDMI3_DUAL_0_7A_H (REG_HDMI3_DUAL_0_BASE + 0xF5) 6471 #define REG_HDMI3_DUAL_0_7B_L (REG_HDMI3_DUAL_0_BASE + 0xF6) 6472 #define REG_HDMI3_DUAL_0_7B_H (REG_HDMI3_DUAL_0_BASE + 0xF7) 6473 #define REG_HDMI3_DUAL_0_7C_L (REG_HDMI3_DUAL_0_BASE + 0xF8) 6474 #define REG_HDMI3_DUAL_0_7C_H (REG_HDMI3_DUAL_0_BASE + 0xF9) 6475 #define REG_HDMI3_DUAL_0_7D_L (REG_HDMI3_DUAL_0_BASE + 0xFA) 6476 #define REG_HDMI3_DUAL_0_7D_H (REG_HDMI3_DUAL_0_BASE + 0xFB) 6477 #define REG_HDMI3_DUAL_0_7E_L (REG_HDMI3_DUAL_0_BASE + 0xFC) 6478 #define REG_HDMI3_DUAL_0_7E_H (REG_HDMI3_DUAL_0_BASE + 0xFD) 6479 #define REG_HDMI3_DUAL_0_7F_L (REG_HDMI3_DUAL_0_BASE + 0xFE) 6480 #define REG_HDMI3_DUAL_0_7F_H (REG_HDMI3_DUAL_0_BASE + 0xFF) 6481 6482 //============================================================= 6483 // COMBO_GP_TOP 6484 #define REG_COMBO_GP_TOP_00_L (REG_COMBO_GP_TOP_BASE + 0x00) 6485 #define REG_COMBO_GP_TOP_00_H (REG_COMBO_GP_TOP_BASE + 0x01) 6486 #define REG_COMBO_GP_TOP_01_L (REG_COMBO_GP_TOP_BASE + 0x02) 6487 #define REG_COMBO_GP_TOP_01_H (REG_COMBO_GP_TOP_BASE + 0x03) 6488 #define REG_COMBO_GP_TOP_02_L (REG_COMBO_GP_TOP_BASE + 0x04) 6489 #define REG_COMBO_GP_TOP_02_H (REG_COMBO_GP_TOP_BASE + 0x05) 6490 #define REG_COMBO_GP_TOP_03_L (REG_COMBO_GP_TOP_BASE + 0x06) 6491 #define REG_COMBO_GP_TOP_03_H (REG_COMBO_GP_TOP_BASE + 0x07) 6492 #define REG_COMBO_GP_TOP_04_L (REG_COMBO_GP_TOP_BASE + 0x08) 6493 #define REG_COMBO_GP_TOP_04_H (REG_COMBO_GP_TOP_BASE + 0x09) 6494 #define REG_COMBO_GP_TOP_05_L (REG_COMBO_GP_TOP_BASE + 0x0A) 6495 #define REG_COMBO_GP_TOP_05_H (REG_COMBO_GP_TOP_BASE + 0x0B) 6496 #define REG_COMBO_GP_TOP_06_L (REG_COMBO_GP_TOP_BASE + 0x0C) 6497 #define REG_COMBO_GP_TOP_06_H (REG_COMBO_GP_TOP_BASE + 0x0D) 6498 #define REG_COMBO_GP_TOP_07_L (REG_COMBO_GP_TOP_BASE + 0x0E) 6499 #define REG_COMBO_GP_TOP_07_H (REG_COMBO_GP_TOP_BASE + 0x0F) 6500 #define REG_COMBO_GP_TOP_08_L (REG_COMBO_GP_TOP_BASE + 0x10) 6501 #define REG_COMBO_GP_TOP_08_H (REG_COMBO_GP_TOP_BASE + 0x11) 6502 #define REG_COMBO_GP_TOP_09_L (REG_COMBO_GP_TOP_BASE + 0x12) 6503 #define REG_COMBO_GP_TOP_09_H (REG_COMBO_GP_TOP_BASE + 0x13) 6504 #define REG_COMBO_GP_TOP_0A_L (REG_COMBO_GP_TOP_BASE + 0x14) 6505 #define REG_COMBO_GP_TOP_0A_H (REG_COMBO_GP_TOP_BASE + 0x15) 6506 #define REG_COMBO_GP_TOP_0B_L (REG_COMBO_GP_TOP_BASE + 0x16) 6507 #define REG_COMBO_GP_TOP_0B_H (REG_COMBO_GP_TOP_BASE + 0x17) 6508 #define REG_COMBO_GP_TOP_0C_L (REG_COMBO_GP_TOP_BASE + 0x18) 6509 #define REG_COMBO_GP_TOP_0C_H (REG_COMBO_GP_TOP_BASE + 0x19) 6510 #define REG_COMBO_GP_TOP_0D_L (REG_COMBO_GP_TOP_BASE + 0x1A) 6511 #define REG_COMBO_GP_TOP_0D_H (REG_COMBO_GP_TOP_BASE + 0x1B) 6512 #define REG_COMBO_GP_TOP_0E_L (REG_COMBO_GP_TOP_BASE + 0x1C) 6513 #define REG_COMBO_GP_TOP_0E_H (REG_COMBO_GP_TOP_BASE + 0x1D) 6514 #define REG_COMBO_GP_TOP_0F_L (REG_COMBO_GP_TOP_BASE + 0x1E) 6515 #define REG_COMBO_GP_TOP_0F_H (REG_COMBO_GP_TOP_BASE + 0x1F) 6516 #define REG_COMBO_GP_TOP_10_L (REG_COMBO_GP_TOP_BASE + 0x20) 6517 #define REG_COMBO_GP_TOP_10_H (REG_COMBO_GP_TOP_BASE + 0x21) 6518 #define REG_COMBO_GP_TOP_11_L (REG_COMBO_GP_TOP_BASE + 0x22) 6519 #define REG_COMBO_GP_TOP_11_H (REG_COMBO_GP_TOP_BASE + 0x23) 6520 #define REG_COMBO_GP_TOP_12_L (REG_COMBO_GP_TOP_BASE + 0x24) 6521 #define REG_COMBO_GP_TOP_12_H (REG_COMBO_GP_TOP_BASE + 0x25) 6522 #define REG_COMBO_GP_TOP_13_L (REG_COMBO_GP_TOP_BASE + 0x26) 6523 #define REG_COMBO_GP_TOP_13_H (REG_COMBO_GP_TOP_BASE + 0x27) 6524 #define REG_COMBO_GP_TOP_14_L (REG_COMBO_GP_TOP_BASE + 0x28) 6525 #define REG_COMBO_GP_TOP_14_H (REG_COMBO_GP_TOP_BASE + 0x29) 6526 #define REG_COMBO_GP_TOP_15_L (REG_COMBO_GP_TOP_BASE + 0x2A) 6527 #define REG_COMBO_GP_TOP_15_H (REG_COMBO_GP_TOP_BASE + 0x2B) 6528 #define REG_COMBO_GP_TOP_16_L (REG_COMBO_GP_TOP_BASE + 0x2C) 6529 #define REG_COMBO_GP_TOP_16_H (REG_COMBO_GP_TOP_BASE + 0x2D) 6530 #define REG_COMBO_GP_TOP_17_L (REG_COMBO_GP_TOP_BASE + 0x2E) 6531 #define REG_COMBO_GP_TOP_17_H (REG_COMBO_GP_TOP_BASE + 0x2F) 6532 #define REG_COMBO_GP_TOP_18_L (REG_COMBO_GP_TOP_BASE + 0x30) 6533 #define REG_COMBO_GP_TOP_18_H (REG_COMBO_GP_TOP_BASE + 0x31) 6534 #define REG_COMBO_GP_TOP_19_L (REG_COMBO_GP_TOP_BASE + 0x32) 6535 #define REG_COMBO_GP_TOP_19_H (REG_COMBO_GP_TOP_BASE + 0x33) 6536 #define REG_COMBO_GP_TOP_1A_L (REG_COMBO_GP_TOP_BASE + 0x34) 6537 #define REG_COMBO_GP_TOP_1A_H (REG_COMBO_GP_TOP_BASE + 0x35) 6538 #define REG_COMBO_GP_TOP_1B_L (REG_COMBO_GP_TOP_BASE + 0x36) 6539 #define REG_COMBO_GP_TOP_1B_H (REG_COMBO_GP_TOP_BASE + 0x37) 6540 #define REG_COMBO_GP_TOP_1C_L (REG_COMBO_GP_TOP_BASE + 0x38) 6541 #define REG_COMBO_GP_TOP_1C_H (REG_COMBO_GP_TOP_BASE + 0x39) 6542 #define REG_COMBO_GP_TOP_1D_L (REG_COMBO_GP_TOP_BASE + 0x3A) 6543 #define REG_COMBO_GP_TOP_1D_H (REG_COMBO_GP_TOP_BASE + 0x3B) 6544 #define REG_COMBO_GP_TOP_1E_L (REG_COMBO_GP_TOP_BASE + 0x3C) 6545 #define REG_COMBO_GP_TOP_1E_H (REG_COMBO_GP_TOP_BASE + 0x3D) 6546 #define REG_COMBO_GP_TOP_1F_L (REG_COMBO_GP_TOP_BASE + 0x3E) 6547 #define REG_COMBO_GP_TOP_1F_H (REG_COMBO_GP_TOP_BASE + 0x3F) 6548 #define REG_COMBO_GP_TOP_20_L (REG_COMBO_GP_TOP_BASE + 0x40) 6549 #define REG_COMBO_GP_TOP_20_H (REG_COMBO_GP_TOP_BASE + 0x41) 6550 #define REG_COMBO_GP_TOP_21_L (REG_COMBO_GP_TOP_BASE + 0x42) 6551 #define REG_COMBO_GP_TOP_21_H (REG_COMBO_GP_TOP_BASE + 0x43) 6552 #define REG_COMBO_GP_TOP_22_L (REG_COMBO_GP_TOP_BASE + 0x44) 6553 #define REG_COMBO_GP_TOP_22_H (REG_COMBO_GP_TOP_BASE + 0x45) 6554 #define REG_COMBO_GP_TOP_23_L (REG_COMBO_GP_TOP_BASE + 0x46) 6555 #define REG_COMBO_GP_TOP_23_H (REG_COMBO_GP_TOP_BASE + 0x47) 6556 #define REG_COMBO_GP_TOP_24_L (REG_COMBO_GP_TOP_BASE + 0x48) 6557 #define REG_COMBO_GP_TOP_24_H (REG_COMBO_GP_TOP_BASE + 0x49) 6558 #define REG_COMBO_GP_TOP_25_L (REG_COMBO_GP_TOP_BASE + 0x4A) 6559 #define REG_COMBO_GP_TOP_25_H (REG_COMBO_GP_TOP_BASE + 0x4B) 6560 #define REG_COMBO_GP_TOP_26_L (REG_COMBO_GP_TOP_BASE + 0x4C) 6561 #define REG_COMBO_GP_TOP_26_H (REG_COMBO_GP_TOP_BASE + 0x4D) 6562 #define REG_COMBO_GP_TOP_27_L (REG_COMBO_GP_TOP_BASE + 0x4E) 6563 #define REG_COMBO_GP_TOP_27_H (REG_COMBO_GP_TOP_BASE + 0x4F) 6564 #define REG_COMBO_GP_TOP_28_L (REG_COMBO_GP_TOP_BASE + 0x50) 6565 #define REG_COMBO_GP_TOP_28_H (REG_COMBO_GP_TOP_BASE + 0x51) 6566 #define REG_COMBO_GP_TOP_29_L (REG_COMBO_GP_TOP_BASE + 0x52) 6567 #define REG_COMBO_GP_TOP_29_H (REG_COMBO_GP_TOP_BASE + 0x53) 6568 #define REG_COMBO_GP_TOP_2A_L (REG_COMBO_GP_TOP_BASE + 0x54) 6569 #define REG_COMBO_GP_TOP_2A_H (REG_COMBO_GP_TOP_BASE + 0x55) 6570 #define REG_COMBO_GP_TOP_2B_L (REG_COMBO_GP_TOP_BASE + 0x56) 6571 #define REG_COMBO_GP_TOP_2B_H (REG_COMBO_GP_TOP_BASE + 0x57) 6572 #define REG_COMBO_GP_TOP_2C_L (REG_COMBO_GP_TOP_BASE + 0x58) 6573 #define REG_COMBO_GP_TOP_2C_H (REG_COMBO_GP_TOP_BASE + 0x59) 6574 #define REG_COMBO_GP_TOP_2D_L (REG_COMBO_GP_TOP_BASE + 0x5A) 6575 #define REG_COMBO_GP_TOP_2D_H (REG_COMBO_GP_TOP_BASE + 0x5B) 6576 #define REG_COMBO_GP_TOP_2E_L (REG_COMBO_GP_TOP_BASE + 0x5C) 6577 #define REG_COMBO_GP_TOP_2E_H (REG_COMBO_GP_TOP_BASE + 0x5D) 6578 #define REG_COMBO_GP_TOP_2F_L (REG_COMBO_GP_TOP_BASE + 0x5E) 6579 #define REG_COMBO_GP_TOP_2F_H (REG_COMBO_GP_TOP_BASE + 0x5F) 6580 #define REG_COMBO_GP_TOP_30_L (REG_COMBO_GP_TOP_BASE + 0x60) 6581 #define REG_COMBO_GP_TOP_30_H (REG_COMBO_GP_TOP_BASE + 0x61) 6582 #define REG_COMBO_GP_TOP_31_L (REG_COMBO_GP_TOP_BASE + 0x62) 6583 #define REG_COMBO_GP_TOP_31_H (REG_COMBO_GP_TOP_BASE + 0x63) 6584 #define REG_COMBO_GP_TOP_32_L (REG_COMBO_GP_TOP_BASE + 0x64) 6585 #define REG_COMBO_GP_TOP_32_H (REG_COMBO_GP_TOP_BASE + 0x65) 6586 #define REG_COMBO_GP_TOP_33_L (REG_COMBO_GP_TOP_BASE + 0x66) 6587 #define REG_COMBO_GP_TOP_33_H (REG_COMBO_GP_TOP_BASE + 0x67) 6588 #define REG_COMBO_GP_TOP_34_L (REG_COMBO_GP_TOP_BASE + 0x68) 6589 #define REG_COMBO_GP_TOP_34_H (REG_COMBO_GP_TOP_BASE + 0x69) 6590 #define REG_COMBO_GP_TOP_35_L (REG_COMBO_GP_TOP_BASE + 0x6A) 6591 #define REG_COMBO_GP_TOP_35_H (REG_COMBO_GP_TOP_BASE + 0x6B) 6592 #define REG_COMBO_GP_TOP_36_L (REG_COMBO_GP_TOP_BASE + 0x6C) 6593 #define REG_COMBO_GP_TOP_36_H (REG_COMBO_GP_TOP_BASE + 0x6D) 6594 #define REG_COMBO_GP_TOP_37_L (REG_COMBO_GP_TOP_BASE + 0x6E) 6595 #define REG_COMBO_GP_TOP_37_H (REG_COMBO_GP_TOP_BASE + 0x6F) 6596 #define REG_COMBO_GP_TOP_38_L (REG_COMBO_GP_TOP_BASE + 0x70) 6597 #define REG_COMBO_GP_TOP_38_H (REG_COMBO_GP_TOP_BASE + 0x71) 6598 #define REG_COMBO_GP_TOP_39_L (REG_COMBO_GP_TOP_BASE + 0x72) 6599 #define REG_COMBO_GP_TOP_39_H (REG_COMBO_GP_TOP_BASE + 0x73) 6600 #define REG_COMBO_GP_TOP_3A_L (REG_COMBO_GP_TOP_BASE + 0x74) 6601 #define REG_COMBO_GP_TOP_3A_H (REG_COMBO_GP_TOP_BASE + 0x75) 6602 #define REG_COMBO_GP_TOP_3B_L (REG_COMBO_GP_TOP_BASE + 0x76) 6603 #define REG_COMBO_GP_TOP_3B_H (REG_COMBO_GP_TOP_BASE + 0x77) 6604 #define REG_COMBO_GP_TOP_3C_L (REG_COMBO_GP_TOP_BASE + 0x78) 6605 #define REG_COMBO_GP_TOP_3C_H (REG_COMBO_GP_TOP_BASE + 0x79) 6606 #define REG_COMBO_GP_TOP_3D_L (REG_COMBO_GP_TOP_BASE + 0x7A) 6607 #define REG_COMBO_GP_TOP_3D_H (REG_COMBO_GP_TOP_BASE + 0x7B) 6608 #define REG_COMBO_GP_TOP_3E_L (REG_COMBO_GP_TOP_BASE + 0x7C) 6609 #define REG_COMBO_GP_TOP_3E_H (REG_COMBO_GP_TOP_BASE + 0x7D) 6610 #define REG_COMBO_GP_TOP_3F_L (REG_COMBO_GP_TOP_BASE + 0x7E) 6611 #define REG_COMBO_GP_TOP_3F_H (REG_COMBO_GP_TOP_BASE + 0x7F) 6612 #define REG_COMBO_GP_TOP_40_L (REG_COMBO_GP_TOP_BASE + 0x80) 6613 #define REG_COMBO_GP_TOP_40_H (REG_COMBO_GP_TOP_BASE + 0x81) 6614 #define REG_COMBO_GP_TOP_41_L (REG_COMBO_GP_TOP_BASE + 0x82) 6615 #define REG_COMBO_GP_TOP_41_H (REG_COMBO_GP_TOP_BASE + 0x83) 6616 #define REG_COMBO_GP_TOP_42_L (REG_COMBO_GP_TOP_BASE + 0x84) 6617 #define REG_COMBO_GP_TOP_42_H (REG_COMBO_GP_TOP_BASE + 0x85) 6618 #define REG_COMBO_GP_TOP_43_L (REG_COMBO_GP_TOP_BASE + 0x86) 6619 #define REG_COMBO_GP_TOP_43_H (REG_COMBO_GP_TOP_BASE + 0x87) 6620 #define REG_COMBO_GP_TOP_44_L (REG_COMBO_GP_TOP_BASE + 0x88) 6621 #define REG_COMBO_GP_TOP_44_H (REG_COMBO_GP_TOP_BASE + 0x89) 6622 #define REG_COMBO_GP_TOP_45_L (REG_COMBO_GP_TOP_BASE + 0x8A) 6623 #define REG_COMBO_GP_TOP_45_H (REG_COMBO_GP_TOP_BASE + 0x8B) 6624 #define REG_COMBO_GP_TOP_46_L (REG_COMBO_GP_TOP_BASE + 0x8C) 6625 #define REG_COMBO_GP_TOP_46_H (REG_COMBO_GP_TOP_BASE + 0x8D) 6626 #define REG_COMBO_GP_TOP_47_L (REG_COMBO_GP_TOP_BASE + 0x8E) 6627 #define REG_COMBO_GP_TOP_47_H (REG_COMBO_GP_TOP_BASE + 0x8F) 6628 #define REG_COMBO_GP_TOP_48_L (REG_COMBO_GP_TOP_BASE + 0x90) 6629 #define REG_COMBO_GP_TOP_48_H (REG_COMBO_GP_TOP_BASE + 0x91) 6630 #define REG_COMBO_GP_TOP_49_L (REG_COMBO_GP_TOP_BASE + 0x92) 6631 #define REG_COMBO_GP_TOP_49_H (REG_COMBO_GP_TOP_BASE + 0x93) 6632 #define REG_COMBO_GP_TOP_4A_L (REG_COMBO_GP_TOP_BASE + 0x94) 6633 #define REG_COMBO_GP_TOP_4A_H (REG_COMBO_GP_TOP_BASE + 0x95) 6634 #define REG_COMBO_GP_TOP_4B_L (REG_COMBO_GP_TOP_BASE + 0x96) 6635 #define REG_COMBO_GP_TOP_4B_H (REG_COMBO_GP_TOP_BASE + 0x97) 6636 #define REG_COMBO_GP_TOP_4C_L (REG_COMBO_GP_TOP_BASE + 0x98) 6637 #define REG_COMBO_GP_TOP_4C_H (REG_COMBO_GP_TOP_BASE + 0x99) 6638 #define REG_COMBO_GP_TOP_4D_L (REG_COMBO_GP_TOP_BASE + 0x9A) 6639 #define REG_COMBO_GP_TOP_4D_H (REG_COMBO_GP_TOP_BASE + 0x9B) 6640 #define REG_COMBO_GP_TOP_4E_L (REG_COMBO_GP_TOP_BASE + 0x9C) 6641 #define REG_COMBO_GP_TOP_4E_H (REG_COMBO_GP_TOP_BASE + 0x9D) 6642 #define REG_COMBO_GP_TOP_4F_L (REG_COMBO_GP_TOP_BASE + 0x9E) 6643 #define REG_COMBO_GP_TOP_4F_H (REG_COMBO_GP_TOP_BASE + 0x9F) 6644 #define REG_COMBO_GP_TOP_50_L (REG_COMBO_GP_TOP_BASE + 0xA0) 6645 #define REG_COMBO_GP_TOP_50_H (REG_COMBO_GP_TOP_BASE + 0xA1) 6646 #define REG_COMBO_GP_TOP_51_L (REG_COMBO_GP_TOP_BASE + 0xA2) 6647 #define REG_COMBO_GP_TOP_51_H (REG_COMBO_GP_TOP_BASE + 0xA3) 6648 #define REG_COMBO_GP_TOP_52_L (REG_COMBO_GP_TOP_BASE + 0xA4) 6649 #define REG_COMBO_GP_TOP_52_H (REG_COMBO_GP_TOP_BASE + 0xA5) 6650 #define REG_COMBO_GP_TOP_53_L (REG_COMBO_GP_TOP_BASE + 0xA6) 6651 #define REG_COMBO_GP_TOP_53_H (REG_COMBO_GP_TOP_BASE + 0xA7) 6652 #define REG_COMBO_GP_TOP_54_L (REG_COMBO_GP_TOP_BASE + 0xA8) 6653 #define REG_COMBO_GP_TOP_54_H (REG_COMBO_GP_TOP_BASE + 0xA9) 6654 #define REG_COMBO_GP_TOP_55_L (REG_COMBO_GP_TOP_BASE + 0xAA) 6655 #define REG_COMBO_GP_TOP_55_H (REG_COMBO_GP_TOP_BASE + 0xAB) 6656 #define REG_COMBO_GP_TOP_56_L (REG_COMBO_GP_TOP_BASE + 0xAC) 6657 #define REG_COMBO_GP_TOP_56_H (REG_COMBO_GP_TOP_BASE + 0xAD) 6658 #define REG_COMBO_GP_TOP_57_L (REG_COMBO_GP_TOP_BASE + 0xAE) 6659 #define REG_COMBO_GP_TOP_57_H (REG_COMBO_GP_TOP_BASE + 0xAF) 6660 #define REG_COMBO_GP_TOP_58_L (REG_COMBO_GP_TOP_BASE + 0xB0) 6661 #define REG_COMBO_GP_TOP_58_H (REG_COMBO_GP_TOP_BASE + 0xB1) 6662 #define REG_COMBO_GP_TOP_59_L (REG_COMBO_GP_TOP_BASE + 0xB2) 6663 #define REG_COMBO_GP_TOP_59_H (REG_COMBO_GP_TOP_BASE + 0xB3) 6664 #define REG_COMBO_GP_TOP_5A_L (REG_COMBO_GP_TOP_BASE + 0xB4) 6665 #define REG_COMBO_GP_TOP_5A_H (REG_COMBO_GP_TOP_BASE + 0xB5) 6666 #define REG_COMBO_GP_TOP_5B_L (REG_COMBO_GP_TOP_BASE + 0xB6) 6667 #define REG_COMBO_GP_TOP_5B_H (REG_COMBO_GP_TOP_BASE + 0xB7) 6668 #define REG_COMBO_GP_TOP_5C_L (REG_COMBO_GP_TOP_BASE + 0xB8) 6669 #define REG_COMBO_GP_TOP_5C_H (REG_COMBO_GP_TOP_BASE + 0xB9) 6670 #define REG_COMBO_GP_TOP_5D_L (REG_COMBO_GP_TOP_BASE + 0xBA) 6671 #define REG_COMBO_GP_TOP_5D_H (REG_COMBO_GP_TOP_BASE + 0xBB) 6672 #define REG_COMBO_GP_TOP_5E_L (REG_COMBO_GP_TOP_BASE + 0xBC) 6673 #define REG_COMBO_GP_TOP_5E_H (REG_COMBO_GP_TOP_BASE + 0xBD) 6674 #define REG_COMBO_GP_TOP_5F_L (REG_COMBO_GP_TOP_BASE + 0xBE) 6675 #define REG_COMBO_GP_TOP_5F_H (REG_COMBO_GP_TOP_BASE + 0xBF) 6676 #define REG_COMBO_GP_TOP_60_L (REG_COMBO_GP_TOP_BASE + 0xC0) 6677 #define REG_COMBO_GP_TOP_60_H (REG_COMBO_GP_TOP_BASE + 0xC1) 6678 #define REG_COMBO_GP_TOP_61_L (REG_COMBO_GP_TOP_BASE + 0xC2) 6679 #define REG_COMBO_GP_TOP_61_H (REG_COMBO_GP_TOP_BASE + 0xC3) 6680 #define REG_COMBO_GP_TOP_62_L (REG_COMBO_GP_TOP_BASE + 0xC4) 6681 #define REG_COMBO_GP_TOP_62_H (REG_COMBO_GP_TOP_BASE + 0xC5) 6682 #define REG_COMBO_GP_TOP_63_L (REG_COMBO_GP_TOP_BASE + 0xC6) 6683 #define REG_COMBO_GP_TOP_63_H (REG_COMBO_GP_TOP_BASE + 0xC7) 6684 #define REG_COMBO_GP_TOP_64_L (REG_COMBO_GP_TOP_BASE + 0xC8) 6685 #define REG_COMBO_GP_TOP_64_H (REG_COMBO_GP_TOP_BASE + 0xC9) 6686 #define REG_COMBO_GP_TOP_65_L (REG_COMBO_GP_TOP_BASE + 0xCA) 6687 #define REG_COMBO_GP_TOP_65_H (REG_COMBO_GP_TOP_BASE + 0xCB) 6688 #define REG_COMBO_GP_TOP_66_L (REG_COMBO_GP_TOP_BASE + 0xCC) 6689 #define REG_COMBO_GP_TOP_66_H (REG_COMBO_GP_TOP_BASE + 0xCD) 6690 #define REG_COMBO_GP_TOP_67_L (REG_COMBO_GP_TOP_BASE + 0xCE) 6691 #define REG_COMBO_GP_TOP_67_H (REG_COMBO_GP_TOP_BASE + 0xCF) 6692 #define REG_COMBO_GP_TOP_68_L (REG_COMBO_GP_TOP_BASE + 0xD0) 6693 #define REG_COMBO_GP_TOP_68_H (REG_COMBO_GP_TOP_BASE + 0xD1) 6694 #define REG_COMBO_GP_TOP_69_L (REG_COMBO_GP_TOP_BASE + 0xD2) 6695 #define REG_COMBO_GP_TOP_69_H (REG_COMBO_GP_TOP_BASE + 0xD3) 6696 #define REG_COMBO_GP_TOP_6A_L (REG_COMBO_GP_TOP_BASE + 0xD4) 6697 #define REG_COMBO_GP_TOP_6A_H (REG_COMBO_GP_TOP_BASE + 0xD5) 6698 #define REG_COMBO_GP_TOP_6B_L (REG_COMBO_GP_TOP_BASE + 0xD6) 6699 #define REG_COMBO_GP_TOP_6B_H (REG_COMBO_GP_TOP_BASE + 0xD7) 6700 #define REG_COMBO_GP_TOP_6C_L (REG_COMBO_GP_TOP_BASE + 0xD8) 6701 #define REG_COMBO_GP_TOP_6C_H (REG_COMBO_GP_TOP_BASE + 0xD9) 6702 #define REG_COMBO_GP_TOP_6D_L (REG_COMBO_GP_TOP_BASE + 0xDA) 6703 #define REG_COMBO_GP_TOP_6D_H (REG_COMBO_GP_TOP_BASE + 0xDB) 6704 #define REG_COMBO_GP_TOP_6E_L (REG_COMBO_GP_TOP_BASE + 0xDC) 6705 #define REG_COMBO_GP_TOP_6E_H (REG_COMBO_GP_TOP_BASE + 0xDD) 6706 6707 //============================================================= 6708 // SECURE_TZPC 6709 #define REG_SECURE_TZPC_00_L (REG_SECURE_TZPC_BASE + 0x00) 6710 #define REG_SECURE_TZPC_00_H (REG_SECURE_TZPC_BASE + 0x01) 6711 #define REG_SECURE_TZPC_01_L (REG_SECURE_TZPC_BASE + 0x02) 6712 #define REG_SECURE_TZPC_01_H (REG_SECURE_TZPC_BASE + 0x03) 6713 #define REG_SECURE_TZPC_02_L (REG_SECURE_TZPC_BASE + 0x04) 6714 #define REG_SECURE_TZPC_02_H (REG_SECURE_TZPC_BASE + 0x05) 6715 #define REG_SECURE_TZPC_03_L (REG_SECURE_TZPC_BASE + 0x06) 6716 #define REG_SECURE_TZPC_03_H (REG_SECURE_TZPC_BASE + 0x07) 6717 #define REG_SECURE_TZPC_04_L (REG_SECURE_TZPC_BASE + 0x08) 6718 #define REG_SECURE_TZPC_04_H (REG_SECURE_TZPC_BASE + 0x09) 6719 #define REG_SECURE_TZPC_05_L (REG_SECURE_TZPC_BASE + 0x0A) 6720 #define REG_SECURE_TZPC_05_H (REG_SECURE_TZPC_BASE + 0x0B) 6721 #define REG_SECURE_TZPC_06_L (REG_SECURE_TZPC_BASE + 0x0C) 6722 #define REG_SECURE_TZPC_06_H (REG_SECURE_TZPC_BASE + 0x0D) 6723 #define REG_SECURE_TZPC_07_L (REG_SECURE_TZPC_BASE + 0x0E) 6724 #define REG_SECURE_TZPC_07_H (REG_SECURE_TZPC_BASE + 0x0F) 6725 #define REG_SECURE_TZPC_08_L (REG_SECURE_TZPC_BASE + 0x10) 6726 #define REG_SECURE_TZPC_08_H (REG_SECURE_TZPC_BASE + 0x11) 6727 #define REG_SECURE_TZPC_09_L (REG_SECURE_TZPC_BASE + 0x12) 6728 #define REG_SECURE_TZPC_09_H (REG_SECURE_TZPC_BASE + 0x13) 6729 #define REG_SECURE_TZPC_0A_L (REG_SECURE_TZPC_BASE + 0x14) 6730 #define REG_SECURE_TZPC_0A_H (REG_SECURE_TZPC_BASE + 0x15) 6731 #define REG_SECURE_TZPC_0B_L (REG_SECURE_TZPC_BASE + 0x16) 6732 #define REG_SECURE_TZPC_0B_H (REG_SECURE_TZPC_BASE + 0x17) 6733 #define REG_SECURE_TZPC_0C_L (REG_SECURE_TZPC_BASE + 0x18) 6734 #define REG_SECURE_TZPC_0C_H (REG_SECURE_TZPC_BASE + 0x19) 6735 #define REG_SECURE_TZPC_0D_L (REG_SECURE_TZPC_BASE + 0x1A) 6736 #define REG_SECURE_TZPC_0D_H (REG_SECURE_TZPC_BASE + 0x1B) 6737 #define REG_SECURE_TZPC_0E_L (REG_SECURE_TZPC_BASE + 0x1C) 6738 #define REG_SECURE_TZPC_0E_H (REG_SECURE_TZPC_BASE + 0x1D) 6739 #define REG_SECURE_TZPC_0F_L (REG_SECURE_TZPC_BASE + 0x1E) 6740 #define REG_SECURE_TZPC_0F_H (REG_SECURE_TZPC_BASE + 0x1F) 6741 #define REG_SECURE_TZPC_10_L (REG_SECURE_TZPC_BASE + 0x20) 6742 #define REG_SECURE_TZPC_10_H (REG_SECURE_TZPC_BASE + 0x21) 6743 #define REG_SECURE_TZPC_11_L (REG_SECURE_TZPC_BASE + 0x22) 6744 #define REG_SECURE_TZPC_11_H (REG_SECURE_TZPC_BASE + 0x23) 6745 #define REG_SECURE_TZPC_12_L (REG_SECURE_TZPC_BASE + 0x24) 6746 #define REG_SECURE_TZPC_12_H (REG_SECURE_TZPC_BASE + 0x25) 6747 #define REG_SECURE_TZPC_13_L (REG_SECURE_TZPC_BASE + 0x26) 6748 #define REG_SECURE_TZPC_13_H (REG_SECURE_TZPC_BASE + 0x27) 6749 #define REG_SECURE_TZPC_14_L (REG_SECURE_TZPC_BASE + 0x28) 6750 #define REG_SECURE_TZPC_14_H (REG_SECURE_TZPC_BASE + 0x29) 6751 #define REG_SECURE_TZPC_15_L (REG_SECURE_TZPC_BASE + 0x2A) 6752 #define REG_SECURE_TZPC_15_H (REG_SECURE_TZPC_BASE + 0x2B) 6753 #define REG_SECURE_TZPC_16_L (REG_SECURE_TZPC_BASE + 0x2C) 6754 #define REG_SECURE_TZPC_16_H (REG_SECURE_TZPC_BASE + 0x2D) 6755 #define REG_SECURE_TZPC_17_L (REG_SECURE_TZPC_BASE + 0x2E) 6756 #define REG_SECURE_TZPC_17_H (REG_SECURE_TZPC_BASE + 0x2F) 6757 #define REG_SECURE_TZPC_18_L (REG_SECURE_TZPC_BASE + 0x30) 6758 #define REG_SECURE_TZPC_18_H (REG_SECURE_TZPC_BASE + 0x31) 6759 #define REG_SECURE_TZPC_19_L (REG_SECURE_TZPC_BASE + 0x32) 6760 #define REG_SECURE_TZPC_19_H (REG_SECURE_TZPC_BASE + 0x33) 6761 #define REG_SECURE_TZPC_1A_L (REG_SECURE_TZPC_BASE + 0x34) 6762 #define REG_SECURE_TZPC_1A_H (REG_SECURE_TZPC_BASE + 0x35) 6763 #define REG_SECURE_TZPC_1B_L (REG_SECURE_TZPC_BASE + 0x36) 6764 #define REG_SECURE_TZPC_1B_H (REG_SECURE_TZPC_BASE + 0x37) 6765 #define REG_SECURE_TZPC_1C_L (REG_SECURE_TZPC_BASE + 0x38) 6766 #define REG_SECURE_TZPC_1C_H (REG_SECURE_TZPC_BASE + 0x39) 6767 #define REG_SECURE_TZPC_1D_L (REG_SECURE_TZPC_BASE + 0x3A) 6768 #define REG_SECURE_TZPC_1D_H (REG_SECURE_TZPC_BASE + 0x3B) 6769 #define REG_SECURE_TZPC_1E_L (REG_SECURE_TZPC_BASE + 0x3C) 6770 #define REG_SECURE_TZPC_1E_H (REG_SECURE_TZPC_BASE + 0x3D) 6771 #define REG_SECURE_TZPC_1F_L (REG_SECURE_TZPC_BASE + 0x3E) 6772 #define REG_SECURE_TZPC_1F_H (REG_SECURE_TZPC_BASE + 0x3F) 6773 #define REG_SECURE_TZPC_20_L (REG_SECURE_TZPC_BASE + 0x40) 6774 #define REG_SECURE_TZPC_20_H (REG_SECURE_TZPC_BASE + 0x41) 6775 #define REG_SECURE_TZPC_21_L (REG_SECURE_TZPC_BASE + 0x42) 6776 #define REG_SECURE_TZPC_21_H (REG_SECURE_TZPC_BASE + 0x43) 6777 #define REG_SECURE_TZPC_22_L (REG_SECURE_TZPC_BASE + 0x44) 6778 #define REG_SECURE_TZPC_22_H (REG_SECURE_TZPC_BASE + 0x45) 6779 #define REG_SECURE_TZPC_23_L (REG_SECURE_TZPC_BASE + 0x46) 6780 #define REG_SECURE_TZPC_23_H (REG_SECURE_TZPC_BASE + 0x47) 6781 #define REG_SECURE_TZPC_24_L (REG_SECURE_TZPC_BASE + 0x48) 6782 #define REG_SECURE_TZPC_24_H (REG_SECURE_TZPC_BASE + 0x49) 6783 #define REG_SECURE_TZPC_25_L (REG_SECURE_TZPC_BASE + 0x4A) 6784 #define REG_SECURE_TZPC_25_H (REG_SECURE_TZPC_BASE + 0x4B) 6785 #define REG_SECURE_TZPC_26_L (REG_SECURE_TZPC_BASE + 0x4C) 6786 #define REG_SECURE_TZPC_26_H (REG_SECURE_TZPC_BASE + 0x4D) 6787 #define REG_SECURE_TZPC_27_L (REG_SECURE_TZPC_BASE + 0x4E) 6788 #define REG_SECURE_TZPC_27_H (REG_SECURE_TZPC_BASE + 0x4F) 6789 #define REG_SECURE_TZPC_28_L (REG_SECURE_TZPC_BASE + 0x50) 6790 #define REG_SECURE_TZPC_28_H (REG_SECURE_TZPC_BASE + 0x51) 6791 #define REG_SECURE_TZPC_29_L (REG_SECURE_TZPC_BASE + 0x52) 6792 #define REG_SECURE_TZPC_29_H (REG_SECURE_TZPC_BASE + 0x53) 6793 #define REG_SECURE_TZPC_2A_L (REG_SECURE_TZPC_BASE + 0x54) 6794 #define REG_SECURE_TZPC_2A_H (REG_SECURE_TZPC_BASE + 0x55) 6795 #define REG_SECURE_TZPC_2B_L (REG_SECURE_TZPC_BASE + 0x56) 6796 #define REG_SECURE_TZPC_2B_H (REG_SECURE_TZPC_BASE + 0x57) 6797 #define REG_SECURE_TZPC_2C_L (REG_SECURE_TZPC_BASE + 0x58) 6798 #define REG_SECURE_TZPC_2C_H (REG_SECURE_TZPC_BASE + 0x59) 6799 #define REG_SECURE_TZPC_2D_L (REG_SECURE_TZPC_BASE + 0x5A) 6800 #define REG_SECURE_TZPC_2D_H (REG_SECURE_TZPC_BASE + 0x5B) 6801 #define REG_SECURE_TZPC_2E_L (REG_SECURE_TZPC_BASE + 0x5C) 6802 #define REG_SECURE_TZPC_2E_H (REG_SECURE_TZPC_BASE + 0x5D) 6803 #define REG_SECURE_TZPC_2F_L (REG_SECURE_TZPC_BASE + 0x5E) 6804 #define REG_SECURE_TZPC_2F_H (REG_SECURE_TZPC_BASE + 0x5F) 6805 #define REG_SECURE_TZPC_30_L (REG_SECURE_TZPC_BASE + 0x60) 6806 #define REG_SECURE_TZPC_30_H (REG_SECURE_TZPC_BASE + 0x61) 6807 #define REG_SECURE_TZPC_31_L (REG_SECURE_TZPC_BASE + 0x62) 6808 #define REG_SECURE_TZPC_31_H (REG_SECURE_TZPC_BASE + 0x63) 6809 #define REG_SECURE_TZPC_32_L (REG_SECURE_TZPC_BASE + 0x64) 6810 #define REG_SECURE_TZPC_32_H (REG_SECURE_TZPC_BASE + 0x65) 6811 #define REG_SECURE_TZPC_33_L (REG_SECURE_TZPC_BASE + 0x66) 6812 #define REG_SECURE_TZPC_33_H (REG_SECURE_TZPC_BASE + 0x67) 6813 #define REG_SECURE_TZPC_34_L (REG_SECURE_TZPC_BASE + 0x68) 6814 #define REG_SECURE_TZPC_34_H (REG_SECURE_TZPC_BASE + 0x69) 6815 #define REG_SECURE_TZPC_35_L (REG_SECURE_TZPC_BASE + 0x6A) 6816 #define REG_SECURE_TZPC_35_H (REG_SECURE_TZPC_BASE + 0x6B) 6817 #define REG_SECURE_TZPC_36_L (REG_SECURE_TZPC_BASE + 0x6C) 6818 #define REG_SECURE_TZPC_36_H (REG_SECURE_TZPC_BASE + 0x6D) 6819 #define REG_SECURE_TZPC_37_L (REG_SECURE_TZPC_BASE + 0x6E) 6820 #define REG_SECURE_TZPC_37_H (REG_SECURE_TZPC_BASE + 0x6F) 6821 #define REG_SECURE_TZPC_38_L (REG_SECURE_TZPC_BASE + 0x70) 6822 #define REG_SECURE_TZPC_38_H (REG_SECURE_TZPC_BASE + 0x71) 6823 #define REG_SECURE_TZPC_39_L (REG_SECURE_TZPC_BASE + 0x72) 6824 #define REG_SECURE_TZPC_39_H (REG_SECURE_TZPC_BASE + 0x73) 6825 #define REG_SECURE_TZPC_3A_L (REG_SECURE_TZPC_BASE + 0x74) 6826 #define REG_SECURE_TZPC_3A_H (REG_SECURE_TZPC_BASE + 0x75) 6827 #define REG_SECURE_TZPC_3B_L (REG_SECURE_TZPC_BASE + 0x76) 6828 #define REG_SECURE_TZPC_3B_H (REG_SECURE_TZPC_BASE + 0x77) 6829 #define REG_SECURE_TZPC_3C_L (REG_SECURE_TZPC_BASE + 0x78) 6830 #define REG_SECURE_TZPC_3C_H (REG_SECURE_TZPC_BASE + 0x79) 6831 #define REG_SECURE_TZPC_3D_L (REG_SECURE_TZPC_BASE + 0x7A) 6832 #define REG_SECURE_TZPC_3D_H (REG_SECURE_TZPC_BASE + 0x7B) 6833 #define REG_SECURE_TZPC_3E_L (REG_SECURE_TZPC_BASE + 0x7C) 6834 #define REG_SECURE_TZPC_3E_H (REG_SECURE_TZPC_BASE + 0x7D) 6835 #define REG_SECURE_TZPC_3F_L (REG_SECURE_TZPC_BASE + 0x7E) 6836 #define REG_SECURE_TZPC_3F_H (REG_SECURE_TZPC_BASE + 0x7F) 6837 #define REG_SECURE_TZPC_40_L (REG_SECURE_TZPC_BASE + 0x80) 6838 #define REG_SECURE_TZPC_40_H (REG_SECURE_TZPC_BASE + 0x81) 6839 #define REG_SECURE_TZPC_41_L (REG_SECURE_TZPC_BASE + 0x82) 6840 #define REG_SECURE_TZPC_41_H (REG_SECURE_TZPC_BASE + 0x83) 6841 #define REG_SECURE_TZPC_42_L (REG_SECURE_TZPC_BASE + 0x84) 6842 #define REG_SECURE_TZPC_42_H (REG_SECURE_TZPC_BASE + 0x85) 6843 #define REG_SECURE_TZPC_43_L (REG_SECURE_TZPC_BASE + 0x86) 6844 #define REG_SECURE_TZPC_43_H (REG_SECURE_TZPC_BASE + 0x87) 6845 #define REG_SECURE_TZPC_44_L (REG_SECURE_TZPC_BASE + 0x88) 6846 #define REG_SECURE_TZPC_44_H (REG_SECURE_TZPC_BASE + 0x89) 6847 #define REG_SECURE_TZPC_45_L (REG_SECURE_TZPC_BASE + 0x8A) 6848 #define REG_SECURE_TZPC_45_H (REG_SECURE_TZPC_BASE + 0x8B) 6849 #define REG_SECURE_TZPC_46_L (REG_SECURE_TZPC_BASE + 0x8C) 6850 #define REG_SECURE_TZPC_46_H (REG_SECURE_TZPC_BASE + 0x8D) 6851 #define REG_SECURE_TZPC_47_L (REG_SECURE_TZPC_BASE + 0x8E) 6852 #define REG_SECURE_TZPC_47_H (REG_SECURE_TZPC_BASE + 0x8F) 6853 #define REG_SECURE_TZPC_48_L (REG_SECURE_TZPC_BASE + 0x90) 6854 #define REG_SECURE_TZPC_48_H (REG_SECURE_TZPC_BASE + 0x91) 6855 #define REG_SECURE_TZPC_49_L (REG_SECURE_TZPC_BASE + 0x92) 6856 #define REG_SECURE_TZPC_49_H (REG_SECURE_TZPC_BASE + 0x93) 6857 #define REG_SECURE_TZPC_4A_L (REG_SECURE_TZPC_BASE + 0x94) 6858 #define REG_SECURE_TZPC_4A_H (REG_SECURE_TZPC_BASE + 0x95) 6859 #define REG_SECURE_TZPC_4B_L (REG_SECURE_TZPC_BASE + 0x96) 6860 #define REG_SECURE_TZPC_4B_H (REG_SECURE_TZPC_BASE + 0x97) 6861 #define REG_SECURE_TZPC_4C_L (REG_SECURE_TZPC_BASE + 0x98) 6862 #define REG_SECURE_TZPC_4C_H (REG_SECURE_TZPC_BASE + 0x99) 6863 #define REG_SECURE_TZPC_4D_L (REG_SECURE_TZPC_BASE + 0x9A) 6864 #define REG_SECURE_TZPC_4D_H (REG_SECURE_TZPC_BASE + 0x9B) 6865 #define REG_SECURE_TZPC_4E_L (REG_SECURE_TZPC_BASE + 0x9C) 6866 #define REG_SECURE_TZPC_4E_H (REG_SECURE_TZPC_BASE + 0x9D) 6867 #define REG_SECURE_TZPC_4F_L (REG_SECURE_TZPC_BASE + 0x9E) 6868 #define REG_SECURE_TZPC_4F_H (REG_SECURE_TZPC_BASE + 0x9F) 6869 #define REG_SECURE_TZPC_50_L (REG_SECURE_TZPC_BASE + 0xA0) 6870 #define REG_SECURE_TZPC_50_H (REG_SECURE_TZPC_BASE + 0xA1) 6871 #define REG_SECURE_TZPC_51_L (REG_SECURE_TZPC_BASE + 0xA2) 6872 #define REG_SECURE_TZPC_51_H (REG_SECURE_TZPC_BASE + 0xA3) 6873 #define REG_SECURE_TZPC_52_L (REG_SECURE_TZPC_BASE + 0xA4) 6874 #define REG_SECURE_TZPC_52_H (REG_SECURE_TZPC_BASE + 0xA5) 6875 #define REG_SECURE_TZPC_53_L (REG_SECURE_TZPC_BASE + 0xA6) 6876 #define REG_SECURE_TZPC_53_H (REG_SECURE_TZPC_BASE + 0xA7) 6877 #define REG_SECURE_TZPC_54_L (REG_SECURE_TZPC_BASE + 0xA8) 6878 #define REG_SECURE_TZPC_54_H (REG_SECURE_TZPC_BASE + 0xA9) 6879 #define REG_SECURE_TZPC_55_L (REG_SECURE_TZPC_BASE + 0xAA) 6880 #define REG_SECURE_TZPC_55_H (REG_SECURE_TZPC_BASE + 0xAB) 6881 #define REG_SECURE_TZPC_56_L (REG_SECURE_TZPC_BASE + 0xAC) 6882 #define REG_SECURE_TZPC_56_H (REG_SECURE_TZPC_BASE + 0xAD) 6883 #define REG_SECURE_TZPC_57_L (REG_SECURE_TZPC_BASE + 0xAE) 6884 #define REG_SECURE_TZPC_57_H (REG_SECURE_TZPC_BASE + 0xAF) 6885 #define REG_SECURE_TZPC_58_L (REG_SECURE_TZPC_BASE + 0xB0) 6886 #define REG_SECURE_TZPC_58_H (REG_SECURE_TZPC_BASE + 0xB1) 6887 #define REG_SECURE_TZPC_59_L (REG_SECURE_TZPC_BASE + 0xB2) 6888 #define REG_SECURE_TZPC_59_H (REG_SECURE_TZPC_BASE + 0xB3) 6889 #define REG_SECURE_TZPC_5A_L (REG_SECURE_TZPC_BASE + 0xB4) 6890 #define REG_SECURE_TZPC_5A_H (REG_SECURE_TZPC_BASE + 0xB5) 6891 #define REG_SECURE_TZPC_5B_L (REG_SECURE_TZPC_BASE + 0xB6) 6892 #define REG_SECURE_TZPC_5B_H (REG_SECURE_TZPC_BASE + 0xB7) 6893 #define REG_SECURE_TZPC_5C_L (REG_SECURE_TZPC_BASE + 0xB8) 6894 #define REG_SECURE_TZPC_5C_H (REG_SECURE_TZPC_BASE + 0xB9) 6895 #define REG_SECURE_TZPC_5D_L (REG_SECURE_TZPC_BASE + 0xBA) 6896 #define REG_SECURE_TZPC_5D_H (REG_SECURE_TZPC_BASE + 0xBB) 6897 #define REG_SECURE_TZPC_5E_L (REG_SECURE_TZPC_BASE + 0xBC) 6898 #define REG_SECURE_TZPC_5E_H (REG_SECURE_TZPC_BASE + 0xBD) 6899 #define REG_SECURE_TZPC_5F_L (REG_SECURE_TZPC_BASE + 0xBE) 6900 #define REG_SECURE_TZPC_5F_H (REG_SECURE_TZPC_BASE + 0xBF) 6901 #define REG_SECURE_TZPC_60_L (REG_SECURE_TZPC_BASE + 0xC0) 6902 #define REG_SECURE_TZPC_60_H (REG_SECURE_TZPC_BASE + 0xC1) 6903 #define REG_SECURE_TZPC_61_L (REG_SECURE_TZPC_BASE + 0xC2) 6904 #define REG_SECURE_TZPC_61_H (REG_SECURE_TZPC_BASE + 0xC3) 6905 #define REG_SECURE_TZPC_62_L (REG_SECURE_TZPC_BASE + 0xC4) 6906 #define REG_SECURE_TZPC_62_H (REG_SECURE_TZPC_BASE + 0xC5) 6907 #define REG_SECURE_TZPC_63_L (REG_SECURE_TZPC_BASE + 0xC6) 6908 #define REG_SECURE_TZPC_63_H (REG_SECURE_TZPC_BASE + 0xC7) 6909 #define REG_SECURE_TZPC_64_L (REG_SECURE_TZPC_BASE + 0xC8) 6910 #define REG_SECURE_TZPC_64_H (REG_SECURE_TZPC_BASE + 0xC9) 6911 #define REG_SECURE_TZPC_65_L (REG_SECURE_TZPC_BASE + 0xCA) 6912 #define REG_SECURE_TZPC_65_H (REG_SECURE_TZPC_BASE + 0xCB) 6913 #define REG_SECURE_TZPC_66_L (REG_SECURE_TZPC_BASE + 0xCC) 6914 #define REG_SECURE_TZPC_66_H (REG_SECURE_TZPC_BASE + 0xCD) 6915 #define REG_SECURE_TZPC_67_L (REG_SECURE_TZPC_BASE + 0xCE) 6916 #define REG_SECURE_TZPC_67_H (REG_SECURE_TZPC_BASE + 0xCF) 6917 #define REG_SECURE_TZPC_68_L (REG_SECURE_TZPC_BASE + 0xD0) 6918 #define REG_SECURE_TZPC_68_H (REG_SECURE_TZPC_BASE + 0xD1) 6919 #define REG_SECURE_TZPC_69_L (REG_SECURE_TZPC_BASE + 0xD2) 6920 #define REG_SECURE_TZPC_69_H (REG_SECURE_TZPC_BASE + 0xD3) 6921 #define REG_SECURE_TZPC_6A_L (REG_SECURE_TZPC_BASE + 0xD4) 6922 #define REG_SECURE_TZPC_6A_H (REG_SECURE_TZPC_BASE + 0xD5) 6923 #define REG_SECURE_TZPC_6B_L (REG_SECURE_TZPC_BASE + 0xD6) 6924 #define REG_SECURE_TZPC_6B_H (REG_SECURE_TZPC_BASE + 0xD7) 6925 #define REG_SECURE_TZPC_6C_L (REG_SECURE_TZPC_BASE + 0xD8) 6926 #define REG_SECURE_TZPC_6C_H (REG_SECURE_TZPC_BASE + 0xD9) 6927 #define REG_SECURE_TZPC_6D_L (REG_SECURE_TZPC_BASE + 0xDA) 6928 #define REG_SECURE_TZPC_6D_H (REG_SECURE_TZPC_BASE + 0xDB) 6929 #define REG_SECURE_TZPC_6E_L (REG_SECURE_TZPC_BASE + 0xDC) 6930 #define REG_SECURE_TZPC_6E_H (REG_SECURE_TZPC_BASE + 0xDD) 6931 6932 // CHIP_GPIO 6933 #define REG_CHIP_GPIO_08_L (REG_CHIP_GPIO_BASE + 0x10) 6934 #define REG_CHIP_GPIO_08_H (REG_CHIP_GPIO_BASE + 0x11) 6935 #define REG_CHIP_GPIO_09_L (REG_CHIP_GPIO_BASE + 0x12) 6936 #define REG_CHIP_GPIO_09_H (REG_CHIP_GPIO_BASE + 0x13) 6937 #define REG_CHIP_GPIO_0A_L (REG_CHIP_GPIO_BASE + 0x14) 6938 #define REG_CHIP_GPIO_0A_H (REG_CHIP_GPIO_BASE + 0x15) 6939 #define REG_CHIP_GPIO_0B_L (REG_CHIP_GPIO_BASE + 0x16) 6940 #define REG_CHIP_GPIO_0B_H (REG_CHIP_GPIO_BASE + 0x17) 6941 #define REG_CHIP_GPIO_0C_L (REG_CHIP_GPIO_BASE + 0x18) 6942 #define REG_CHIP_GPIO_0C_H (REG_CHIP_GPIO_BASE + 0x19) 6943 #define REG_CHIP_GPIO_0D_L (REG_CHIP_GPIO_BASE + 0x1A) 6944 #define REG_CHIP_GPIO_0D_H (REG_CHIP_GPIO_BASE + 0x1B) 6945 #define REG_CHIP_GPIO_0E_L (REG_CHIP_GPIO_BASE + 0x1C) 6946 #define REG_CHIP_GPIO_0E_H (REG_CHIP_GPIO_BASE + 0x1D) 6947 #define REG_CHIP_GPIO_0F_L (REG_CHIP_GPIO_BASE + 0x1E) 6948 #define REG_CHIP_GPIO_0F_H (REG_CHIP_GPIO_BASE + 0x1F) 6949 6950 #define REG_CHIP_GPIO_50_L (REG_CHIP_GPIO_BASE + 0xA0) 6951 #define REG_CHIP_GPIO_50_H (REG_CHIP_GPIO_BASE + 0xA1) 6952 #define REG_CHIP_GPIO_51_L (REG_CHIP_GPIO_BASE + 0xA2) 6953 #define REG_CHIP_GPIO_51_H (REG_CHIP_GPIO_BASE + 0xA3) 6954 #define REG_CHIP_GPIO_52_L (REG_CHIP_GPIO_BASE + 0xA4) 6955 #define REG_CHIP_GPIO_52_H (REG_CHIP_GPIO_BASE + 0xA5) 6956 #define REG_CHIP_GPIO_53_L (REG_CHIP_GPIO_BASE + 0xA6) 6957 #define REG_CHIP_GPIO_53_H (REG_CHIP_GPIO_BASE + 0xA7) 6958 #define REG_CHIP_GPIO_54_L (REG_CHIP_GPIO_BASE + 0xA8) 6959 #define REG_CHIP_GPIO_54_H (REG_CHIP_GPIO_BASE + 0xA9) 6960 #define REG_CHIP_GPIO_55_L (REG_CHIP_GPIO_BASE + 0xAA) 6961 #define REG_CHIP_GPIO_55_H (REG_CHIP_GPIO_BASE + 0xAB) 6962 #define REG_CHIP_GPIO_56_L (REG_CHIP_GPIO_BASE + 0xAC) 6963 #define REG_CHIP_GPIO_56_H (REG_CHIP_GPIO_BASE + 0xAD) 6964 #define REG_CHIP_GPIO_57_L (REG_CHIP_GPIO_BASE + 0xAE) 6965 #define REG_CHIP_GPIO_57_H (REG_CHIP_GPIO_BASE + 0xAF) 6966 6967 #endif 6968 6969