| /utopia/UTPA2-700.0.x/modules/mvop/hal/k6/mvop/ |
| H A D | halMVOP.c | 783 …HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x4, CKG_DC0_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4… in HAL_MVOP_SetOutputInterlace()
1520 …HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x4, CKG_DC0_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4… in HAL_MVOP_SetDCSRAMClk()
1524 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC0_SRAM); in HAL_MVOP_SetDCSRAMClk()
1531 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC0_SRAM); in HAL_MVOP_SetDCSRAMClk()
1661 …HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC0_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4… in HAL_MVOP_SetH264HardwireMode()
1675 …HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x4, CKG_DC0_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4… in HAL_MVOP_SetRMHardwireMode()
1731 …HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC0_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4… in HAL_MVOP_SetEVDHardwireMode()
4335 …HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x40, CKG_DC1_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x… in HAL_MVOP_SubSetOutputInterlace()
4932 …HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x4, CKG_DC1_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4… in HAL_MVOP_SubSetDCSRAMClk()
4936 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC1_SRAM); in HAL_MVOP_SubSetDCSRAMClk()
[all …]
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| H A D | regMVOP.h | 489 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0xAE) macro
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/k7u/mvop/ |
| H A D | regMVOP.h | 448 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0xAE) macro
478 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0xAE) macro
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| H A D | halMVOP.c | 1459 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC0_SRAM_MASK);//mfdec0 in HAL_MVOP_SetDCSRAMClk()
1460 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC1_SRAM_MASK);//mfdec1 in HAL_MVOP_SetDCSRAMClk()
4897 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC0_SRAM_MASK);//mfdec0 in HAL_MVOP_SubSetDCSRAMClk()
4898 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC1_SRAM_MASK);//mfdec1 in HAL_MVOP_SubSetDCSRAMClk()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/mustang/mvop/ |
| H A D | regMVOP.h | 384 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E) macro
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| H A D | halMVOP.c | 1316 HAL_WriteRegBit(REG_CKG_DC_SRAM, !bEnable, CKG_DC0_SRAM); in HAL_MVOP_SetDCSRAMClk()
3827 HAL_WriteRegBit(REG_CKG_DC_SRAM, !bEnable, CKG_DC1_SRAM); in HAL_MVOP_SubSetDCSRAMClk()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/macan/mvop/ |
| H A D | regMVOP.h | 403 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E) macro
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/messi/mvop/ |
| H A D | regMVOP.h | 404 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E) macro
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/manhattan/mvop/ |
| H A D | regMVOP.h | 397 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E) macro
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| H A D | halMVOP.c | 1407 HAL_WriteRegBit(REG_CKG_DC_SRAM, !bEnable, CKG_DC0_SRAM); in HAL_MVOP_SetDCSRAMClk()
4343 HAL_WriteRegBit(REG_CKG_DC_SRAM, !bEnable, CKG_DC1_SRAM); in HAL_MVOP_SubSetDCSRAMClk()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/M7821/mvop/ |
| H A D | regMVOP.h | 406 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E) macro
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/mainz/mvop/ |
| H A D | regMVOP.h | 404 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E) macro
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/mooney/mvop/ |
| H A D | regMVOP.h | 422 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E) macro
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| H A D | halMVOP.c | 1427 HAL_WriteRegBit(REG_CKG_DC_SRAM, !bEnable, CKG_DC0_SRAM); in HAL_MVOP_SetDCSRAMClk()
4451 HAL_WriteRegBit(REG_CKG_DC_SRAM, !bEnable, CKG_DC1_SRAM); in HAL_MVOP_SubSetDCSRAMClk()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/maserati/mvop/ |
| H A D | regMVOP.h | 407 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E) macro
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| H A D | halMVOP.c | 1499 HAL_WriteRegBit(REG_CKG_DC_SRAM, !bEnable, CKG_DC0_SRAM); in HAL_MVOP_SetDCSRAMClk()
4808 HAL_WriteRegBit(REG_CKG_DC_SRAM, !bEnable, CKG_DC1_SRAM); in HAL_MVOP_SubSetDCSRAMClk()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/M7621/mvop/ |
| H A D | regMVOP.h | 419 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E) macro
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/M5621/mvop/ |
| H A D | regMVOP.h | 413 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E) macro
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| H A D | halMVOP.c | 1380 HAL_WriteRegBit(REG_CKG_DC_SRAM, !bEnable, CKG_DC0_SRAM); in HAL_MVOP_SetDCSRAMClk()
4333 HAL_WriteRegBit(REG_CKG_DC_SRAM, !bEnable, CKG_DC1_SRAM); in HAL_MVOP_SubSetDCSRAMClk()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/kastor/mvop/ |
| H A D | regMVOP.h | 436 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E) macro
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/curry/mvop/ |
| H A D | regMVOP.h | 433 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E) macro
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/kano/mvop/ |
| H A D | regMVOP.h | 434 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E) macro
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/k6lite/mvop/ |
| H A D | regMVOP.h | 426 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0xAE) macro
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| H A D | halMVOP.c | 1504 …HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x4, CKG_DC0_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4… in HAL_MVOP_SetDCSRAMClk()
1506 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC0_SRAM); in HAL_MVOP_SetDCSRAMClk()
4704 …HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x40, CKG_DC1_SRAM); //Dc1 enable & dc1_mfdec_en =0 57[7:4]= 0… in HAL_MVOP_SubSetDCSRAMClk()
4706 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC1_SRAM); in HAL_MVOP_SubSetDCSRAMClk()
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| /utopia/UTPA2-700.0.x/modules/mvop/hal/maxim/mvop/ |
| H A D | regMVOP.h | 419 #define REG_CKG_DC_SRAM (CHIP_REG_BASE + 0x9E) macro
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