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Searched refs:REG (Results 1 – 25 of 50) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/include/
H A DMaserati_Bandwidth_RegTable.c23 { REG(0x162200), 0xFF, 0xFF, 0x15 },//Same mark
24 { REG(0x162201), 0xFF, 0xFF, 0x80 },//Same mark
25 { REG(0x101240), 0xFF, 0xFF, 0x15 },
26 { REG(0x101241), 0xFF, 0xFF, 0x80 },
27 { REG(0x101242), 0xFF, 0xFF, 0x08 },
28 { REG(0x101243), 0xFF, 0xFF, 0x20 },
29 { REG(0x101244), 0xFF, 0xFF, 0x00 },
30 { REG(0x101245), 0xFF, 0xFF, 0x04 },
31 { REG(0x101248), 0xFF, 0xFF, 0xFF },
32 { REG(0x101249), 0xFF, 0xFF, 0xFF },
[all …]
H A DManhattan_Bandwidth_RegTable.c23 { REG(0x101240), 0xFF, 0xFF, 0x15 },
24 { REG(0x101241), 0xFF, 0xFF, 0x80 },
25 { REG(0x101242), 0xFF, 0xFF, 0x08 },
26 { REG(0x101243), 0xFF, 0xFF, 0x20 },
27 { REG(0x101244), 0xFF, 0xFF, 0x00 },
28 { REG(0x101245), 0xFF, 0xFF, 0x04 },
29 { REG(0x101248), 0xFF, 0xFF, 0xFF },
30 { REG(0x101249), 0xFF, 0xFF, 0xFF },
31 { REG(0x10125C), 0xFF, 0xFF, 0x02 },
32 { REG(0x10125D), 0xFF, 0xFF, 0x00 },
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/M7621/pq/include/
H A DMaserati_Bandwidth_RegTable.c23 { REG(0x101240), 0xFF, 0xFF, 0x15 },
24 { REG(0x101241), 0xFF, 0xFF, 0x80 },
25 { REG(0x101242), 0xFF, 0xFF, 0x08 },
26 { REG(0x101243), 0xFF, 0xFF, 0x20 },
27 { REG(0x101244), 0xFF, 0xFF, 0x00 },
28 { REG(0x101245), 0xFF, 0xFF, 0x04 },
29 { REG(0x101248), 0xFF, 0xFF, 0xFF },
30 { REG(0x101249), 0xFF, 0xFF, 0xFF },
31 { REG(0x101260), 0xFF, 0xFF, 0x15 },
32 { REG(0x101261), 0xFF, 0xFF, 0x80 },
[all …]
H A DManhattan_Bandwidth_RegTable.c23 { REG(0x101240), 0xFF, 0xFF, 0x15 },
24 { REG(0x101241), 0xFF, 0xFF, 0x80 },
25 { REG(0x101242), 0xFF, 0xFF, 0x08 },
26 { REG(0x101243), 0xFF, 0xFF, 0x20 },
27 { REG(0x101244), 0xFF, 0xFF, 0x00 },
28 { REG(0x101245), 0xFF, 0xFF, 0x04 },
29 { REG(0x101248), 0xFF, 0xFF, 0xFF },
30 { REG(0x101249), 0xFF, 0xFF, 0xFF },
31 { REG(0x10125C), 0xFF, 0xFF, 0x02 },
32 { REG(0x10125D), 0xFF, 0xFF, 0x00 },
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/include/
H A DMaserati_Bandwidth_RegTable.c23 { REG(0x101240), 0xFF, 0xFF, 0x15 },
24 { REG(0x101241), 0xFF, 0xFF, 0x80 },
25 { REG(0x101242), 0xFF, 0xFF, 0x08 },
26 { REG(0x101243), 0xFF, 0xFF, 0x20 },
27 { REG(0x101244), 0xFF, 0xFF, 0x00 },
28 { REG(0x101245), 0xFF, 0xFF, 0x04 },
29 { REG(0x101248), 0xFF, 0xFF, 0xFF },
30 { REG(0x101249), 0xFF, 0xFF, 0xFF },
31 { REG(0x101260), 0xFF, 0xFF, 0x15 },
32 { REG(0x101261), 0xFF, 0xFF, 0x80 },
[all …]
H A DManhattan_Bandwidth_RegTable.c23 { REG(0x101240), 0xFF, 0xFF, 0x15 },
24 { REG(0x101241), 0xFF, 0xFF, 0x80 },
25 { REG(0x101242), 0xFF, 0xFF, 0x08 },
26 { REG(0x101243), 0xFF, 0xFF, 0x20 },
27 { REG(0x101244), 0xFF, 0xFF, 0x00 },
28 { REG(0x101245), 0xFF, 0xFF, 0x04 },
29 { REG(0x101248), 0xFF, 0xFF, 0xFF },
30 { REG(0x101249), 0xFF, 0xFF, 0xFF },
31 { REG(0x10125C), 0xFF, 0xFF, 0x02 },
32 { REG(0x10125D), 0xFF, 0xFF, 0x00 },
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/include/
H A DMaserati_Bandwidth_RegTable.c23 { REG(0x101240), 0xFF, 0xFF, 0x15 },
24 { REG(0x101241), 0xFF, 0xFF, 0x80 },
25 { REG(0x101242), 0xFF, 0xFF, 0x08 },
26 { REG(0x101243), 0xFF, 0xFF, 0x20 },
27 { REG(0x101244), 0xFF, 0xFF, 0x00 },
28 { REG(0x101245), 0xFF, 0xFF, 0x04 },
29 { REG(0x101248), 0xFF, 0xFF, 0xFF },
30 { REG(0x101249), 0xFF, 0xFF, 0xFF },
31 { REG(0x101260), 0xFF, 0xFF, 0x15 },
32 { REG(0x101261), 0xFF, 0xFF, 0x80 },
[all …]
H A DManhattan_Bandwidth_RegTable.c23 { REG(0x101240), 0xFF, 0xFF, 0x15 },
24 { REG(0x101241), 0xFF, 0xFF, 0x80 },
25 { REG(0x101242), 0xFF, 0xFF, 0x08 },
26 { REG(0x101243), 0xFF, 0xFF, 0x20 },
27 { REG(0x101244), 0xFF, 0xFF, 0x00 },
28 { REG(0x101245), 0xFF, 0xFF, 0x04 },
29 { REG(0x101248), 0xFF, 0xFF, 0xFF },
30 { REG(0x101249), 0xFF, 0xFF, 0xFF },
31 { REG(0x10125C), 0xFF, 0xFF, 0x02 },
32 { REG(0x10125D), 0xFF, 0xFF, 0x00 },
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/manhattan/pq/include/
H A DManhattan_Bandwidth_RegTable.c23 { REG(0x101240), 0xFF, 0xFF, 0x15 },
24 { REG(0x101241), 0xFF, 0xFF, 0x80 },
25 { REG(0x101242), 0xFF, 0xFF, 0x08 },
26 { REG(0x101243), 0xFF, 0xFF, 0x20 },
27 { REG(0x101244), 0xFF, 0xFF, 0x00 },
28 { REG(0x101245), 0xFF, 0xFF, 0x04 },
29 { REG(0x101248), 0xFF, 0xFF, 0xFF },
30 { REG(0x101249), 0xFF, 0xFF, 0xFF },
31 { REG(0x10125C), 0xFF, 0xFF, 0x02 },
32 { REG(0x10125D), 0xFF, 0xFF, 0x00 },
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/mooney/pq/include/
H A DMooney_Bandwidth_RegTable.c23 { REG(0x101240), 0xFF, 0xFF, 0x15 },
24 { REG(0x101241), 0xFF, 0xFF, 0x80 },
25 { REG(0x101242), 0xFF, 0xFF, 0x08 },
26 { REG(0x101243), 0xFF, 0xFF, 0x20 },
27 { REG(0x101244), 0xFF, 0xFF, 0x00 },
28 { REG(0x101245), 0xFF, 0xFF, 0x04 },
29 { REG(0x101248), 0xFF, 0xFF, 0xFF },
30 { REG(0x101249), 0xFF, 0xFF, 0xFF },
31 { REG(0x101260), 0xFF, 0xFF, 0x15 },
32 { REG(0x101261), 0xFF, 0xFF, 0x80 },
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/k6lite/pq/include/
H A Dk6lite_Bandwidth_RegTable.c23 { REG(0x101240), 0xFF, 0xFF, 0x11 },
24 { REG(0x101241), 0xFF, 0xFF, 0x80 },
25 { REG(0x101242), 0xFF, 0xFF, 0x08 },
26 { REG(0x101243), 0xFF, 0xFF, 0x20 },
27 { REG(0x101244), 0xFF, 0xFF, 0x00 },
28 { REG(0x101245), 0xFF, 0xFF, 0x04 },
29 { REG(0x101248), 0xFF, 0xFF, 0xFF },
30 { REG(0x101249), 0xFF, 0xFF, 0xFF },
31 { REG(0x101260), 0xFF, 0xFF, 0x11 },
32 { REG(0x101261), 0xFF, 0xFF, 0x80 },
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/k6/pq/include/
H A Dk6_Bandwidth_RegTable.c23 { REG(0x101240), 0xFF, 0xFF, 0x15 },
24 { REG(0x101241), 0xFF, 0xFF, 0x80 },
25 { REG(0x101242), 0xFF, 0xFF, 0x08 },
26 { REG(0x101243), 0xFF, 0xFF, 0x20 },
27 { REG(0x101244), 0xFF, 0xFF, 0x00 },
28 { REG(0x101245), 0xFF, 0xFF, 0x04 },
29 { REG(0x101248), 0xFF, 0xFF, 0xFF },
30 { REG(0x101249), 0xFF, 0xFF, 0xFF },
31 { REG(0x101260), 0xFF, 0xFF, 0x15 },
32 { REG(0x101261), 0xFF, 0xFF, 0x80 },
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/kano/pq/include/
H A DKano_Bandwidth_RegTable.c23 { REG(0x101240), 0xFF, 0xFF, 0x15 },
24 { REG(0x101241), 0xFF, 0xFF, 0x80 },
25 { REG(0x101242), 0xFF, 0xFF, 0x08 },
26 { REG(0x101243), 0xFF, 0xFF, 0x20 },
27 { REG(0x101244), 0xFF, 0xFF, 0x00 },
28 { REG(0x101245), 0xFF, 0xFF, 0x04 },
29 { REG(0x101248), 0xFF, 0xFF, 0xFF },
30 { REG(0x101249), 0xFF, 0xFF, 0xFF },
31 { REG(0x101260), 0xFF, 0xFF, 0x15 },
32 { REG(0x101261), 0xFF, 0xFF, 0x80 },
[all …]
/utopia/UTPA2-700.0.x/modules/pq/hal/curry/pq/include/
H A DCurry_Bandwidth_RegTable.c23 { REG(0x101240), 0xFF, 0xFF, 0x15 },
24 { REG(0x101241), 0xFF, 0xFF, 0x80 },
25 { REG(0x101242), 0xFF, 0xFF, 0x08 },
26 { REG(0x101243), 0xFF, 0xFF, 0x20 },
27 { REG(0x101244), 0xFF, 0xFF, 0x00 },
28 { REG(0x101245), 0xFF, 0xFF, 0x04 },
29 { REG(0x101248), 0xFF, 0xFF, 0xFF },
30 { REG(0x101249), 0xFF, 0xFF, 0xFF },
31 { REG(0x101260), 0xFF, 0xFF, 0x15 },
32 { REG(0x101261), 0xFF, 0xFF, 0x80 },
[all …]
H A DKano_Bandwidth_RegTable.c23 { REG(0x101240), 0xFF, 0xFF, 0x15 },
24 { REG(0x101241), 0xFF, 0xFF, 0x80 },
25 { REG(0x101242), 0xFF, 0xFF, 0x08 },
26 { REG(0x101243), 0xFF, 0xFF, 0x20 },
27 { REG(0x101244), 0xFF, 0xFF, 0x00 },
28 { REG(0x101245), 0xFF, 0xFF, 0x04 },
29 { REG(0x101248), 0xFF, 0xFF, 0xFF },
30 { REG(0x101249), 0xFF, 0xFF, 0xFF },
31 { REG(0x101260), 0xFF, 0xFF, 0x15 },
32 { REG(0x101261), 0xFF, 0xFF, 0x80 },
[all …]
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6/hdmitx/
H A DhalHDMIUtilTx.c132 #define REG(bank, addr) (*((volatile MS_U16 *)((_gPM_MapBase+(bank<<1U)) + ((addr)<<2U… macro
142 #define i2cSetSCL(pin_state) ( REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) = (REG(HDMI…
143 #define i2cSetSDA(pin_state) ( REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) = (REG(HDMI…
144 #define i2cSCL_PIN_STATUS ( (REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) & BIT0) >>…
145 #define i2cSDA_PIN_STATUS ( (REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) & BIT4) >>…
736 return(REG(bank, address)); in MHal_HDMITx_Read()
752 REG(bank, address) = reg_data; in MHal_HDMITx_Write()
771 reg_value = (REG(bank, address) & (~reg_mask)) | (reg_data & reg_mask); in MHal_HDMITx_Mask_Write()
772 REG(bank, address) = reg_value; in MHal_HDMITx_Mask_Write()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/M7621/hdmitx/
H A DhalHDMIUtilTx.c132 #define REG(bank, addr) (*((volatile MS_U16 *)((_gPM_MapBase+(bank<<1U)) + ((addr)<<2U… macro
142 #define i2cSetSCL(pin_state) ( REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) = (REG(HDMI…
143 #define i2cSetSDA(pin_state) ( REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) = (REG(HDMI…
144 #define i2cSCL_PIN_STATUS ( (REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) & BIT0) >>…
145 #define i2cSDA_PIN_STATUS ( (REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) & BIT4) >>…
736 return(REG(bank, address)); in MHal_HDMITx_Read()
752 REG(bank, address) = reg_data; in MHal_HDMITx_Write()
771 reg_value = (REG(bank, address) & (~reg_mask)) | (reg_data & reg_mask); in MHal_HDMITx_Mask_Write()
772 REG(bank, address) = reg_value; in MHal_HDMITx_Mask_Write()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/k6lite/hdmitx/
H A DhalHDMIUtilTx.c132 #define REG(bank, addr) (*((volatile MS_U16 *)((_gPM_MapBase+(bank<<1U)) + ((addr)<<2U… macro
142 #define i2cSetSCL(pin_state) ( REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) = (REG(HDMI…
143 #define i2cSetSDA(pin_state) ( REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) = (REG(HDMI…
144 #define i2cSCL_PIN_STATUS ( (REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) & BIT0) >>…
145 #define i2cSDA_PIN_STATUS ( (REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) & BIT4) >>…
736 return(REG(bank, address)); in MHal_HDMITx_Read()
752 REG(bank, address) = reg_data; in MHal_HDMITx_Write()
771 reg_value = (REG(bank, address) & (~reg_mask)) | (reg_data & reg_mask); in MHal_HDMITx_Mask_Write()
772 REG(bank, address) = reg_value; in MHal_HDMITx_Mask_Write()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/curry/hdmitx/
H A DhalHDMIUtilTx.c132 #define REG(bank, addr) (*((volatile MS_U16 *)((_gPM_MapBase+(bank<<1U)) + ((addr)<<2U… macro
142 #define i2cSetSCL(pin_state) ( REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) = (REG(HDMI…
143 #define i2cSetSDA(pin_state) ( REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) = (REG(HDMI…
144 #define i2cSCL_PIN_STATUS ( (REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) & BIT0) >>…
145 #define i2cSDA_PIN_STATUS ( (REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) & BIT4) >>…
736 return(REG(bank, address)); in MHal_HDMITx_Read()
752 REG(bank, address) = reg_data; in MHal_HDMITx_Write()
771 reg_value = (REG(bank, address) & (~reg_mask)) | (reg_data & reg_mask); in MHal_HDMITx_Mask_Write()
772 REG(bank, address) = reg_value; in MHal_HDMITx_Mask_Write()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/kano/hdmitx/
H A DhalHDMIUtilTx.c132 #define REG(bank, addr) (*((volatile MS_U16 *)((_gPM_MapBase+(bank<<1U)) + ((addr)<<2U… macro
142 #define i2cSetSCL(pin_state) ( REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) = (REG(HDMI…
143 #define i2cSetSDA(pin_state) ( REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) = (REG(HDMI…
144 #define i2cSCL_PIN_STATUS ( (REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) & BIT0) >>…
145 #define i2cSDA_PIN_STATUS ( (REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) & BIT4) >>…
736 return(REG(bank, address)); in MHal_HDMITx_Read()
752 REG(bank, address) = reg_data; in MHal_HDMITx_Write()
771 reg_value = (REG(bank, address) & (~reg_mask)) | (reg_data & reg_mask); in MHal_HDMITx_Mask_Write()
772 REG(bank, address) = reg_value; in MHal_HDMITx_Mask_Write()
/utopia/UTPA2-700.0.x/modules/hdmi/hal/maxim/hdmitx/
H A DhalHDMIUtilTx.c132 #define REG(bank, addr) (*((volatile MS_U16 *)((_gPM_MapBase+(bank<<1U)) + ((addr)<<2U… macro
142 #define i2cSetSCL(pin_state) ( REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) = (REG(HDMI…
143 #define i2cSetSDA(pin_state) ( REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) = (REG(HDMI…
144 #define i2cSCL_PIN_STATUS ( (REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) & BIT0) >>…
145 #define i2cSDA_PIN_STATUS ( (REG(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_01) & BIT4) >>…
736 return(REG(bank, address)); in MHal_HDMITx_Read()
752 REG(bank, address) = reg_data; in MHal_HDMITx_Write()
771 reg_value = (REG(bank, address) & (~reg_mask)) | (reg_data & reg_mask); in MHal_HDMITx_Mask_Write()
772 REG(bank, address) = reg_value; in MHal_HDMITx_Mask_Write()
/utopia/UTPA2-700.0.x/modules/pwm/hal/mustang/pwm/
H A DhalPWM.h122 #define SETBIT(REG, BIT) ((REG) |= (1UL << (BIT))) argument
123 #define CLRBIT(REG, BIT) ((REG) &= ~(1UL << (BIT))) argument
124 #define GETBIT(REG, BIT) (((REG) >> (BIT)) & 0x01UL) argument
/utopia/UTPA2-700.0.x/modules/pwm/hal/macan/pwm/
H A DhalPWM.h138 #define SETBIT(REG, BIT) ((REG) |= (1UL << (BIT))) argument
139 #define CLRBIT(REG, BIT) ((REG) &= ~(1UL << (BIT))) argument
140 #define GETBIT(REG, BIT) (((REG) >> (BIT)) & 0x01UL) argument
/utopia/UTPA2-700.0.x/modules/pwm/hal/maldives/pwm/
H A DhalPWM.h122 #define SETBIT(REG, BIT) ((REG) |= (1UL << (BIT))) argument
123 #define CLRBIT(REG, BIT) ((REG) &= ~(1UL << (BIT))) argument
124 #define GETBIT(REG, BIT) (((REG) >> (BIT)) & 0x01UL) argument
/utopia/UTPA2-700.0.x/modules/pwm/hal/mooney/pwm/
H A DhalPWM.h138 #define SETBIT(REG, BIT) ((REG) |= (1UL << (BIT))) argument
139 #define CLRBIT(REG, BIT) ((REG) &= ~(1UL << (BIT))) argument
140 #define GETBIT(REG, BIT) (((REG) >> (BIT)) & 0x01UL) argument

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