1 //////////////////////////////////////////////////////////////////////////////// 2 // 3 // Copyright (c) 2006-2008 MStar Semiconductor, Inc. 4 // All rights reserved. 5 // 6 // Unless otherwise stipulated in writing, any and all information contained 7 // herein regardless in any format shall remain the sole proprietary of 8 // MStar Semiconductor Inc. and be kept in strict confidence 9 // (; MStar; Confidential; Information; ) by the recipient. 10 // Any unauthorized act including without limitation unauthorized disclosure, 11 // copying, use, reproduction, sale, distribution, modification, disassembling, 12 // reverse engineering and compiling of the contents of MStar Confidential 13 // Information is unlawful and strictly prohibited. MStar hereby reserves the 14 // rights to any and all damages, losses, costs and expenses resulting therefrom. 15 // 16 17 18 //**************************************************** 19 // DDR1300MHz 20 //**************************************************** 21 code U8 BWTABLE_COM[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+1] = 22 {//Reg Bank Mask Value 23 { REG(0x101240), 0xFF, 0xFF, 0x15 }, 24 { REG(0x101241), 0xFF, 0xFF, 0x80 }, 25 { REG(0x101242), 0xFF, 0xFF, 0x08 }, 26 { REG(0x101243), 0xFF, 0xFF, 0x20 }, 27 { REG(0x101244), 0xFF, 0xFF, 0x00 }, 28 { REG(0x101245), 0xFF, 0xFF, 0x04 }, 29 { REG(0x101248), 0xFF, 0xFF, 0xFF }, 30 { REG(0x101249), 0xFF, 0xFF, 0xFF }, 31 { REG(0x101260), 0xFF, 0xFF, 0x15 }, 32 { REG(0x101261), 0xFF, 0xFF, 0x80 }, 33 { REG(0x101262), 0xFF, 0xFF, 0x08 }, 34 { REG(0x101263), 0xFF, 0xFF, 0x20 }, 35 { REG(0x101264), 0xFF, 0xFF, 0x00 }, 36 { REG(0x101265), 0xFF, 0xFF, 0x04 }, 37 { REG(0x101268), 0xFF, 0xFF, 0xF9 }, 38 { REG(0x101269), 0xFF, 0xFF, 0xFF }, 39 { REG(0x101280), 0xFF, 0xFF, 0x15 }, 40 { REG(0x101281), 0xFF, 0xFF, 0x80 }, 41 { REG(0x101282), 0xFF, 0xFF, 0x08 }, 42 { REG(0x101283), 0xFF, 0xFF, 0x20 }, 43 { REG(0x101284), 0xFF, 0xFF, 0x00 }, 44 { REG(0x101285), 0xFF, 0xFF, 0x04 }, 45 { REG(0x101288), 0xFF, 0xFF, 0xFF }, 46 { REG(0x101289), 0xFF, 0xFF, 0xFF }, 47 { REG(0x1012A0), 0xFF, 0xFF, 0x15 }, 48 { REG(0x1012A1), 0xFF, 0xFF, 0x80 }, 49 { REG(0x1012A2), 0xFF, 0xFF, 0x08 }, 50 { REG(0x1012A3), 0xFF, 0xFF, 0x20 }, 51 { REG(0x1012A4), 0xFF, 0xFF, 0x00 }, 52 { REG(0x1012A5), 0xFF, 0xFF, 0x04 }, 53 { REG(0x1012A8), 0xFF, 0xFF, 0xFF }, 54 { REG(0x1012A9), 0xFF, 0xFF, 0xFF }, 55 { REG(0x1012FE), 0xFF, 0xFF, 0xE1 }, 56 { REG(0x1012FF), 0xFF, 0x9F, 0x09 }, 57 { REG(0x100640), 0xFF, 0xFF, 0x15 }, 58 { REG(0x100641), 0xFF, 0xFF, 0x80 }, 59 { REG(0x100642), 0xFF, 0xFF, 0x08 }, 60 { REG(0x100643), 0xFF, 0xFF, 0x20 }, 61 { REG(0x100644), 0xFF, 0xFF, 0x00 }, 62 { REG(0x100645), 0xFF, 0xFF, 0x04 }, 63 { REG(0x100648), 0xFF, 0xFF, 0xFF }, 64 { REG(0x100649), 0xFF, 0xFF, 0xFF }, 65 { REG(0x100660), 0xFF, 0xFF, 0x15 }, 66 { REG(0x100661), 0xFF, 0xFF, 0x80 }, 67 { REG(0x100662), 0xFF, 0xFF, 0x08 }, 68 { REG(0x100663), 0xFF, 0xFF, 0x20 }, 69 { REG(0x100664), 0xFF, 0xFF, 0x00 }, 70 { REG(0x100665), 0xFF, 0xFF, 0x04 }, 71 { REG(0x100668), 0xFF, 0xFF, 0xFF }, 72 { REG(0x100669), 0xFF, 0xFF, 0xFF }, 73 { REG(0x100680), 0xFF, 0xFF, 0x15 }, 74 { REG(0x100681), 0xFF, 0xFF, 0x80 }, 75 { REG(0x100682), 0xFF, 0xFF, 0x08 }, 76 { REG(0x100683), 0xFF, 0xFF, 0x20 }, 77 { REG(0x100684), 0xFF, 0xFF, 0x00 }, 78 { REG(0x100685), 0xFF, 0xFF, 0x04 }, 79 { REG(0x100688), 0xFF, 0xFF, 0xFF }, 80 { REG(0x100689), 0xFF, 0xFF, 0xFF }, 81 { REG(0x1006A0), 0xFF, 0xFF, 0x15 }, 82 { REG(0x1006A1), 0xFF, 0xFF, 0x80 }, 83 { REG(0x1006A2), 0xFF, 0xFF, 0x08 }, 84 { REG(0x1006A3), 0xFF, 0xFF, 0x20 }, 85 { REG(0x1006A4), 0xFF, 0xFF, 0x00 }, 86 { REG(0x1006A5), 0xFF, 0xFF, 0x04 }, 87 { REG(0x1006A8), 0xFF, 0xFF, 0xFF }, 88 { REG(0x1006A9), 0xFF, 0xFF, 0xFF }, 89 { REG(0x161500), 0xFF, 0xFF, 0x15 }, 90 { REG(0x161501), 0xFF, 0xFF, 0x80 }, 91 { REG(0x161502), 0xFF, 0xFF, 0x08 }, 92 { REG(0x161503), 0xFF, 0xFF, 0x20 }, 93 { REG(0x161504), 0xFF, 0xFF, 0x00 }, 94 { REG(0x161505), 0xFF, 0xFF, 0x04 }, 95 { REG(0x161508), 0xFF, 0xFF, 0xDC }, 96 { REG(0x161509), 0xFF, 0xFF, 0xFF }, 97 { REG(0x16151C), 0xFF, 0xFF, 0x01 }, 98 { REG(0x16151D), 0xFF, 0xFF, 0x00 }, 99 { REG(0x161520), 0xFF, 0xFF, 0x15 }, 100 { REG(0x161521), 0xFF, 0xFF, 0x80 }, 101 { REG(0x161522), 0xFF, 0xFF, 0x10 }, 102 { REG(0x161523), 0xFF, 0xFF, 0x20 }, 103 { REG(0x161524), 0xFF, 0xFF, 0x00 }, 104 { REG(0x161525), 0xFF, 0xFF, 0x04 }, 105 { REG(0x161528), 0xFF, 0xFF, 0x91 }, 106 { REG(0x161529), 0xFF, 0xFF, 0xF8 }, 107 { REG(0x1615BE), 0xFF, 0xFF, 0x90 },//Same mark 108 { REG(0x1615BF), 0xFF, 0xFF, 0x01 },//Same mark 109 { REG(0x1615CC), 0xFF, 0xFF, 0x18 }, 110 { REG(0x1615CD), 0xFF, 0xFF, 0x04 }, 111 { REG(0x1615CE), 0xFF, 0xFF, 0x02 }, 112 { REG(0x1615CF), 0xFF, 0xFF, 0x00 }, 113 { REG(0x1615E2), 0xFF, 0xFF, 0x1E }, 114 { REG(0x1615E3), 0xFF, 0xFF, 0x00 }, 115 { REG(0x1615E8), 0xFF, 0xFF, 0x18 }, 116 { REG(0x1615E9), 0xFF, 0xFF, 0x00 }, 117 { REG(0x1615EA), 0xFF, 0xFF, 0x80 }, 118 { REG(0x1615EB), 0xFF, 0xFF, 0x04 }, 119 { REG(0x1615EC), 0xFF, 0xFF, 0x02 }, 120 { REG(0x1615ED), 0xFF, 0xFF, 0x02 }, 121 { REG(0x1615FE), 0xFF, 0xFF, 0xE1 }, 122 { REG(0x1615FF), 0xFF, 0xFF, 0x03 }, 123 { REG(0x1615E0), 0xFF, 0xFF, 0x02 },//Same mark 124 { REG(0x1615E1), 0xFF, 0xFF, 0x00 },//Same mark 125 { REG(0x162202), 0xFF, 0xFF, 0x08 }, 126 { REG(0x162203), 0xFF, 0xFF, 0x20 }, 127 { REG(0x162204), 0xFF, 0xFF, 0x00 }, 128 { REG(0x162205), 0xFF, 0xFF, 0x04 }, 129 { REG(0x162208), 0xFF, 0xFF, 0xFF }, 130 { REG(0x162209), 0xFF, 0xFF, 0xFF }, 131 { REG(0x162220), 0xFF, 0xFF, 0x15 }, 132 { REG(0x162221), 0xFF, 0xFF, 0x80 }, 133 { REG(0x162222), 0xFF, 0xFF, 0x10 }, 134 { REG(0x162223), 0xFF, 0xFF, 0x20 }, 135 { REG(0x162224), 0xFF, 0xFF, 0x00 }, 136 { REG(0x162225), 0xFF, 0xFF, 0x04 }, 137 { REG(0x162228), 0xFF, 0xFF, 0xFF }, 138 { REG(0x162229), 0xFF, 0xFF, 0xFF }, 139 { REG(0x1622BE), 0xFF, 0xFF, 0x90 },//Same mark 140 { REG(0x1622BF), 0xFF, 0xFF, 0x01 },//Same mark 141 { REG(0x1622CC), 0xFF, 0xFF, 0x18 }, 142 { REG(0x1622CD), 0xFF, 0xFF, 0x04 }, 143 { REG(0x1622CE), 0xFF, 0xFF, 0x02 }, 144 { REG(0x1622CF), 0xFF, 0xFF, 0x00 }, 145 { REG(0x1622E2), 0xFF, 0xFF, 0x1E }, 146 { REG(0x1622E3), 0xFF, 0xFF, 0x00 }, 147 { REG(0x1622E8), 0xFF, 0xFF, 0x18 }, 148 { REG(0x1622E9), 0xFF, 0xFF, 0x00 }, 149 { REG(0x1622EA), 0xFF, 0xFF, 0x10 }, 150 { REG(0x1622EB), 0xFF, 0xFF, 0x04 }, 151 { REG(0x1622EC), 0xFF, 0xFF, 0x02 }, 152 { REG(0x1622ED), 0xFF, 0xFF, 0x02 }, 153 { REG(0x1622FE), 0xFF, 0xFF, 0xE1 }, 154 { REG(0x1622FF), 0xFF, 0xFF, 0x03 }, 155 { REG(0x1622E0), 0xFF, 0xFF, 0x02 },//Same mark 156 { REG(0x1622E1), 0xFF, 0xFF, 0x00 },//Same mark 157 { REG(REG_TABLE_END), 0x00, 0x00 } 158 }; 159 160 code U8 BWTABLE[][REG_BW_ADDR_SIZE+REG_BW_BANK_SIZE+REG_BW_MASK_SIZE+BWTABLE_NUMS]= 161 {//Reg Bank Mask Value 162 { REG(REG_TABLE_END), 0x00, 0x00 } 163 }; 164 165 166