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Searched refs:PM_REG_BASE (Results 1 – 25 of 29) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/pm/hal/manhattan/pm/
H A DregPM.h119 #define PM_REG_BASE (0x0700UL*2) macro
124 #define REG_PM_DUMMY_ACTIVE_STANDBY ((PM_REG_BASE + 0x38*2+0))
125 #define REG_PM_DUMMY_POWERON_MODE ((PM_REG_BASE + 0x38UL*2+1))
126 #define REG_PM_DUMMY_WAKEUP_SOURCE ((PM_REG_BASE + 0x39UL*2+0))
127 #define REG_PM_DUMMY_RT51_STATUS ((PM_REG_BASE + 0x39UL*2+1))
128 #define REG_PM_CKG_RTC ((PM_REG_BASE + 0x22UL*2+0))
129 #define REG_PM_CHIP_CFG_OVERWRITE ((PM_REG_BASE + 0x1FUL*2+0))
135 #define PM_REG1_ScratchPad ((PM_REG_BASE + 0x52UL*2))
136 #define PM_REG2_ScratchPad ((PM_REG_BASE + 0x53UL*2))
137 #define PM_REG3_ScratchPad ((PM_REG_BASE + 0x54UL*2))
[all …]
/utopia/UTPA2-700.0.x/modules/pm/hal/maserati/pm/
H A DregPM.h119 #define PM_REG_BASE (0x0700UL*2) macro
124 #define REG_PM_DUMMY_ACTIVE_STANDBY ((PM_REG_BASE + 0x38*2+0))
125 #define REG_PM_DUMMY_POWERON_MODE ((PM_REG_BASE + 0x38UL*2+1))
126 #define REG_PM_DUMMY_WAKEUP_SOURCE ((PM_REG_BASE + 0x39UL*2+0))
127 #define REG_PM_DUMMY_RT51_STATUS ((PM_REG_BASE + 0x39UL*2+1))
128 #define REG_PM_CKG_RTC ((PM_REG_BASE + 0x22UL*2+0))
129 #define REG_PM_CHIP_CFG_OVERWRITE ((PM_REG_BASE + 0x1FUL*2+0))
135 #define PM_REG1_ScratchPad ((PM_REG_BASE + 0x52UL*2))
136 #define PM_REG2_ScratchPad ((PM_REG_BASE + 0x53UL*2))
137 #define PM_REG3_ScratchPad ((PM_REG_BASE + 0x54UL*2))
[all …]
/utopia/UTPA2-700.0.x/modules/pm/hal/M7821/pm/
H A DregPM.h119 #define PM_REG_BASE (0x0700UL*2) macro
124 #define REG_PM_DUMMY_ACTIVE_STANDBY ((PM_REG_BASE + 0x38*2+0))
125 #define REG_PM_DUMMY_POWERON_MODE ((PM_REG_BASE + 0x38UL*2+1))
126 #define REG_PM_DUMMY_WAKEUP_SOURCE ((PM_REG_BASE + 0x39UL*2+0))
127 #define REG_PM_DUMMY_RT51_STATUS ((PM_REG_BASE + 0x39UL*2+1))
128 #define REG_PM_CKG_RTC ((PM_REG_BASE + 0x22UL*2+0))
129 #define REG_PM_CHIP_CFG_OVERWRITE ((PM_REG_BASE + 0x1FUL*2+0))
135 #define PM_REG1_ScratchPad ((PM_REG_BASE + 0x52UL*2))
136 #define PM_REG2_ScratchPad ((PM_REG_BASE + 0x53UL*2))
137 #define PM_REG3_ScratchPad ((PM_REG_BASE + 0x54UL*2))
[all …]
/utopia/UTPA2-700.0.x/modules/pm/hal/M7621/pm/
H A DregPM.h119 #define PM_REG_BASE (0x0700UL*2) macro
124 #define REG_PM_DUMMY_ACTIVE_STANDBY ((PM_REG_BASE + 0x38*2+0))
125 #define REG_PM_DUMMY_POWERON_MODE ((PM_REG_BASE + 0x38UL*2+1))
126 #define REG_PM_DUMMY_WAKEUP_SOURCE ((PM_REG_BASE + 0x39UL*2+0))
127 #define REG_PM_DUMMY_RT51_STATUS ((PM_REG_BASE + 0x39UL*2+1))
128 #define REG_PM_CKG_RTC ((PM_REG_BASE + 0x22UL*2+0))
129 #define REG_PM_CHIP_CFG_OVERWRITE ((PM_REG_BASE + 0x1FUL*2+0))
135 #define PM_REG1_ScratchPad ((PM_REG_BASE + 0x52UL*2))
136 #define PM_REG2_ScratchPad ((PM_REG_BASE + 0x53UL*2))
137 #define PM_REG3_ScratchPad ((PM_REG_BASE + 0x54UL*2))
[all …]
/utopia/UTPA2-700.0.x/modules/pm/hal/maxim/pm/
H A DregPM.h119 #define PM_REG_BASE (0x0700UL*2) macro
124 #define REG_PM_DUMMY_ACTIVE_STANDBY ((PM_REG_BASE + 0x38*2+0))
125 #define REG_PM_DUMMY_POWERON_MODE ((PM_REG_BASE + 0x38UL*2+1))
126 #define REG_PM_DUMMY_WAKEUP_SOURCE ((PM_REG_BASE + 0x39UL*2+0))
127 #define REG_PM_DUMMY_RT51_STATUS ((PM_REG_BASE + 0x39UL*2+1))
128 #define REG_PM_CKG_RTC ((PM_REG_BASE + 0x22UL*2+0))
129 #define REG_PM_CHIP_CFG_OVERWRITE ((PM_REG_BASE + 0x1FUL*2+0))
135 #define PM_REG1_ScratchPad ((PM_REG_BASE + 0x52UL*2))
136 #define PM_REG2_ScratchPad ((PM_REG_BASE + 0x53UL*2))
137 #define PM_REG3_ScratchPad ((PM_REG_BASE + 0x54UL*2))
[all …]
/utopia/UTPA2-700.0.x/modules/pm/hal/mainz/pm/
H A DregPM.h115 #define PM_REG_BASE 0x0e00 //(0x0700*2) macro
126 #define REG_PM_GPIO_PM_LOCK ((PM_REG_BASE + 0x12UL * 2))
127 #define REG_PM_CKG_RTC ((PM_REG_BASE + 0x22UL * 2))
130 #define REG_PM_DUMMY_ACTIVE_STANDBY ((PM_REG_BASE + 0x38UL * 2))
131 #define REG_PM_DUMMY_POWERON_MODE ((PM_REG_BASE + 0x38UL * 2 + 1))
132 #define REG_PM_DUMMY_WAKEUP_SOURCE ((PM_REG_BASE + 0x39UL * 2))
134 #define PM_REG1_ScratchPad ((PM_REG_BASE + 0x52UL*2))
135 #define PM_REG2_ScratchPad ((PM_REG_BASE + 0x53UL*2))
136 #define PM_REG3_ScratchPad ((PM_REG_BASE + 0x54UL*2))
137 #define PM_REG4_ScratchPad ((PM_REG_BASE + 0x55UL*2))
/utopia/UTPA2-700.0.x/modules/pm/hal/macan/pm/
H A DregPM.h119 #define PM_REG_BASE (0x0700UL*2) macro
126 #define REG_PM_DUMMY_POWERON_MODE ((PM_REG_BASE + 0x38UL*2+1))
127 #define REG_PM_DUMMY_WAKEUP_SOURCE ((PM_REG_BASE + 0x39UL*2+0))
128 #define REG_PM_CKG_RTC ((PM_REG_BASE + 0x22UL*2+0))
129 #define REG_PM_CHIP_CFG_OVERWRITE ((PM_REG_BASE + 0x1FUL*2+0))
135 #define PM_REG1_ScratchPad ((PM_REG_BASE + 0x52UL*2))
136 #define PM_REG2_ScratchPad ((PM_REG_BASE + 0x53UL*2))
137 #define PM_REG3_ScratchPad ((PM_REG_BASE + 0x54UL*2))
138 #define PM_REG4_ScratchPad ((PM_REG_BASE + 0x55UL*2))
145 #define REG_PM_GPIO_PM_LOCK ((PM_REG_BASE + 0x12UL*2))
/utopia/UTPA2-700.0.x/modules/pm/hal/messi/pm/
H A DregPM.h115 #define PM_REG_BASE 0x0e00 //(0x0700*2) macro
126 #define REG_PM_GPIO_PM_LOCK ((PM_REG_BASE + 0x12UL * 2))
127 #define REG_PM_CKG_RTC ((PM_REG_BASE + 0x22UL * 2))
130 #define REG_PM_DUMMY_ACTIVE_STANDBY ((PM_REG_BASE + 0x38UL * 2))
131 #define REG_PM_DUMMY_POWERON_MODE ((PM_REG_BASE + 0x38UL * 2 + 1))
132 #define REG_PM_DUMMY_WAKEUP_SOURCE ((PM_REG_BASE + 0x39UL * 2))
134 #define PM_REG1_ScratchPad ((PM_REG_BASE + 0x52UL*2))
135 #define PM_REG2_ScratchPad ((PM_REG_BASE + 0x53UL*2))
136 #define PM_REG3_ScratchPad ((PM_REG_BASE + 0x54UL*2))
137 #define PM_REG4_ScratchPad ((PM_REG_BASE + 0x55UL*2))
/utopia/UTPA2-700.0.x/modules/pm/hal/mooney/pm/
H A DregPM.h115 #define PM_REG_BASE 0x0e00 //(0x0700*2) macro
126 #define REG_PM_GPIO_PM_LOCK ((PM_REG_BASE + 0x12UL * 2))
127 #define REG_PM_CKG_RTC ((PM_REG_BASE + 0x22UL * 2))
130 #define REG_PM_DUMMY_ACTIVE_STANDBY ((PM_REG_BASE + 0x38UL * 2))
131 #define REG_PM_DUMMY_POWERON_MODE ((PM_REG_BASE + 0x38UL * 2 + 1))
132 #define REG_PM_DUMMY_WAKEUP_SOURCE ((PM_REG_BASE + 0x39UL * 2))
134 #define PM_REG1_ScratchPad ((PM_REG_BASE + 0x52UL*2))
135 #define PM_REG2_ScratchPad ((PM_REG_BASE + 0x53UL*2))
136 #define PM_REG3_ScratchPad ((PM_REG_BASE + 0x54UL*2))
137 #define PM_REG4_ScratchPad ((PM_REG_BASE + 0x55UL*2))
/utopia/UTPA2-700.0.x/modules/pm/hal/maldives/pm/
H A DregPM.h115 #define PM_REG_BASE 0x0e00 //(0x0700*2) macro
125 #define REG_PM_GPIO_PM_LOCK ((PM_REG_BASE + 0x12 * 2))
126 #define REG_PM_CKG_RTC ((PM_REG_BASE + 0x22 * 2))
130 #define REG_PM_DUMMY_POWERON_MODE ((PM_REG_BASE + 0x38 * 2 + 1))
131 #define REG_PM_DUMMY_WAKEUP_SOURCE ((PM_REG_BASE + 0x39 * 2 + 0))
133 #define PM_REG1_ScratchPad ((PM_REG_BASE + 0x52 * 2))
134 #define PM_REG2_ScratchPad ((PM_REG_BASE + 0x53 * 2))
135 #define PM_REG3_ScratchPad ((PM_REG_BASE + 0x54 * 2))
136 #define PM_REG4_ScratchPad ((PM_REG_BASE + 0x55 * 2))
/utopia/UTPA2-700.0.x/modules/pm/hal/mustang/pm/
H A DregPM.h116 #define PM_REG_BASE 0x0e00 //(0x0700*2) macro
126 #define REG_PM_GPIO_PM_LOCK ((PM_REG_BASE + 0x12 * 2))
127 #define REG_PM_CKG_RTC ((PM_REG_BASE + 0x22 * 2))
131 #define REG_PM_DUMMY_POWERON_MODE ((PM_REG_BASE + 0x38 * 2 + 1))
132 #define REG_PM_DUMMY_WAKEUP_SOURCE ((PM_REG_BASE + 0x39 * 2 + 0))
134 #define PM_REG1_ScratchPad ((PM_REG_BASE + 0x52 * 2))
135 #define PM_REG2_ScratchPad ((PM_REG_BASE + 0x53 * 2))
136 #define PM_REG3_ScratchPad ((PM_REG_BASE + 0x54 * 2))
137 #define PM_REG4_ScratchPad ((PM_REG_BASE + 0x55 * 2))
/utopia/UTPA2-700.0.x/modules/pm/hal/kano/pm/
H A DregPM.h119 #define PM_REG_BASE (0x0700UL*2) macro
121 #define REG_PM_DUMMY_ACTIVE_STANDBY ((PM_REG_BASE + 0x3AUL*2+0))
122 #define REG_PM_DUMMY_POWERON_MODE ((PM_REG_BASE + 0x37UL*2+1))
123 #define REG_PM_DUMMY_WAKEUP_SOURCE ((PM_REG_BASE + 0x34UL*2+1))
124 #define REG_PM_DUMMY_WAKEUP_KEY ((PM_REG_BASE + 0x36UL*2+0))
125 #define REG_PM_DUMMY_RT51_STATUS ((PM_REG_BASE + 0x39UL*2+1))
126 #define REG_PM_CHIP_CFG_OVERWRITE ((PM_REG_BASE + 0x1FUL*2+0))
129 #define REG_PM_CPU_SW_RST ((PM_REG_BASE + 0x29UL*2+1))
/utopia/UTPA2-700.0.x/modules/pm/hal/k6/pm/
H A DregPM.h119 #define PM_REG_BASE (0x0700UL*2) macro
121 #define REG_PM_DUMMY_ACTIVE_STANDBY ((PM_REG_BASE + 0x3AUL*2+0))
122 #define REG_PM_DUMMY_POWERON_MODE ((PM_REG_BASE + 0x37UL*2+1))
123 #define REG_PM_DUMMY_WAKEUP_SOURCE ((PM_REG_BASE + 0x34UL*2+1))
124 #define REG_PM_DUMMY_WAKEUP_KEY ((PM_REG_BASE + 0x36UL*2+0))
125 #define REG_PM_DUMMY_RT51_STATUS ((PM_REG_BASE + 0x39UL*2+1))
126 #define REG_PM_CHIP_CFG_OVERWRITE ((PM_REG_BASE + 0x1FUL*2+0))
129 #define REG_PM_CPU_SW_RST ((PM_REG_BASE + 0x29UL*2+1))
/utopia/UTPA2-700.0.x/modules/pm/hal/k6lite/pm/
H A DregPM.h119 #define PM_REG_BASE (0x0700UL*2) macro
121 #define REG_PM_DUMMY_ACTIVE_STANDBY ((PM_REG_BASE + 0x3AUL*2+0))
122 #define REG_PM_DUMMY_POWERON_MODE ((PM_REG_BASE + 0x37UL*2+1))
123 #define REG_PM_DUMMY_WAKEUP_SOURCE ((PM_REG_BASE + 0x34UL*2+1))
124 #define REG_PM_DUMMY_WAKEUP_KEY ((PM_REG_BASE + 0x36UL*2+0))
125 #define REG_PM_DUMMY_RT51_STATUS ((PM_REG_BASE + 0x39UL*2+1))
126 #define REG_PM_CHIP_CFG_OVERWRITE ((PM_REG_BASE + 0x1FUL*2+0))
129 #define REG_PM_CPU_SW_RST ((PM_REG_BASE + 0x29UL*2+1))
/utopia/UTPA2-700.0.x/modules/pm/hal/curry/pm/
H A DregPM.h119 #define PM_REG_BASE (0x0700UL*2) macro
121 #define REG_PM_DUMMY_ACTIVE_STANDBY ((PM_REG_BASE + 0x3AUL*2+0))
122 #define REG_PM_DUMMY_POWERON_MODE ((PM_REG_BASE + 0x37UL*2+1))
123 #define REG_PM_DUMMY_WAKEUP_SOURCE ((PM_REG_BASE + 0x34UL*2+1))
124 #define REG_PM_DUMMY_WAKEUP_KEY ((PM_REG_BASE + 0x36UL*2+0))
125 #define REG_PM_CHIP_CFG_OVERWRITE ((PM_REG_BASE + 0x1FUL*2+0))
128 #define REG_PM_CPU_SW_RST ((PM_REG_BASE + 0x29UL*2+1))
/utopia/UTPA2-700.0.x/modules/miu/hal/maldives/miu/
H A DregMIU.h119 #define PM_REG_BASE (0x1E00) macro
126 #define PM_CHIP_REVISION (PM_REG_BASE+0x03) // 0x1E03
/utopia/UTPA2-700.0.x/modules/miu/hal/messi/miu/
H A DregMIU.h100 #define PM_REG_BASE (0x1E00UL) macro
107 #define PM_CHIP_REVISION (PM_REG_BASE + 0x03) //0x001E03
/utopia/UTPA2-700.0.x/modules/ir_tx/hal/k6lite/ir_tx/
H A Dreg_IR_TX.h20 #define PM_REG_BASE (0x0E00UL) macro
24 #define PM_SET_REG(x) (PM_REG_BASE+(x))
/utopia/UTPA2-700.0.x/modules/miu/hal/mooney/miu/
H A DregMIU.h100 #define PM_REG_BASE (0x1E00UL) macro
107 #define PM_CHIP_REVISION (PM_REG_BASE + 0x03) //0x001E03
/utopia/UTPA2-700.0.x/modules/miu/hal/mainz/miu/
H A DregMIU.h100 #define PM_REG_BASE (0x1E00UL) macro
107 #define PM_CHIP_REVISION (PM_REG_BASE + 0x03) //0x001E03
/utopia/UTPA2-700.0.x/modules/miu/hal/manhattan/miu/
H A DregMIU.h121 #define PM_REG_BASE (0x1E00UL) macro
131 #define PM_CHIP_REVISION (PM_REG_BASE+0x03) // 0x1E03
/utopia/UTPA2-700.0.x/modules/miu/hal/curry/miu/
H A DregMIU.h119 #define PM_REG_BASE (0x1E00UL) macro
126 #define PM_CHIP_REVISION (PM_REG_BASE+0x03) // 0x1E03
/utopia/UTPA2-700.0.x/modules/miu/hal/kano/miu/
H A DregMIU.h119 #define PM_REG_BASE (0x1E00UL) macro
126 #define PM_CHIP_REVISION (PM_REG_BASE+0x03) // 0x1E03
/utopia/UTPA2-700.0.x/modules/miu/hal/M7821/miu/
H A DregMIU.h121 #define PM_REG_BASE (0x1E00UL) macro
134 #define PM_CHIP_REVISION (PM_REG_BASE+0x03) // 0x1E03
/utopia/UTPA2-700.0.x/modules/miu/hal/maserati/miu/
H A DregMIU.h121 #define PM_REG_BASE (0x1E00UL) macro
134 #define PM_CHIP_REVISION (PM_REG_BASE+0x03) // 0x1E03

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