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Searched refs:OTV_SW_RESET (Results 1 – 8 of 8) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dmx/hal/curry/otv/
H A DhalOTV.c190 …VEng][0].OTV_HW_CTRL0, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET)); in HAL_OTV_Init()
191 …VEng][0].OTV_HW_CTRL0, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET)); in HAL_OTV_Init()
203 …VEng][0].OTV_HW_CTRL0, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET));
H A DregOTV.h240 #define OTV_SW_RESET 0x0001 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/otv/
H A DhalOTV.c198 …VEng][0].OTV_HW_CTRL0, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET)); in HAL_OTV_Init()
199 …VEng][0].OTV_HW_CTRL0, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET)); in HAL_OTV_Init()
211 …VEng][0].OTV_HW_CTRL0, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET));
H A DregOTV.h240 #define OTV_SW_RESET 0x0001 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/k6/otv/
H A DhalOTV.c198 …VEng][0].OTV_HW_CTRL0, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET)); in HAL_OTV_Init()
199 …VEng][0].OTV_HW_CTRL0, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET)); in HAL_OTV_Init()
211 …VEng][0].OTV_HW_CTRL0, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET));
H A DregOTV.h240 #define OTV_SW_RESET 0x0001 macro
/utopia/UTPA2-700.0.x/modules/dmx/hal/kano/otv/
H A DhalOTV.c198 …VEng][0].OTV_HW_CTRL0, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET)); in HAL_OTV_Init()
199 …VEng][0].OTV_HW_CTRL0, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET)); in HAL_OTV_Init()
211 …VEng][0].OTV_HW_CTRL0, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET));
H A DregOTV.h240 #define OTV_SW_RESET 0x0001 macro