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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regOTV.h 98 // Description: OTV Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _OTV_REG_H_ 103 #define _OTV_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 137 //-------------------------------------------------------------------------------------------------- 138 // Compliation Option 139 //-------------------------------------------------------------------------------------------------- 140 141 //------------------------------------------------------------------------------------------------- 142 // Harware Capability 143 //------------------------------------------------------------------------------------------------- 144 145 //------------------------------------------------------------------------------------------------- 146 // Type and Structure 147 //------------------------------------------------------------------------------------------------- 148 149 // Software 150 151 #define OTV_BANK0_REG_CTRL_BASE (0x45000) //0x228<<9 //bank 0x1228 152 #define OTV_BANK1_REG_CTRL_BASE (0xC6400) //0x632<<9 //bank 0x1632 153 154 #define OTV0_REG_CTRL_BASE OTV_BANK0_REG_CTRL_BASE 155 #define OTV1_REG_CTRL_BASE (OTV_BANK0_REG_CTRL_BASE+0x100) 156 #define OTV2_REG_CTRL_BASE OTV_BANK1_REG_CTRL_BASE 157 #define OTV3_REG_CTRL_BASE (OTV_BANK1_REG_CTRL_BASE+0x100) 158 159 #define OTV0_PIDFLT_BASE (OTV0_REG_CTRL_BASE+0x2C) 160 #define OTV1_PIDFLT_BASE (OTV1_REG_CTRL_BASE+0x2C) 161 #define OTV2_PIDFLT_BASE (OTV2_REG_CTRL_BASE+0x2C) 162 #define OTV3_PIDFLT_BASE (OTV3_REG_CTRL_BASE+0x2C) 163 164 #define OTV0_EVENT_MASK_BASE (OTV0_REG_CTRL_BASE+0xC0) 165 #define OTV1_EVENT_MASK_BASE (OTV1_REG_CTRL_BASE+0xC0) 166 #define OTV2_EVENT_MASK_BASE (OTV2_REG_CTRL_BASE+0xC0) 167 #define OTV3_EVENT_MASK_BASE (OTV3_REG_CTRL_BASE+0xC0) 168 169 //#define OTV0_BANK0_PIDFLT_BASE (OTV0_BANK0_REG_CTRL_BASE+0x80) 170 //#define OTV0_BANK1_EVENT_MASK_BASE (OTV0_BANK1_REG_CTRL_BASE+0x180) 171 //#define OTV0_BANK1_PAYLOAD_MASK_BASE (OTV0_BANK1_REG_CTRL_BASE+0x100) 172 173 //#define OTV1_BANK0_REG_CTRL_BASE (0x23A00) 174 //#define OTV1_BANK1_REG_CTRL_BASE (0x23C00) 175 176 //#define OTV1_BANK0_PIDFLT_BASE (OTV1_BANK0_REG_CTRL_BASE+0x80) 177 //#define OTV1_BANK1_EVENT_MASK_BASE (OTV1_BANK1_REG_CTRL_BASE+0x180) 178 //#define OTV1_BANK1_PAYLOAD_MASK_BASE (OTV1_BANK1_REG_CTRL_BASE+0x100) 179 180 // Payload/Event Mask flag 181 #define OTV_EVENT_MASK 0xffffffff 182 #define OTV_EVENT_AFE 0x00000001 // Adaptation Field Extension flag 183 #define OTV_EVENT_TPD 0x00000002 // Transport Private Data flag 184 #define OTV_EVENT_SP 0x00000004 // Splicing Point flag 185 #define OTV_EVENT_OPCR 0x00000008 // OPCR flag 186 #define OTV_EVENT_PCR 0x00000010 // PCR flag 187 #define OTV_EVENT_ESPI 0x00000020 // Elementary Stream Priority Indicator 188 #define OTV_EVENT_RAI 0x00000040 // Random Access Indicator 189 #define OTV_EVENT_DI 0x00000080 // Discontinuity Indicator 190 #define OTV_EVENT_CESOS 0x00000100 // Change of Elementary Stream to Odd Scrambled 191 #define OTV_EVENT_CESES 0x00000200 // Change of Elementary Stream to Even Scrambled 192 #define OTV_EVENT_CESNS 0x00000400 // Change of Elementary Stream to Not Scrambled 193 #define OTV_EVENT_PUSI 0x00000800 // Payload Unit Start Indicator 194 #define OTV_EVENT_FPR 0x00001000 // First Packet Recorded 195 196 197 typedef struct _OTV_REG32 198 { 199 volatile MS_U16 L; 200 volatile MS_U16 empty_L; 201 volatile MS_U16 H; 202 volatile MS_U16 empty_H; 203 } OTV_REG32; 204 205 typedef struct _OTV_REG16 206 { 207 volatile MS_U16 data; 208 volatile MS_U16 _resv; 209 } OTV_REG16; 210 211 //typedef OTV_REG16 REG_PidFlt; //bruce 212 213 typedef struct _REG_OTV 214 { 215 //---------------------------------------------- 216 // 0xBF245000 MIPS direct access 217 //---------------------------------------------- 218 OTV_REG32 OTV_PktTimer; // 0xbf245000 0x00 219 OTV_REG32 OTV_PktNum; // 0xbf245008 0x02 220 OTV_REG16 _bf245010; // 0xbf245010 0x04 221 222 OTV_REG16 OTV_PktSize2; // 0xbf245014 0x05 223 #define OTV_PKT_SIZE_MASK 0xFF00 224 #define OTV_PKT_SIZE_188 0xBB 225 #define OTV_PKT_SHIFT 8 226 227 OTV_REG16 OTV_EventLogCtrlStatus; // 0xbf245018 0x06 228 #define OTV_EVENT_FIFO_NUM_MASK 0x001F 229 #define OTV_EVENT_FIFO_FULL 0X0020 230 #define OTV_EVENT_FIFO_EMPTY 0x0040 231 #define OTV_EVENT_FIFO_RDLV_MASK 0x0300 232 #define OTV_EVENT_FIFO_RDLV_SHIFT 8 233 #define OTV_EVENT_FIFO_WTLV_MASK 0x0C00 234 #define OTV_EVENT_FIFO_WTLV_SHIFT 10 235 #define OTV_EVENT_FIFO_RD_OVF 0x1000 236 #define OTV_EVENT_FIFO_WT_OVF 0x2000 237 238 OTV_REG16 OTV_PktChkSize2; // 0xbf24501c 0x07 239 OTV_REG16 OTV_HW_CTRL0; // 0xbf245020 0x08 240 #define OTV_SW_RESET 0x0001 241 #define OTV_TEI_SKIP_PKT 0x0040 242 #define OTV_CLR_EVENT_OVERFLOW 0x0200 243 #define OTV_MASK_MD 0x0800 244 #define OTV_REC_EFRAME_EN 0x1000 245 #define OTV_RM_PIPE 0x4000 // OTV RASP auto flush 246 247 OTV_REG16 OTV_HW_CTRL1; // 0xbf245024 0x09 248 #define OTV_ALT_TS_SIZE 0x0080 249 #define OTV_TICK_TIME_MASK 0x6000 250 #define OTV_EFRAME_RD 0x8000 // read eframe fifo 251 252 OTV_REG16 OTV_HW_CTRL2; // 0xbf245028 0x0a 253 #define OTV_INT_TIMER_EN 0x0001 254 #define OTV_INT_EVENT_EN 0x0002 255 #define OTV_INT_TIME_WATER_MASK 0x000C 256 #define OTV_INT_TIME_WATER_SHIFT 2 257 #define OTV_INT_EVENT_WATER_MASK 0x01F0 258 #define OTV_INT_EVENT_WATER_SHIFT 4 259 #define OTV_PKT_NUM_TIMER_SEL 0x2000 // The recording packet timestamp: default 0:replace with pkt timer, 1: pkt number 260 #define OTV_TIMESTAMP_OTV_EN 0x4000 // The recording packet timestamp sel: default 0: no OTV timestamp replace, with PVR timestamp replace; 1: with OTV timestamp replace 261 #define OTV_TIMESTAMP_PVR_TO_OTV_EN 0x8000 // The OTV packet timestamp source select : default 0: match OTV local timstamp 1: match PVR timstamp 262 263 OTV_REG16 OTV_Pidflt_0; // 0xbf24502c 0x0b 264 OTV_REG16 OTV_Pidflt_1; // 0xbf245030 0x0c 265 OTV_REG16 OTV_Pidflt_2; // 0xbf245034 0x0d 266 OTV_REG16 OTV_Pidflt_3; // 0xbf245038 0x0e 267 268 OTV_REG16 OTV_HW_CTRL3; // 0xbf24503c 0x0f 269 #define OTV_PKT_SW_RST 0x0001 // If this bit set to 1, pkt_num & pkt timestamp will be reset 270 #define OTV_PKT_NUM_SRC_SEL 0x0002 // 0:count by OTV pid hit, pkt_num index start from 0,1,2,...etc 271 // 1:count by pkt dmx hit, pkt_num index start from 1,2,3,...etc 272 273 #define OTV_PKT_NUM_TIMER_LOCK 0x0004 // pkt num/timer will be locked for reading if this bit is set to 1 274 #define OTV_FIRST_PKT_TIMER_BASE_EN 0x0008 // If this bit set to 1, timer will be (orginal timer - first pkt timer) 275 #define OTV_EVENT_FLT_RST 0x0010 // If this bit set to 1, OTV event flt will reset (The bit only work after Kirin U02, including U02) 276 277 OTV_REG32 OTV_EventDescriptor; // 0xbf201d40 0x10 278 OTV_REG32 OTV_EventPktNum; // 0xbf201d48 0x12 279 OTV_REG32 OTV_EventPktTimer; // 0xbf201d50 0x14 280 OTV_REG32 OTV_EventPktPCR; // 0xbf201d58 0x16 281 OTV_REG16 OTV_EventPktPID; // 0xbf201d60 0x18 282 283 OTV_REG16 OTV_PushCnt; // 0xbf201d64 0x19 284 #define OTV_PUSH_CNT_MASK 0xFF00 // OTV auto flush push counter 285 286 OTV_REG32 OTV_Debug; // 0xbf245068 0x1a 287 288 OTV_REG16 OTV_INT_Flag; // 0xbf201d70 0x1c 289 #define OTV_INT_FLAG_MASK 0x00FF 290 #define OTV_INT_FROM_OTV0_TIMER 0x0001 // write 0 to clear(only valid at bank OTV0) 291 #define OTV_INT_FROM_OTV0_EVENT 0x0002 // write 0 to clear(only valid at bank OTV0) 292 #define OTV_INT_FROM_OTV1_TIMER 0x0004 // write 0 to clear(only valid at bank OTV0) 293 #define OTV_INT_FROM_OTV1_EVENT 0x0008 // write 0 to clear(only valid at bank OTV0) 294 #define OTV_INT_FROM_OTV2_TIMER 0x0010 // write 0 to clear(only valid at bank OTV0) 295 #define OTV_INT_FROM_OTV2_EVENT 0x0020 // write 0 to clear(only valid at bank OTV0) 296 #define OTV_INT_FROM_OTV3_TIMER 0x0040 // write 0 to clear(only valid at bank OTV0) 297 #define OTV_INT_FROM_OTV3_EVENT 0x0080 // write 0 to clear(only valid at bank OTV0) 298 299 OTV_REG16 OTV_HW_CTRL4; // 0xbf245074 0x1d 300 OTV_REG16 OTV_HW_CTRL5; // 0xbf245078 0x1e 301 OTV_REG16 OTV_HW_CTRL6; // 0xbf24507c 0x1f 302 303 OTV_REG32 OTV_Pid_PayLoadMask_0; // 0xbf245080 0x20 304 OTV_REG32 OTV_Pid_PayLoadMask_1; // 0xbf245088 0x22 305 OTV_REG32 OTV_Pid_PayLoadMask_2; // 0xbf245090 0x24 306 OTV_REG32 OTV_Pid_PayLoadMask_3; // 0xbf245098 0x26 307 OTV_REG32 OTV_Pid_PayLoadMask_4; // 0xbf2450a0 0x28 308 309 OTV_REG16 _bf2450a8_bf2450bc[0x30-0x2a]; // 0xbf2450a8-bf2450bc 0x2a-0x2f 310 311 OTV_REG32 OTV_Pid_EventMask_0; // 0xbf2450c0 0x30 312 OTV_REG32 OTV_Pid_EventMask_1; // 0xbf2450c8 0x32 313 OTV_REG32 OTV_Pid_EventMask_2; // 0xbf2450d0 0x34 314 OTV_REG32 OTV_Pid_EventMask_3; // 0xbf2450d8 0x36 315 OTV_REG32 OTV_Pid_EventMask_4; // 0xbf2450e0 0x38 316 317 } REG_OTV; 318 319 #endif // _OTV_REG_H_ 320