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Searched refs:MIU1_REG_RQ0_MASK (Results 1 – 25 of 126) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/vpu/
H A DhalVPU.c129 #define _MaskMiu1Req_VPU_D_RW( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
130 #define _MaskMiu1Req_VPU_Q_RW( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
131 #define _MaskMiu1Req_VPU_I_R( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
H A DregVPU.h354 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/vpu/
H A DhalVPU.c129 #define _MaskMiu1Req_VPU_D_RW( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
130 #define _MaskMiu1Req_VPU_Q_RW( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
131 #define _MaskMiu1Req_VPU_I_R( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
H A DregVPU.h354 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/vpu/
H A DhalVPU.c129 #define _MaskMiu1Req_VPU_D_RW( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
130 #define _MaskMiu1Req_VPU_Q_RW( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
131 #define _MaskMiu1Req_VPU_I_R( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/vpu/
H A DhalVPU.c129 #define _MaskMiu1Req_VPU_D_RW( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
130 #define _MaskMiu1Req_VPU_Q_RW( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
131 #define _MaskMiu1Req_VPU_I_R( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/vpu/
H A DhalVPU.c129 #define _MaskMiu1Req_VPU_D_RW( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
130 #define _MaskMiu1Req_VPU_Q_RW( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
131 #define _MaskMiu1Req_VPU_I_R( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/vpu/
H A DhalVPU.c129 #define _MaskMiu1Req_VPU_D_RW( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
130 #define _MaskMiu1Req_VPU_Q_RW( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
131 #define _MaskMiu1Req_VPU_I_R( m ) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DhalVPU_EX.c238 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5))
239 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5))
240 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
253 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5))
254 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5))
255 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DhalVPU_EX.c238 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5))
239 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5))
240 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
253 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5))
254 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5))
255 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/
H A DhalVPU_EX.c262 …pu,m) (vpu==VPU_EVDR2)?({_VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5));}):({_VPU_WriteRegBit(MIU1…
263 …pu,m) (vpu==VPU_EVDR2)?({_VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(5));}):({_VPU_WriteRegBit(MIU1…
264 …u,m) (vpu==VPU_EVDR2)?({_VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(3));}):({_VPU_WriteRegBit(MIU1…
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/vpu_ex/
H A DhalVPU_EX.c218 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
219 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
220 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
H A DregVPU_EX.h361 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/vpu_ex/
H A DhalVPU_EX.c218 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
219 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
220 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
H A DregVPU_EX.h361 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/vpu_ex/
H A DhalVPU_EX.c218 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
219 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
220 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/vpu_ex/
H A DhalVPU_EX.c218 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
219 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
220 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/vpu_ex/
H A DhalVPU_EX.c218 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
219 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
220 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/vpu_ex/
H A DhalVPU_EX.c218 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
219 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
220 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
H A DregVPU_EX.h361 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/vpu_ex/
H A DhalVPU_EX.c218 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
219 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
220 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/vpu_ex/
H A DhalVPU_EX.c218 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
219 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
220 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
H A DregVPU_EX.h361 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/vpu_ex/
H A DhalVPU_EX.c239 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
240 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
241 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/vpu_ex/
H A DhalVPU_EX.c239 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
240 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
241 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))

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