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Searched refs:MIU1_BASEADDR (Results 1 – 25 of 37) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/vdec_v1/drv/mvd/
H A Dmvd_cc.c164 #define MIU1_BASEADDR stMemCfg.u32Miu1BaseAddr macro
194 if((u32StartAddress&MIU1_BASEADDR) == MIU1_BASEADDR) in MDrv_CC_CM_SetMVDRB_HWAddr()
208 CCMVD_RINGBUFFER_START_ADR[u8CC608] = u32StartAddress | MIU1_BASEADDR; in MDrv_CC_CM_SetMVDRB_HWAddr()
226 u32MVDCC_Temp1 = u32StartAddress - MIU1_BASEADDR; in MDrv_CC_CM_SetMVDRB_HWAddr()
364 return (u32MVDCC_Temp1|MIU1_BASEADDR); in MDrv_CC_CM_GetMVDRB_HWAddr()
424 u32MVDCC_Temp1 = u32ReadAddress - MIU1_BASEADDR ; in MDrv_CC_CM_SetMVDRB_SWAddr()
440 #define __Offset2PA(x) ((MVD_ON_MIU1)?((x)|MIU1_BASEADDR):(x))
508 … u32MVDCC_Temp1 = CCMVD_RINGBUFFER_START_ADR[u8CC608] & (MIU1_BASEADDR - 1); // to Phy address in MDrv_CC_PM_SetMVDRB_ReadAddr()
/utopia/UTPA2-700.0.x/modules/vdec_v2/drv/mvd_ex/
H A Dmvd_cc_EX.c168 #define MIU1_BASEADDR HAL_MVD_GetMiu1BaseAdd() macro
343 if((u32StartAddress&MIU1_BASEADDR) == MIU1_BASEADDR) in MDrv_CC_CM_SetMVDRB_HWAddr()
357 CCMVD_RINGBUFFER_START_ADR[u8CC608] = u32StartAddress | MIU1_BASEADDR; in MDrv_CC_CM_SetMVDRB_HWAddr()
375 u32MVDCC_Temp1 = u32StartAddress - MIU1_BASEADDR ; in MDrv_CC_CM_SetMVDRB_HWAddr()
571 return (u32MVDCC_Temp1|MIU1_BASEADDR); in MDrv_CC_CM_GetMVDRB_HWAddr()
684 u32MVDCC_Temp1 = u32ReadAddress - MIU1_BASEADDR; in MDrv_CC_CM_SetMVDRB_SWAddr()
703 #define __Offset2PA(x) ((MVD_ON_MIU1)?((x)|MIU1_BASEADDR):(x))
1117 … u32MVDCC_Temp1 = CCMVD_RINGBUFFER_START_ADR[u8CC608] & (MIU1_BASEADDR - 1); // to Phy address in MDrv_CC_PM_SetMVDRB_ReadAddr()
/utopia/UTPA2-700.0.x/modules/vdec_v3/drv/mvd_v3/
H A Dmvd_cc_EX.c172 #define MIU1_BASEADDR HAL_MVD_GetMiu1BaseAdd() macro
347 if((u32StartAddress&MIU1_BASEADDR) == MIU1_BASEADDR) in MDrv_CC_CM_SetMVDRB_HWAddr()
361 CCMVD_RINGBUFFER_START_ADR[u8CC608] = u32StartAddress | MIU1_BASEADDR; in MDrv_CC_CM_SetMVDRB_HWAddr()
379 u32MVDCC_Temp1 = u32StartAddress - MIU1_BASEADDR ; in MDrv_CC_CM_SetMVDRB_HWAddr()
575 return (u32MVDCC_Temp1|MIU1_BASEADDR); in MDrv_CC_CM_GetMVDRB_HWAddr()
688 u32MVDCC_Temp1 = u32ReadAddress - MIU1_BASEADDR; in MDrv_CC_CM_SetMVDRB_SWAddr()
707 #define __Offset2PA(x) ((MVD_ON_MIU1)?((x)|MIU1_BASEADDR):(x))
1121 … u32MVDCC_Temp1 = CCMVD_RINGBUFFER_START_ADR[u8CC608] & (MIU1_BASEADDR - 1); // to Phy address in MDrv_CC_PM_SetMVDRB_ReadAddr()
/utopia/UTPA2-700.0.x/modules/vdec_lite/drv/mvd_lite/
H A Dmvd_cc_EX.c172 #define MIU1_BASEADDR HAL_MVD_GetMiu1BaseAdd() macro
347 if((u32StartAddress&MIU1_BASEADDR) == MIU1_BASEADDR) in MDrv_CC_CM_SetMVDRB_HWAddr()
361 CCMVD_RINGBUFFER_START_ADR[u8CC608] = u32StartAddress | MIU1_BASEADDR; in MDrv_CC_CM_SetMVDRB_HWAddr()
379 u32MVDCC_Temp1 = u32StartAddress - MIU1_BASEADDR ; in MDrv_CC_CM_SetMVDRB_HWAddr()
575 return (u32MVDCC_Temp1|MIU1_BASEADDR); in MDrv_CC_CM_GetMVDRB_HWAddr()
688 u32MVDCC_Temp1 = u32ReadAddress - MIU1_BASEADDR; in MDrv_CC_CM_SetMVDRB_SWAddr()
707 #define __Offset2PA(x) ((MVD_ON_MIU1)?((x)|MIU1_BASEADDR):(x))
1121 … u32MVDCC_Temp1 = CCMVD_RINGBUFFER_START_ADR[u8CC608] & (MIU1_BASEADDR - 1); // to Phy address in MDrv_CC_PM_SetMVDRB_ReadAddr()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/mvd/
H A DhalMVD.c162 #define MIU1_BASEADDR stMemCfg.u32Miu1BaseAddr macro
163 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
378 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
422 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
666 u32fwPA = u32fwAddr + MIU1_BASEADDR; in HAL_MVD_LoadCode()
672 …VD_LoadCode u32fwAddr=%lx, miuSel=%x, miu1Base=%lx\n",u32fwAddr,stMemCfg.bFWMiuSel,MIU1_BASEADDR)); in HAL_MVD_LoadCode()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/mvd/
H A DhalMVD.c162 #define MIU1_BASEADDR stMemCfg.u32Miu1BaseAddr macro
163 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
378 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
422 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
666 u32fwPA = u32fwAddr + MIU1_BASEADDR; in HAL_MVD_LoadCode()
672 …VD_LoadCode u32fwAddr=%lx, miuSel=%x, miu1Base=%lx\n",u32fwAddr,stMemCfg.bFWMiuSel,MIU1_BASEADDR)); in HAL_MVD_LoadCode()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/mvd/
H A DhalMVD.c162 #define MIU1_BASEADDR stMemCfg.u32Miu1BaseAddr macro
163 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
378 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
422 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
666 u32fwPA = u32fwAddr + MIU1_BASEADDR; in HAL_MVD_LoadCode()
672 …VD_LoadCode u32fwAddr=%lx, miuSel=%x, miu1Base=%lx\n",u32fwAddr,stMemCfg.bFWMiuSel,MIU1_BASEADDR)); in HAL_MVD_LoadCode()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/mainz/mvd/
H A DhalMVD.c162 #define MIU1_BASEADDR stMemCfg.u32Miu1BaseAddr macro
163 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
378 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
422 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
666 u32fwPA = u32fwAddr + MIU1_BASEADDR; in HAL_MVD_LoadCode()
672 …VD_LoadCode u32fwAddr=%lx, miuSel=%x, miu1Base=%lx\n",u32fwAddr,stMemCfg.bFWMiuSel,MIU1_BASEADDR)); in HAL_MVD_LoadCode()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/mvd/
H A DhalMVD.c162 #define MIU1_BASEADDR stMemCfg.u32Miu1BaseAddr macro
163 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
378 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
422 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
666 u32fwPA = u32fwAddr + MIU1_BASEADDR; in HAL_MVD_LoadCode()
672 …VD_LoadCode u32fwAddr=%lx, miuSel=%x, miu1Base=%lx\n",u32fwAddr,stMemCfg.bFWMiuSel,MIU1_BASEADDR)); in HAL_MVD_LoadCode()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/messi/mvd/
H A DhalMVD.c162 #define MIU1_BASEADDR stMemCfg.u32Miu1BaseAddr macro
163 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
378 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
422 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
666 u32fwPA = u32fwAddr + MIU1_BASEADDR; in HAL_MVD_LoadCode()
672 …VD_LoadCode u32fwAddr=%lx, miuSel=%x, miu1Base=%lx\n",u32fwAddr,stMemCfg.bFWMiuSel,MIU1_BASEADDR)); in HAL_MVD_LoadCode()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/mvd/
H A DhalMVD.c162 #define MIU1_BASEADDR stMemCfg.u32Miu1BaseAddr macro
163 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
378 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
422 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
666 u32fwPA = u32fwAddr + MIU1_BASEADDR; in HAL_MVD_LoadCode()
672 …VD_LoadCode u32fwAddr=%lx, miuSel=%x, miu1Base=%lx\n",u32fwAddr,stMemCfg.bFWMiuSel,MIU1_BASEADDR)); in HAL_MVD_LoadCode()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/mvd/
H A DhalMVD.c162 #define MIU1_BASEADDR stMemCfg.u32Miu1BaseAddr macro
163 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
378 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
422 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
666 u32fwPA = u32fwAddr + MIU1_BASEADDR; in HAL_MVD_LoadCode()
672 …VD_LoadCode u32fwAddr=%lx, miuSel=%x, miu1Base=%lx\n",u32fwAddr,stMemCfg.bFWMiuSel,MIU1_BASEADDR)); in HAL_MVD_LoadCode()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/mvd_ex/
H A DhalMVD_EX.c127 #define MIU1_BASEADDR pMVDHalContext->stMiuCfg.u32Miu1BaseAddr macro
128 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
724 return MIU1_BASEADDR; in HAL_MVD_GetMiu1BaseAdd()
834 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
842 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
889 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
896 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
970 u32Address += MIU1_BASEADDR; in HAL_MVD_Memset4Byte()
5309 u32start += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
5310 u32end += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/mvd_ex/
H A DhalMVD_EX.c127 #define MIU1_BASEADDR pMVDHalContext->stMiuCfg.u32Miu1BaseAddr macro
128 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
690 return MIU1_BASEADDR; in HAL_MVD_GetMiu1BaseAdd()
800 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
808 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
855 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
862 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
936 u32Address += MIU1_BASEADDR; in HAL_MVD_Memset4Byte()
5218 u32start += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
5219 u32end += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/mvd_ex/
H A DhalMVD_EX.c127 #define MIU1_BASEADDR pMVDHalContext->stMiuCfg.u32Miu1BaseAddr macro
128 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
724 return MIU1_BASEADDR; in HAL_MVD_GetMiu1BaseAdd()
834 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
842 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
889 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
896 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
970 u32Address += MIU1_BASEADDR; in HAL_MVD_Memset4Byte()
5309 u32start += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
5310 u32end += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/mvd_ex/
H A DhalMVD_EX.c127 #define MIU1_BASEADDR pMVDHalContext->stMiuCfg.u32Miu1BaseAddr macro
128 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
690 return MIU1_BASEADDR; in HAL_MVD_GetMiu1BaseAdd()
800 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
808 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
855 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
862 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
936 u32Address += MIU1_BASEADDR; in HAL_MVD_Memset4Byte()
5218 u32start += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
5219 u32end += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/mvd_ex/
H A DhalMVD_EX.c127 #define MIU1_BASEADDR pMVDHalContext->stMiuCfg.u32Miu1BaseAddr macro
128 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
690 return MIU1_BASEADDR; in HAL_MVD_GetMiu1BaseAdd()
800 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
808 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
855 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
862 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
936 u32Address += MIU1_BASEADDR; in HAL_MVD_Memset4Byte()
5218 u32start += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
5219 u32end += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/mvd_ex/
H A DhalMVD_EX.c127 #define MIU1_BASEADDR pMVDHalContext->stMiuCfg.u32Miu1BaseAddr macro
128 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
690 return MIU1_BASEADDR; in HAL_MVD_GetMiu1BaseAdd()
800 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
808 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
855 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
862 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
936 u32Address += MIU1_BASEADDR; in HAL_MVD_Memset4Byte()
5218 u32start += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
5219 u32end += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/mvd_ex/
H A DhalMVD_EX.c127 #define MIU1_BASEADDR pMVDHalContext->stMiuCfg.u32Miu1BaseAddr macro
128 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
690 return MIU1_BASEADDR; in HAL_MVD_GetMiu1BaseAdd()
800 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
808 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
855 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
862 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
936 u32Address += MIU1_BASEADDR; in HAL_MVD_Memset4Byte()
5218 u32start += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
5219 u32end += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/mvd_ex/
H A DhalMVD_EX.c127 #define MIU1_BASEADDR pMVDHalContext->stMiuCfg.u32Miu1BaseAddr macro
128 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
690 return MIU1_BASEADDR; in HAL_MVD_GetMiu1BaseAdd()
800 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
808 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
855 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
862 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
936 u32Address += MIU1_BASEADDR; in HAL_MVD_Memset4Byte()
5218 u32start += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
5219 u32end += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/mvd_ex/
H A DhalMVD_EX.c127 #define MIU1_BASEADDR pMVDHalContext->stMiuCfg.u32Miu1BaseAddr macro
128 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
690 return MIU1_BASEADDR; in HAL_MVD_GetMiu1BaseAdd()
800 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
808 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
855 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
862 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
936 u32Address += MIU1_BASEADDR; in HAL_MVD_Memset4Byte()
5218 u32start += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
5219 u32end += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/mvd_ex/
H A DhalMVD_EX.c127 #define MIU1_BASEADDR pMVDHalContext->stMiuCfg.u32Miu1BaseAddr macro
128 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
690 return MIU1_BASEADDR; in HAL_MVD_GetMiu1BaseAdd()
800 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
808 u32Address += MIU1_BASEADDR; in HAL_MVD_MemRead4Byte()
855 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
862 u32Address += MIU1_BASEADDR; in HAL_MVD_MemWrite4Byte()
936 u32Address += MIU1_BASEADDR; in HAL_MVD_Memset4Byte()
5218 u32start += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
5219 u32end += MIU1_BASEADDR; in HAL_MVD_SetSLQStartEnd()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/mvd_v3/
H A DhalMVD_EX.c143 #define MIU1_BASEADDR pMVDHalContext->stMiuCfg.u32Miu1BaseAddr macro
144 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
801 return MIU1_BASEADDR;
808 return MIU1_BASEADDR; in HAL_MVD_GetMiu1BaseAdd()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/mvd_v3/
H A DhalMVD_EX.c143 #define MIU1_BASEADDR pMVDHalContext->stMiuCfg.u32Miu1BaseAddr macro
144 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
801 return MIU1_BASEADDR;
808 return MIU1_BASEADDR; in HAL_MVD_GetMiu1BaseAdd()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/mvd_v3/
H A DhalMVD_EX.c159 #define MIU1_BASEADDR pMVDHalContext->stMiuCfg.u32Miu1BaseAddr macro
160 #define _PA2Offset(x) (((x)>=MIU1_BASEADDR)?(x-MIU1_BASEADDR):(x))
838 return MIU1_BASEADDR;
845 return MIU1_BASEADDR; in HAL_MVD_GetMiu1BaseAdd()

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