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Searched refs:MIU0_REG_HVD_BASE (Results 1 – 25 of 62) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/vpu_v3/
H A DregVPU_EX.h386 #define MIU0_REG_HVD_BASE (0x1200) macro
392 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
393 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
394 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
395 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
406 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
407 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
408 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
409 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
410 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A DregVPU_EX.h394 #define MIU0_REG_HVD_BASE (0x1200) macro
403 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
404 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
405 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
406 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
425 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
426 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
427 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
428 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
429 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A DregVPU_EX.h402 #define MIU0_REG_HVD_BASE (0x1200) macro
411 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
412 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
413 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
414 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
433 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
434 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
435 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
436 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
437 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DregVPU_EX.h402 #define MIU0_REG_HVD_BASE (0x1200) macro
411 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
412 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
413 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
414 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
433 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
434 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
435 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
436 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
437 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DregVPU_EX.h402 #define MIU0_REG_HVD_BASE (0x1200) macro
411 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
412 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
413 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
414 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
433 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
434 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
435 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
436 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
437 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/vpu_v3/
H A DregVPU_EX.h422 #define MIU0_REG_HVD_BASE (0x1200) macro
428 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
429 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
430 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
431 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
442 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
443 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
444 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
445 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
446 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DregVPU_EX.h422 #define MIU0_REG_HVD_BASE (0x1200) macro
431 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
432 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
433 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
434 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
453 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
454 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
455 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
456 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
457 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/vpu_v3/
H A DregVPU_EX.h422 #define MIU0_REG_HVD_BASE (0x1200) macro
428 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
429 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
430 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
431 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
442 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
443 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
444 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
445 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
446 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DregVPU_EX.h422 #define MIU0_REG_HVD_BASE (0x1200) macro
431 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
432 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
433 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
434 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
453 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
454 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
455 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
456 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
457 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/vpu_v3/
H A DregVPU_EX.h422 #define MIU0_REG_HVD_BASE (0x1200) macro
428 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
429 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
430 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
431 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
442 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
443 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
444 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
445 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
446 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/vpu_lite/
H A DregVPU_EX.h420 #define MIU0_REG_HVD_BASE (0x1200) macro
429 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
430 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
431 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
432 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
451 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
452 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
453 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
454 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
455 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/vpu_v3/
H A DregVPU_EX.h422 #define MIU0_REG_HVD_BASE (0x1200) macro
431 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
432 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
433 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
434 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
454 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
455 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
456 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
457 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
458 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/vpu_v3/
H A DregVPU_EX.h422 #define MIU0_REG_HVD_BASE (0x1200) macro
431 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
432 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
433 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
434 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
454 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
455 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
456 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
457 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
458 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/vpu_v3/
H A DregVPU_EX.h422 #define MIU0_REG_HVD_BASE (0x1200) macro
431 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
432 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
433 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
434 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
454 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
455 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
456 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
457 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
458 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DregHVD_EX.h592 #define MIU0_REG_HVD_BASE (0x1200) macro
602 #define MIU0_CLIENT_SELECT_GP4 (MIU0_REG_HVD_BASE + (0x007C<<1))
618 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
619 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
620 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
621 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
642 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
643 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
644 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
645 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DregHVD_EX.h593 #define MIU0_REG_HVD_BASE (0x1200) macro
603 #define MIU0_CLIENT_SELECT_GP4 (MIU0_REG_HVD_BASE + (0x007C<<1))
619 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
620 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
621 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
622 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
643 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
644 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
645 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
646 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DregHVD_EX.h609 #define MIU0_REG_HVD_BASE (0x1200) macro
616 #define MIU0_CLIENT_SELECT_GP4 (MIU0_REG_HVD_BASE + (0x007C<<1))
622 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
623 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
624 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
625 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
637 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
638 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
639 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
640 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DregHVD_EX.h593 #define MIU0_REG_HVD_BASE (0x1200) macro
603 #define MIU0_CLIENT_SELECT_GP4 (MIU0_REG_HVD_BASE + (0x007C<<1))
619 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
620 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
621 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
622 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
643 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
644 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
645 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
646 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DregHVD_EX.h594 #define MIU0_REG_HVD_BASE (0x1200) macro
604 #define MIU0_CLIENT_SELECT_GP4 (MIU0_REG_HVD_BASE + (0x007C<<1))
620 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
621 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
622 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
623 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
644 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
645 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
646 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
647 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DregHVD_EX.h592 #define MIU0_REG_HVD_BASE (0x1200) macro
602 #define MIU0_CLIENT_SELECT_GP4 (MIU0_REG_HVD_BASE + (0x007C<<1))
618 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
619 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
620 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
621 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
642 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
643 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
644 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
645 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DregHVD_EX.h609 #define MIU0_REG_HVD_BASE (0x1200) macro
616 #define MIU0_CLIENT_SELECT_GP4 (MIU0_REG_HVD_BASE + (0x007C<<1))
622 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
623 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
624 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
625 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
637 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
638 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
639 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
640 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DregHVD_EX.h593 #define MIU0_REG_HVD_BASE (0x1200) macro
603 #define MIU0_CLIENT_SELECT_GP4 (MIU0_REG_HVD_BASE + (0x007C<<1))
619 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
620 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
621 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
622 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
643 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
644 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
645 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
646 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/hvd_v3/
H A DregHVD_EX.h534 #define MIU0_REG_HVD_BASE (0x1200) macro
540 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
541 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
542 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
543 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
554 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
555 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
556 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
557 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
558 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1))
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/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DregHVD_EX.h638 #define MIU0_REG_HVD_BASE (0x1200) macro
648 #define MIU0_CLIENT_SELECT_GP4 (MIU0_REG_HVD_BASE + (0x007C<<1))
662 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
663 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
664 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
665 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
686 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
687 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
688 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
689 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DregHVD_EX.h621 #define MIU0_REG_HVD_BASE (0x1200) macro
631 #define MIU0_CLIENT_SELECT_GP4 (MIU0_REG_HVD_BASE + (0x007C<<1))
646 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1))
647 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1))
648 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1))
649 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1))
668 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1))
669 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1))
670 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1))
671 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1))
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