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Searched refs:HVD_REG_RISC_ISR_MSK (Results 1 – 25 of 68) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/hvd/
H A DhalHVD_sub.c1285 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_Sub_EnableISR()
1289 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_Sub_EnableISR()
2258 _HVD_WriteWordMask( HVD_REG_RISC_MBOX_CLR , 0 , HVD_REG_RISC_ISR_MSK ); in HAL_HVD_Sub_Enable_ISR()
2262 … _HVD_WriteWordMask( HVD_REG_RISC_MBOX_CLR , HVD_REG_RISC_ISR_MSK , HVD_REG_RISC_ISR_MSK ); in HAL_HVD_Sub_Enable_ISR()
2290 if(_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR)& HVD_REG_RISC_ISR_MSK) in HAL_HVD_Sub_IsEnableISR()
H A DhalHVD.c2471 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EnableISR()
2475 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EnableISR()
2503 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR) & HVD_REG_RISC_ISR_MSK) in HAL_HVD_IsEnableISR()
H A DregHVD.h268 #define HVD_REG_RISC_ISR_MSK BIT(6) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maserati/hvd/
H A DhalHVD_sub.c1285 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_Sub_EnableISR()
1289 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_Sub_EnableISR()
2258 _HVD_WriteWordMask( HVD_REG_RISC_MBOX_CLR , 0 , HVD_REG_RISC_ISR_MSK ); in HAL_HVD_Sub_Enable_ISR()
2262 … _HVD_WriteWordMask( HVD_REG_RISC_MBOX_CLR , HVD_REG_RISC_ISR_MSK , HVD_REG_RISC_ISR_MSK ); in HAL_HVD_Sub_Enable_ISR()
2290 if(_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR)& HVD_REG_RISC_ISR_MSK) in HAL_HVD_Sub_IsEnableISR()
H A DhalHVD.c2471 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EnableISR()
2475 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EnableISR()
2503 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR) & HVD_REG_RISC_ISR_MSK) in HAL_HVD_IsEnableISR()
H A DregHVD.h268 #define HVD_REG_RISC_ISR_MSK BIT(6) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/macan/hvd/
H A DhalHVD_sub.c1285 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_Sub_EnableISR()
1289 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_Sub_EnableISR()
2258 _HVD_WriteWordMask( HVD_REG_RISC_MBOX_CLR , 0 , HVD_REG_RISC_ISR_MSK ); in HAL_HVD_Sub_Enable_ISR()
2262 … _HVD_WriteWordMask( HVD_REG_RISC_MBOX_CLR , HVD_REG_RISC_ISR_MSK , HVD_REG_RISC_ISR_MSK ); in HAL_HVD_Sub_Enable_ISR()
2290 if(_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR)& HVD_REG_RISC_ISR_MSK) in HAL_HVD_Sub_IsEnableISR()
H A DhalHVD.c2471 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EnableISR()
2475 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EnableISR()
2503 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR) & HVD_REG_RISC_ISR_MSK) in HAL_HVD_IsEnableISR()
H A DregHVD.h268 #define HVD_REG_RISC_ISR_MSK BIT(6) macro
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/maxim/hvd/
H A DhalHVD_sub.c1285 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_Sub_EnableISR()
1289 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_Sub_EnableISR()
2258 _HVD_WriteWordMask( HVD_REG_RISC_MBOX_CLR , 0 , HVD_REG_RISC_ISR_MSK ); in HAL_HVD_Sub_Enable_ISR()
2262 … _HVD_WriteWordMask( HVD_REG_RISC_MBOX_CLR , HVD_REG_RISC_ISR_MSK , HVD_REG_RISC_ISR_MSK ); in HAL_HVD_Sub_Enable_ISR()
2290 if(_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR)& HVD_REG_RISC_ISR_MSK) in HAL_HVD_Sub_IsEnableISR()
H A DhalHVD.c2471 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EnableISR()
2475 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EnableISR()
2503 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR) & HVD_REG_RISC_ISR_MSK) in HAL_HVD_IsEnableISR()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/hvd/
H A DhalHVD_sub.c1285 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_Sub_EnableISR()
1289 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_Sub_EnableISR()
2258 _HVD_WriteWordMask( HVD_REG_RISC_MBOX_CLR , 0 , HVD_REG_RISC_ISR_MSK ); in HAL_HVD_Sub_Enable_ISR()
2262 … _HVD_WriteWordMask( HVD_REG_RISC_MBOX_CLR , HVD_REG_RISC_ISR_MSK , HVD_REG_RISC_ISR_MSK ); in HAL_HVD_Sub_Enable_ISR()
2290 if(_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR)& HVD_REG_RISC_ISR_MSK) in HAL_HVD_Sub_IsEnableISR()
H A DhalHVD.c2471 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EnableISR()
2475 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EnableISR()
2503 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR) & HVD_REG_RISC_ISR_MSK) in HAL_HVD_IsEnableISR()
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/hvd/
H A DhalHVD_sub.c1285 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_Sub_EnableISR()
1289 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_Sub_EnableISR()
2258 _HVD_WriteWordMask( HVD_REG_RISC_MBOX_CLR , 0 , HVD_REG_RISC_ISR_MSK ); in HAL_HVD_Sub_Enable_ISR()
2262 … _HVD_WriteWordMask( HVD_REG_RISC_MBOX_CLR , HVD_REG_RISC_ISR_MSK , HVD_REG_RISC_ISR_MSK ); in HAL_HVD_Sub_Enable_ISR()
2290 if(_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR)& HVD_REG_RISC_ISR_MSK) in HAL_HVD_Sub_IsEnableISR()
H A DhalHVD.c2471 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EnableISR()
2475 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EnableISR()
2503 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR) & HVD_REG_RISC_ISR_MSK) in HAL_HVD_IsEnableISR()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maserati/hvd_ex/
H A DhalHVD_EX.c3920 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3924 … _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3964 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK) in HAL_HVD_EX_IsEnableISR()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/hvd_ex/
H A DhalHVD_EX.c3941 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3945 … _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3985 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK) in HAL_HVD_EX_IsEnableISR()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/hvd_ex/
H A DhalHVD_EX.c3920 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3924 … _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3964 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK) in HAL_HVD_EX_IsEnableISR()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7821/hvd_ex/
H A DhalHVD_EX.c3920 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3924 … _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3964 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK) in HAL_HVD_EX_IsEnableISR()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/hvd_ex/
H A DhalHVD_EX.c3941 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3945 … _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3985 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK) in HAL_HVD_EX_IsEnableISR()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/hvd_ex/
H A DhalHVD_EX.c3920 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3924 … _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3964 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK) in HAL_HVD_EX_IsEnableISR()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/hvd_ex/
H A DhalHVD_EX.c3920 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3924 … _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3964 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK) in HAL_HVD_EX_IsEnableISR()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/hvd_ex/
H A DhalHVD_EX.c3920 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3924 … _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3964 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK) in HAL_HVD_EX_IsEnableISR()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/hvd_ex/
H A DhalHVD_EX.c3920 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3924 … _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3964 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK) in HAL_HVD_EX_IsEnableISR()
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/hvd_ex/
H A DhalHVD_EX.c3920 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3924 … _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK); in HAL_HVD_EX_EnableISR()
3964 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK) in HAL_HVD_EX_IsEnableISR()

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