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Searched refs:HVD_BBU_TBL_SIZE (Results 1 – 25 of 28) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DfwHVD_if.h187 #define HVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
189 #define HVD_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
192 #define MVC_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
194 #define MVC_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
197 #define RVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DfwHVD_if.h187 #define HVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
189 #define HVD_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
192 #define MVC_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
194 #define MVC_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
197 #define RVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DfwHVD_if.h187 #define HVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
189 #define HVD_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
192 #define MVC_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
194 #define MVC_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
197 #define RVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DfwHVD_if.h187 #define HVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
189 #define HVD_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
192 #define MVC_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
194 #define MVC_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
197 #define RVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/hvd_v3/
H A DfwHVD_if.h187 #define HVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
189 #define HVD_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
192 #define MVC_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
194 #define MVC_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
197 #define RVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DfwHVD_if.h187 #define HVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
189 #define HVD_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
192 #define MVC_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
194 #define MVC_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
197 #define RVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/hvd_v3/
H A DfwHVD_if.h187 #define HVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
189 #define HVD_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
192 #define MVC_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
194 #define MVC_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
197 #define RVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/hvd_v3/
H A DfwHVD_if.h187 #define HVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
189 #define HVD_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
192 #define MVC_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
194 #define MVC_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
197 #define RVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maldives/hvd_v3/
H A DfwHVD_if.h187 #define HVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
189 #define HVD_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
192 #define MVC_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
194 #define MVC_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
197 #define RVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DfwHVD_if.h187 #define HVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
189 #define HVD_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
192 #define MVC_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
194 #define MVC_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
197 #define RVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/hvd_v3/
H A DfwHVD_if.h187 #define HVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
189 #define HVD_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
192 #define MVC_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
194 #define MVC_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
197 #define RVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DfwHVD_if.h187 #define HVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
189 #define HVD_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
192 #define MVC_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
194 #define MVC_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
197 #define RVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DfwHVD_if.h187 #define HVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
189 #define HVD_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
192 #define MVC_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
194 #define MVC_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
197 #define RVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DfwHVD_if.h187 #define HVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
189 #define HVD_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
192 #define MVC_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
194 #define MVC_BBU2_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
197 #define RVD_BBU_DRAM_TBL_ENTRY (HVD_BBU_TBL_SIZE/8)
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A Dcontroller.h160 #define HVD_BBU_TBL_SIZE 0x1000 macro
174 #define HVD_BBU_TBL_SIZE 0x1000 macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maldives/vpu_v3/
H A Dcontroller.h221 #define HVD_BBU_TBL_SIZE 0x1000 macro
266 #define HVD_BBU_TBL_SIZE 0x1000 macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A Dcontroller.h221 #define HVD_BBU_TBL_SIZE 0x1000 macro
266 #define HVD_BBU_TBL_SIZE 0x1000 macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A Dcontroller.h221 #define HVD_BBU_TBL_SIZE 0x1000 macro
266 #define HVD_BBU_TBL_SIZE 0x1000 macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/vpu_v3/
H A Dcontroller.h221 #define HVD_BBU_TBL_SIZE 0x1000 macro
266 #define HVD_BBU_TBL_SIZE 0x1000 macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/vpu_v3/
H A Dcontroller.h221 #define HVD_BBU_TBL_SIZE 0x1000 macro
266 #define HVD_BBU_TBL_SIZE 0x1000 macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/vpu_v3/
H A Dcontroller.h221 #define HVD_BBU_TBL_SIZE 0x1000 macro
266 #define HVD_BBU_TBL_SIZE 0x1000 macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A Dcontroller.h221 #define HVD_BBU_TBL_SIZE 0x1000 macro
266 #define HVD_BBU_TBL_SIZE 0x1000 macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/vpu_v3/
H A Dcontroller.h223 #define HVD_BBU_TBL_SIZE 0x1000 macro
268 #define HVD_BBU_TBL_SIZE 0x1000 macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/vpu_v3/
H A Dcontroller.h223 #define HVD_BBU_TBL_SIZE 0x1000 macro
268 #define HVD_BBU_TBL_SIZE 0x1000 macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A Dcontroller.h223 #define HVD_BBU_TBL_SIZE 0x1000 macro
268 #define HVD_BBU_TBL_SIZE 0x1000 macro

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