Searched refs:CFG_AV_00_REG_PS_MODE (Results 1 – 2 of 2) sorted by relevance
165 #define CFG_AV_00_REG_PS_MODE 0x8000 macro
2734 REG16_CLR(&_RegAudioCtrl[u8Idx].CFG_AV_00, CFG_AV_00_REG_PS_MODE); in HAL_TSP_FIFO_ClearAll()2739 REG16_CLR(&_RegVideoCtrl[u8Idx].CFG_AV_00, CFG_AV_00_REG_PS_MODE); in HAL_TSP_FIFO_ClearAll()2935 REG16_SET(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_PS_MODE); in HAL_TSP_FIFO_Bypass()2939 REG16_CLR(&_RegAudioCtrl[u8AudioFltIdx].CFG_AV_00, CFG_AV_00_REG_PS_MODE); in HAL_TSP_FIFO_Bypass()2948 REG16_SET(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_PS_MODE); in HAL_TSP_FIFO_Bypass()2952 REG16_CLR(&_RegVideoCtrl[u8VideoFltIdx].CFG_AV_00, CFG_AV_00_REG_PS_MODE); in HAL_TSP_FIFO_Bypass()