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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regAV.h 98 // Description: TSP Audio/Video Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_AV_H_ 103 #define _REG_AV_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 137 138 //------------------------------------------------------------------------------------------------- 139 // Harware Capability 140 //------------------------------------------------------------------------------------------------- 141 142 143 //------------------------------------------------------------------------------------------------- 144 // Type and Structure 145 //------------------------------------------------------------------------------------------------- 146 147 typedef struct _REG_AV_ENG_Ctrl // Audio (Bank:0x3002) , Video (Bank:0x3003) 148 { 149 REG16 CFG_AV_00; 150 #define CFG_AV_00_REG_START_READ_BYPASS_ENABLE 0x0001 151 #define CFG_AV_00_REG_DIS_NULL_PKT 0x0002 152 #define CFG_AV_00_REG_TRACE_MARK_EN 0x0004 153 #define CFG_AV_00_REG_TEI_SKIP_PKT 0x0008 154 #define CFG_AV_00_REG_PUSI_THREE_BYTE_MODE 0x0010 155 #define CFG_AV_00_REG_CLR_PIDFLT_BYTE_CNT 0x0020 156 #define CFG_AV_00_REG_PID_BYPASS 0x0040 157 #define CFG_AV_00_REG_SKIP_PES_RUSH_DATA 0x0080 158 #define CFG_AV_00_REG_PES_ERR_RM_EN 0x0100 159 #define CFG_AV_00_REG_DUP_PKT_SKIP 0x0200 160 #define CFG_AV_00_REG_ALT_TS_SIZE 0x0400 161 #define CFG_AV_00_REG_REG_BD_AUD_EN 0x0800 //Audio-Only 162 #define CFG_AV_00_REG_REG_MAIN_CHANNEL 0x1000 //Audio-Only 163 #define CFG_AV_00_REG_MASK_SCR_EN 0x2000 164 #define CFG_AV_00_REG_BLOCK_DISABLE 0x4000 165 #define CFG_AV_00_REG_PS_MODE 0x8000 166 167 REG16 CFG_AV_01; 168 #define CFG_AV_01_REG_PKT_SIZE_MASK 0x00FF 169 #define CFG_AV_01_REG_PKT_SIZE_SHIFT 0 170 #define CFG_AV_01_REG_DROP_ERR_START_CODE 0x0100 171 #define CFG_AV_01_REG_DROP_TEI_ERR_START_CODE 0x0200 172 #define CFG_AV_01_REG_RESET_FIFO_PARSER 0x0400 173 #define CFG_AV_01_REG_RESET_FILTER 0x0800 174 #define CFG_AV_01_REG_PS_MODE_SRC_MASK 0xF000 175 #define CFG_AV_01_REG_PS_MODE_SRC_SHIFT 12 176 177 REG16 CFG_AV_02; 178 #define CFG_AV_02_REG_DROP_PKT_CNT_LOAD 0x0001 179 #define CFG_AV_02_REG_DROP_PKT_CNT_CLR 0x0002 180 #define CFG_AV_02_REG_DIS_CNTR_LOAD 0x0004 181 #define CFG_AV_02_REG_DIS_CNTR_CLR 0x0008 182 #define CFG_AV_02_REG_PKT_CNT_LOAD 0x0010 183 #define CFG_AV_02_REG_PKT_CNT_CLR 0x0020 184 #define CFG_AV_02_REG_RST_CC_MODE 0x0040 185 #define CFG_AV_02_REG_DIS_CNTR_INC_BY_PL 0x0080 186 #define CFG_AV_02_REG_INPUT_SRC_MASK 0x0F00 187 #define CFG_AV_02_REG_INPUT_SRC_SHIFT 8 188 #define CFG_AV_02_REG_RESET_TOP 0x0100 189 190 REG16 CFG_AV_03; // reg_drop_pkt_cntr 191 192 REG16 CFG_AV_04; // reg_dis_cont_cntr 193 194 REG16 CFG_AV_05; // reg_pes_pkt_cntr 195 196 REG16 CFG_AV_06; 197 #define CFG_AV_06_REG_PES_RSEL 0x0001 198 #define CFG_AV_06_REG_FIFO_RD 0x0002 199 #define CFG_AV_06_REG_STATUS_CLR 0x0004 200 #define CFG_AV_06_REG_LEAF_DROP_DATA_ENABLE 0x0008 201 #define CFG_AV_06_REG_FIFO_FULL_MASK 0x1000 202 #define CFG_AV_06_REG_FIFO_FULL_SHIFT 12 203 #define CFG_AV_06_REG_FIFO_EMPTY_MASK 0x2000 204 #define CFG_AV_06_REG_FIFO_EMPTY_SHIFT 13 205 #define CFG_AV_06_REG_FIFO_WR_LEVEL_MASK 0xC000 206 #define CFG_AV_06_REG_FIFO_WR_LEVEL_SHIFT 14 207 208 REG16 CFG_AV_07; 209 #define CFG_AV_07_REG_DEBUG_FIFO_DATA_MASK 0x01FF 210 #define CFG_AV_07_REG_DEBUG_FIFO_DATA_SHIFT 0 211 #define CFG_AV_07_REG_PES_WR_OVERFLOW 0x0200 212 #define CFG_AV_07_REG_FIFO_WR_LEVEL_EVER_MASK 0x0C00 213 #define CFG_AV_07_REG_FIFO_WR_LEVEL_EVER_SHIFT 10 214 #define CFG_AV_07_REG_FIFO_ERR_EVER 0x1000 215 216 REG16 CFG_AV_08; 217 #define CFG_AV_08_REG_PID_MATCH_MASK 0x1FFF 218 #define CFG_AV_08_REG_PID_MATCH_SHIFT 0 219 #define CFG_AV_08_REG_PID_CHANGE 0x2000 220 221 REG16 CFG_AV_09; // Video-Only 222 #define CFG_AV_09_REG_VPES_DISCONTI 0x0001 223 #define CFG_AV_09_REG_VPES_RD_CNT_MASK 0x00F0 224 #define CFG_AV_09_REG_VPES_RD_CNT_SHIFT 4 225 226 REG16 CFG_AV_0A_0E[0x0F - 0x0A]; // reserved 227 228 REG16 CFG_AV_0F; 229 #define CFG_AV_0F_REG_CLK_GATING_TSP 0x0001 230 #define CFG_AV_0F_REG_CLK_GATING_PARSER 0x0002 231 232 } REG_AV_ENG_Ctrl; 233 234 #endif // _REG_AV_H_ 235