xref: /utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/regAV.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

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////////////////////////////////////////////////////////////////////////////////////////////////////
//
//  File name: regAV.h
//  Description: TSP Audio/Video Register Definition
//
////////////////////////////////////////////////////////////////////////////////////////////////////

#ifndef _REG_AV_H_
#define _REG_AV_H_

//--------------------------------------------------------------------------------------------------
//  Abbreviation
//--------------------------------------------------------------------------------------------------
// Addr                             Address
// Buf                              Buffer
// Clr                              Clear
// CmdQ                             Command queue
// Cnt                              Count
// Ctrl                             Control
// Flt                              Filter
// Hw                               Hardware
// Int                              Interrupt
// Len                              Length
// Ovfw                             Overflow
// Pkt                              Packet
// Rec                              Record
// Recv                             Receive
// Rmn                              Remain
// Reg                              Register
// Req                              Request
// Rst                              Reset
// Scmb                             Scramble
// Sec                              Section
// Stat                             Status
// Sw                               Software
// Ts                               Transport Stream
// MMFI                             Multi Media File In

//--------------------------------------------------------------------------------------------------
//  Global Definition
//--------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Harware Capability
//-------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Type and Structure
//-------------------------------------------------------------------------------------------------

typedef struct _REG_AV_ENG_Ctrl // Audio (Bank:0x3002) , Video (Bank:0x3003)
{
    REG16       CFG_AV_00;
        #define CFG_AV_00_REG_START_READ_BYPASS_ENABLE                          0x0001
        #define CFG_AV_00_REG_DIS_NULL_PKT                                      0x0002
        #define CFG_AV_00_REG_TRACE_MARK_EN                                     0x0004
        #define CFG_AV_00_REG_TEI_SKIP_PKT                                      0x0008
        #define CFG_AV_00_REG_PUSI_THREE_BYTE_MODE                              0x0010
        #define CFG_AV_00_REG_CLR_PIDFLT_BYTE_CNT                               0x0020
        #define CFG_AV_00_REG_PID_BYPASS                                        0x0040
        #define CFG_AV_00_REG_SKIP_PES_RUSH_DATA                                0x0080
        #define CFG_AV_00_REG_PES_ERR_RM_EN                                     0x0100
        #define CFG_AV_00_REG_DUP_PKT_SKIP                                      0x0200
        #define CFG_AV_00_REG_ALT_TS_SIZE                                       0x0400
        #define CFG_AV_00_REG_REG_BD_AUD_EN                                     0x0800  //Audio-Only
        #define CFG_AV_00_REG_REG_MAIN_CHANNEL                                  0x1000  //Audio-Only
        #define CFG_AV_00_REG_MASK_SCR_EN                                       0x2000
        #define CFG_AV_00_REG_BLOCK_DISABLE                                     0x4000
        #define CFG_AV_00_REG_PS_MODE                                           0x8000

    REG16       CFG_AV_01;
        #define CFG_AV_01_REG_PKT_SIZE_MASK                                     0x00FF
        #define CFG_AV_01_REG_PKT_SIZE_SHIFT                                    0
        #define CFG_AV_01_REG_DROP_ERR_START_CODE                               0x0100
        #define CFG_AV_01_REG_DROP_TEI_ERR_START_CODE                           0x0200
        #define CFG_AV_01_REG_RESET_FIFO_PARSER                                 0x0400
        #define CFG_AV_01_REG_RESET_FILTER                                      0x0800
        #define CFG_AV_01_REG_PS_MODE_SRC_MASK                                  0xF000
        #define CFG_AV_01_REG_PS_MODE_SRC_SHIFT                                 12

    REG16       CFG_AV_02;
        #define CFG_AV_02_REG_DROP_PKT_CNT_LOAD                                 0x0001
        #define CFG_AV_02_REG_DROP_PKT_CNT_CLR                                  0x0002
        #define CFG_AV_02_REG_DIS_CNTR_LOAD                                     0x0004
        #define CFG_AV_02_REG_DIS_CNTR_CLR                                      0x0008
        #define CFG_AV_02_REG_PKT_CNT_LOAD                                      0x0010
        #define CFG_AV_02_REG_PKT_CNT_CLR                                       0x0020
        #define CFG_AV_02_REG_RST_CC_MODE                                       0x0040
        #define CFG_AV_02_REG_DIS_CNTR_INC_BY_PL                                0x0080
        #define CFG_AV_02_REG_INPUT_SRC_MASK                                    0x0F00
        #define CFG_AV_02_REG_INPUT_SRC_SHIFT                                   8
        #define CFG_AV_02_REG_RESET_TOP                                         0x0100

    REG16       CFG_AV_03;                                                      // reg_drop_pkt_cntr

    REG16       CFG_AV_04;                                                      // reg_dis_cont_cntr

    REG16       CFG_AV_05;                                                      // reg_pes_pkt_cntr

    REG16       CFG_AV_06;
        #define CFG_AV_06_REG_PES_RSEL                                          0x0001
        #define CFG_AV_06_REG_FIFO_RD                                           0x0002
        #define CFG_AV_06_REG_STATUS_CLR                                        0x0004
        #define CFG_AV_06_REG_LEAF_DROP_DATA_ENABLE                             0x0008
        #define CFG_AV_06_REG_FIFO_FULL_MASK                                    0x1000
        #define CFG_AV_06_REG_FIFO_FULL_SHIFT                                   12
        #define CFG_AV_06_REG_FIFO_EMPTY_MASK                                   0x2000
        #define CFG_AV_06_REG_FIFO_EMPTY_SHIFT                                  13
        #define CFG_AV_06_REG_FIFO_WR_LEVEL_MASK                                0xC000
        #define CFG_AV_06_REG_FIFO_WR_LEVEL_SHIFT                               14

    REG16       CFG_AV_07;
        #define CFG_AV_07_REG_DEBUG_FIFO_DATA_MASK                              0x01FF
        #define CFG_AV_07_REG_DEBUG_FIFO_DATA_SHIFT                             0
        #define CFG_AV_07_REG_PES_WR_OVERFLOW                                   0x0200
        #define CFG_AV_07_REG_FIFO_WR_LEVEL_EVER_MASK                           0x0C00
        #define CFG_AV_07_REG_FIFO_WR_LEVEL_EVER_SHIFT                          10
        #define CFG_AV_07_REG_FIFO_ERR_EVER                                     0x1000

    REG16       CFG_AV_08;
        #define CFG_AV_08_REG_PID_MATCH_MASK                                    0x1FFF
        #define CFG_AV_08_REG_PID_MATCH_SHIFT                                   0
        #define CFG_AV_08_REG_PID_CHANGE                                        0x2000

    REG16       CFG_AV_09;                                                      // Video-Only
        #define CFG_AV_09_REG_VPES_DISCONTI                                     0x0001
        #define CFG_AV_09_REG_VPES_RD_CNT_MASK                                  0x00F0
        #define CFG_AV_09_REG_VPES_RD_CNT_SHIFT                                 4

    REG16       CFG_AV_0A_0E[0x0F - 0x0A];                                      // reserved

    REG16       CFG_AV_0F;
        #define CFG_AV_0F_REG_CLK_GATING_TSP                                    0x0001
        #define CFG_AV_0F_REG_CLK_GATING_PARSER                                 0x0002

} REG_AV_ENG_Ctrl;

#endif // _REG_AV_H_