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Searched refs:pic_wd64 (Results 1 – 4 of 4) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu541.c1236 RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6; in vepu541_h265_set_me_regs() local
1310 … (pic_wd64 * (tmpMin - 1)) + ((pic_wd64 >= swin_scope_wd16) ? swin_scope_wd16 : pic_wd64 * 2); in vepu541_h265_set_me_regs()
1314 pic_wd64 = pic_wd64 << 6; in vepu541_h265_set_me_regs()
1316 if (pic_wd64 <= 512) in vepu541_h265_set_me_regs()
1318 else if (pic_wd64 <= 1024) in vepu541_h265_set_me_regs()
1320 else if (pic_wd64 <= 2048) in vepu541_h265_set_me_regs()
1322 else if (pic_wd64 <= 4096) in vepu541_h265_set_me_regs()
1335 RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6; in vepu540_h265_set_me_ram() local
1341 if (tile_ctu_endx + 1 + (cime_srch_w + 3) / 4 > pic_wd64) in vepu540_h265_set_me_ram()
1342 pic_cime_temp = pic_wd64 * 64; in vepu540_h265_set_me_ram()
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H A Dhal_h265e_vepu580.c268 RK_U32 pic_wd64 = ((regs->reg0196_enc_rsl.pic_wd8_m1 + 1) * 8 + 63) / 64; in vepu580_h265_set_me_ram() local
276 frm_sta = mpp_clip(frm_sta, 0, pic_wd64 - 1); in vepu580_h265_set_me_ram()
278 frm_end = pic_wd64 - 1 + (x_gmv + srch_w) / 16; in vepu580_h265_set_me_ram()
280 frm_end = pic_wd64 - 1 + (x_gmv + srch_w + 15) / 16; in vepu580_h265_set_me_ram()
282 frm_end = mpp_clip(frm_end, 0, pic_wd64 - 1); in vepu580_h265_set_me_ram()
292 frm_sta = mpp_clip(frm_sta, 0, pic_wd64 - 1); in vepu580_h265_set_me_ram()
299 frm_end = mpp_clip(frm_end, 0, pic_wd64 - 1); in vepu580_h265_set_me_ram()
2320 RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6; in vepu580_h265_set_me_regs() local
2399 … (pic_wd64 * (tmpMin - 1)) + ((pic_wd64 >= swin_scope_wd16) ? swin_scope_wd16 : pic_wd64 * 2); in vepu580_h265_set_me_regs()
2403 pic_wd64 = pic_wd64 << 6; in vepu580_h265_set_me_regs()
[all …]
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu541.c1244 RK_S32 pic_wd64 = (pic_w + 63) / 64; in setup_vepu541_me() local
1330 if (pic_wd64 >= swin_scope_wd16) in setup_vepu541_me()
1333 temp1 = pic_wd64 * 2; in setup_vepu541_me()
1334 regs->reg091.cme_rama_max = pic_wd64 * (temp0 - 1) + temp1; in setup_vepu541_me()
1363 regs->reg091.cme_rama_max = (swin_all_4_ver - 1) * pic_wd64 + swin_all_16_hor; in setup_vepu541_me()
1365 … regs->reg091.cme_rama_max = (regs->reg091.cme_rama_h - 1) * pic_wd64 + swin_all_16_hor; in setup_vepu541_me()
H A Dhal_h264e_vepu580.c1736 RK_S32 pic_wd64 = MPP_ALIGN(sps->pic_width_in_mbs * 16, 64) / 64; in calc_cime_parameter() local
1745 frm_sta = mpp_clip(frm_sta, 0, pic_wd64 - 1); in calc_cime_parameter()
1748 frm_end = pic_wd64 - 1 + (x_gmv + srch_w) / 16; in calc_cime_parameter()
1750 frm_end = pic_wd64 - 1 + (x_gmv + srch_w + 15) / 16; in calc_cime_parameter()
1752 frm_end = mpp_clip(frm_end, 0, pic_wd64 - 1); in calc_cime_parameter()