Lines Matching refs:pic_wd64
1236 RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6; in vepu541_h265_set_me_regs() local
1310 … (pic_wd64 * (tmpMin - 1)) + ((pic_wd64 >= swin_scope_wd16) ? swin_scope_wd16 : pic_wd64 * 2); in vepu541_h265_set_me_regs()
1314 pic_wd64 = pic_wd64 << 6; in vepu541_h265_set_me_regs()
1316 if (pic_wd64 <= 512) in vepu541_h265_set_me_regs()
1318 else if (pic_wd64 <= 1024) in vepu541_h265_set_me_regs()
1320 else if (pic_wd64 <= 2048) in vepu541_h265_set_me_regs()
1322 else if (pic_wd64 <= 4096) in vepu541_h265_set_me_regs()
1335 RK_S32 pic_wd64 = MPP_ALIGN(syn->pp.pic_width, 64) >> 6; in vepu540_h265_set_me_ram() local
1341 if (tile_ctu_endx + 1 + (cime_srch_w + 3) / 4 > pic_wd64) in vepu540_h265_set_me_ram()
1342 pic_cime_temp = pic_wd64 * 64; in vepu540_h265_set_me_ram()
1346 if (tile_ctu_endx + 1 + (cime_srch_w + 3) / 4 > pic_wd64) in vepu540_h265_set_me_ram()
1347 pic_cime_temp = (pic_wd64 - tile_ctu_stax + (cime_srch_w + 3) / 4) * 64; in vepu540_h265_set_me_ram()
1374 RK_S32 pic_wd64 = pic_cime_temp / 64; in vepu540_h265_set_me_ram() local
1380 …regs->me_ram.cime_rama_max = (pic_wd64 * (tmpMin - 1)) + ((pic_wd64 >= swin_scope_wd16) ? swin_sco… in vepu540_h265_set_me_ram()
1508 RK_S32 pic_wd64, pic_h64; in hal_h265e_v541_gen_regs() local
1515 pic_wd64 = (syn->pp.pic_width + 63) / 64; in hal_h265e_v541_gen_regs()
1550 regs->enc_pic.log2_ctu_num = ceil(log2((double)pic_wd64 * pic_h64)); in hal_h265e_v541_gen_regs()