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Searched refs:out_fmt (Results 1 – 25 of 32) sorted by relevance

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/rockchip-linux_mpp/mpp/codec/
H A Dmpp_dec.c78 if (MPP_FRAME_FMT_IS_FBC(base->out_fmt)) { in mpp_dec_check_fbc_cap()
79 RK_U32 fbc = (RK_U32)base->out_fmt & MPP_FRAME_FBC_MASK; in mpp_dec_check_fbc_cap()
80 RK_U32 fmt = base->out_fmt - fbc; in mpp_dec_check_fbc_cap()
85 base->out_fmt = (MppFrameFormat)fmt; in mpp_dec_check_fbc_cap()
107 dec->cfg->base.out_fmt = mpp_frame_get_fmt(frame); in mpp_dec_proc_cfg()
108 mpp_log_f("found MPP_DEC_SET_FRAME_INFO fmt %x\n", dec->cfg->base.out_fmt); in mpp_dec_proc_cfg()
940 dec_dbg_func("fast out_fmt %d\n", base->out_fmt); in mpp_dec_set_cfg_by_cmd()
/rockchip-linux_mpp/mpp/inc/
H A Dmpp_dec_cfg.h84 MppFrameFormat out_fmt; member
/rockchip-linux_mpp/mpp/base/
H A Dmpp_dec_cfg.c32 ENTRY(prefix, u32, rk_u32, out_fmt, FLAG_INCR, base, out_fmt) \
/rockchip-linux_mpp/mpp/codec/dec/avs2/
H A Davs2d_dpb.c500 if (MPP_FRAME_FMT_IS_FBC(p_dec->init.cfg->base.out_fmt)) { in dpb_alloc_frame()
504 …mpp_frame_set_fmt(mframe, mpp_frame_get_fmt(mframe) | (p_dec->init.cfg->base.out_fmt & (MPP_FRAME_… in dpb_alloc_frame()
517 } else if (MPP_FRAME_FMT_IS_TILE(p_dec->init.cfg->base.out_fmt)) in dpb_alloc_frame()
518 …mpp_frame_set_fmt(mframe, mpp_frame_get_fmt(mframe) | (p_dec->init.cfg->base.out_fmt & (MPP_FRAME_… in dpb_alloc_frame()
/rockchip-linux_mpp/mpp/hal/rkenc/jpege/
H A Dhal_jpege_vpu720.c198 MppFrameChromaFormat out_fmt = syntax->format_out; in jpege_vpu720_setup_format() local
318 switch (out_fmt) { in jpege_vpu720_setup_format()
474 reg_base->reg032_sw_src_fmt.out_fmt = ctx->fmt_cfg.out_format; in hal_jpege_vpu720_gen_regs()
H A Dhal_jpege_vpu720_reg.h275 RK_U32 out_fmt : 2; member
H A Dhal_jpege_vepu540c_reg.h480 RK_U32 out_fmt : 1; member
/rockchip-linux_mpp/mpp/codec/dec/h264/
H A Dh264d_init.c420 MppFrameFormat out_fmt = p_Dec->cfg->base.out_fmt; in dpb_mark_malloc() local
437 if (MPP_FRAME_FMT_IS_FBC(out_fmt)) { in dpb_mark_malloc()
454 fmt |= (out_fmt & MPP_FRAME_FBC_MASK); in dpb_mark_malloc()
457 p_Dec->cfg->base.out_fmt = fmt; in dpb_mark_malloc()
458 out_fmt = fmt; in dpb_mark_malloc()
459 } else if (MPP_FRAME_FMT_IS_TILE(out_fmt)) { in dpb_mark_malloc()
460 fmt |= (out_fmt & MPP_FRAME_TILE_FLAG); in dpb_mark_malloc()
461 p_Dec->cfg->base.out_fmt = fmt; in dpb_mark_malloc()
462 out_fmt = fmt; in dpb_mark_malloc()
478 if (MPP_FRAME_FMT_IS_FBC(out_fmt)) { in dpb_mark_malloc()
/rockchip-linux_mpp/mpp/codec/dec/av1/
H A Dav1d_parser.c126 (s->cfg->base.out_fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV420SP) in get_pixel_format()
786 if (MPP_FRAME_FMT_IS_FBC(s->cfg->base.out_fmt)) { in get_current_frame()
798 ctx->pix_fmt |= s->cfg->base.out_fmt & (MPP_FRAME_FBC_MASK); in get_current_frame()
808 } else if (MPP_FRAME_FMT_IS_TILE(s->cfg->base.out_fmt)) { in get_current_frame()
809 ctx->pix_fmt |= s->cfg->base.out_fmt & (MPP_FRAME_TILE_FLAG); in get_current_frame()
/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu540c_common.c197 regs->reg0274_src_fmt.out_fmt = 1; in vepu540c_set_jpeg_reg()
H A Dvepu540c_common.h587 RK_U32 out_fmt : 1; member
H A Dvepu510_common.h560 RK_U32 out_fmt : 1; member
/rockchip-linux_mpp/mpp/codec/dec/h265/
H A Dh265d_refs.c86 MppFrameFormat fmt = s->h265dctx->cfg->base.out_fmt & (~MPP_FRAME_FMT_MASK); in alloc_frame()
/rockchip-linux_mpp/mpp/codec/dec/vp9/
H A Dvp9d_parser.c400 if (MPP_FRAME_FMT_IS_FBC(s->cfg->base.out_fmt)) { in vp9_alloc_frame()
404 mpp_frame_set_fmt(frame->f, ctx->pix_fmt | ((s->cfg->base.out_fmt & (MPP_FRAME_FBC_MASK)))); in vp9_alloc_frame()
416 if (MPP_FRAME_FMT_IS_TILE(s->cfg->base.out_fmt)) in vp9_alloc_frame()
417 … mpp_frame_set_fmt(frame->f, ctx->pix_fmt | ((s->cfg->base.out_fmt & (MPP_FRAME_TILE_FLAG)))); in vp9_alloc_frame()
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu540c_reg.h399 RK_U32 out_fmt : 1; member
H A Dhal_h264e_vepu580.c728 regs->reg_base.src_fmt.out_fmt = (fmt == MPP_FMT_YUV400) ? 0 : 1; in setup_vepu580_prep()
866 regs->reg_base.src_fmt.out_fmt = 1; in vepu580_h264e_use_pass1_patch()
H A Dhal_h264e_vepu510.c725 reg_frm->common.src_fmt.out_fmt = ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400 ? 0 : 1); in setup_vepu510_prep()
887 reg_frm->common.src_fmt.out_fmt = 1; in vepu510_h264e_use_pass1_patch()
H A Dhal_h264e_vepu511.c724 reg_frm->common.src_fmt.out_fmt = ((fmt & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400 ? 0 : 1); in setup_vepu511_prep()
860 reg_frm->common.src_fmt.out_fmt = 1; in vepu511_h264e_use_pass1_patch()
H A Dhal_h264e_vepu580_reg.h377 RK_U32 out_fmt : 1; member
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu540c_reg.h487 RK_U32 out_fmt : 1; member
H A Dhal_h265e_vepu580.c1992 reg_base->reg0198_src_fmt.out_fmt = (prep_cfg->format == MPP_FMT_YUV400) ? 0 : 1; in vepu580_h265_set_pp_regs()
2586 reg_base->reg0198_src_fmt.out_fmt = 1; in vepu580_h265e_use_pass1_patch()
2823 (regs->reg0239_synt_sli0.sli_sao_chrm_flg && regs->reg0198_src_fmt.out_fmt)))) { in hal_h265e_v580_set_uniform_tile()
H A Dhal_h265e_vepu510.c1417 …reg_frm->common.src_fmt.out_fmt = ((prep_cfg->format & MPP_FRAME_FMT_MASK) == MPP_FMT_YUV400) ? 0 … in vepu510_h265_set_pp_regs()
1731 reg_frm->common.src_fmt.out_fmt = 1; in vepu510_h265e_use_pass1_patch()
/rockchip-linux_mpp/mpp/hal/vpu/av1d/
H A Dhal_av1d_vdpu.c2217 RK_U32 out_fmt = 0; in vdpu_av1d_gen_regs() local
2220 out_fmt = 3; in vdpu_av1d_gen_regs()
2227 regs->vdpu_av1d_pp_cfg.swreg322.sw_pp_out_format = out_fmt; in vdpu_av1d_gen_regs()
/rockchip-linux_mpp/mpp/hal/rkdec/avs2d/
H A Dhal_avs2d_rkv.c546 if (MPP_FRAME_FMT_IS_FBC(cfg->cfg->base.out_fmt)) in hal_avs2d_rkv_init()
H A Dhal_avs2d_vdpu382.c612 if (MPP_FRAME_FMT_IS_FBC(cfg->cfg->base.out_fmt)) in hal_avs2d_vdpu382_init()

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