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Searched refs:offset_sclst (Results 1 – 12 of 12) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkdec/h265d/
H A Dhal_h265d_ctx.h86 RK_U32 offset_sclst[MAX_GEN_REG]; member
H A Dhal_h265d_vdpu382.c145 reg_ctx->offset_sclst[i] = SCALIST_OFFSET(i); in hal_h265d_vdpu382_init()
153 reg_ctx->sclst_offset = reg_ctx->offset_sclst[0]; in hal_h265d_vdpu382_init()
682 reg_ctx->sclst_offset = reg_ctx->offset_sclst[i]; in hal_h265d_vdpu382_gen_regs()
H A Dhal_h265d_vdpu384a.c133 reg_ctx->offset_sclst[i] = SCALIST_OFFSET(i); in hal_h265d_vdpu384a_init()
142 reg_ctx->sclst_offset = reg_ctx->offset_sclst[0]; in hal_h265d_vdpu384a_init()
811 reg_ctx->sclst_offset = reg_ctx->offset_sclst[i]; in hal_h265d_vdpu384a_gen_regs()
H A Dhal_h265d_vdpu34x.c147 reg_ctx->offset_sclst[i] = SCALIST_OFFSET(i); in hal_h265d_vdpu34x_init()
155 reg_ctx->sclst_offset = reg_ctx->offset_sclst[0]; in hal_h265d_vdpu34x_init()
876 reg_ctx->sclst_offset = reg_ctx->offset_sclst[i]; in hal_h265d_vdpu34x_gen_regs()
H A Dhal_h265d_vdpu383.c157 reg_ctx->offset_sclst[i] = SCALIST_OFFSET(i); in hal_h265d_vdpu383_init()
167 reg_ctx->sclst_offset = reg_ctx->offset_sclst[0]; in hal_h265d_vdpu383_init()
892 reg_ctx->sclst_offset = reg_ctx->offset_sclst[i]; in hal_h265d_vdpu383_gen_regs()
/rockchip-linux_mpp/mpp/hal/rkdec/avs2d/
H A Dhal_avs2d_vdpu383.c47 RK_U32 offset_sclst; member
561 reg_ctx->reg_buf[i].offset_sclst = AVS2_SCALIST_OFFSET(i); in hal_avs2d_vdpu383_init()
567 reg_ctx->sclst_offset = reg_ctx->reg_buf[0].offset_sclst; in hal_avs2d_vdpu383_init()
661 reg_ctx->sclst_offset = reg_ctx->reg_buf[i].offset_sclst; in hal_avs2d_vdpu383_gen_regs()
H A Dhal_avs2d_rkv.c55 RK_U32 offset_sclst; member
537 reg_ctx->reg_buf[i].offset_sclst = AVS2_SCALIST_OFFSET(i); in hal_avs2d_rkv_init()
543 reg_ctx->sclst_offset = reg_ctx->reg_buf[0].offset_sclst; in hal_avs2d_rkv_init()
636 reg_ctx->sclst_offset = reg_ctx->reg_buf[i].offset_sclst; in hal_avs2d_rkv_gen_regs()
H A Dhal_avs2d_vdpu382.c55 RK_U32 offset_sclst; member
603 reg_ctx->reg_buf[i].offset_sclst = AVS2_SCALIST_OFFSET(i); in hal_avs2d_vdpu382_init()
609 reg_ctx->sclst_offset = reg_ctx->reg_buf[0].offset_sclst; in hal_avs2d_vdpu382_init()
703 reg_ctx->sclst_offset = reg_ctx->reg_buf[i].offset_sclst; in hal_avs2d_vdpu382_gen_regs()
/rockchip-linux_mpp/mpp/hal/rkdec/h264d/
H A Dhal_h264d_vdpu34x.c144 RK_U32 offset_sclst[VDPU34X_FAST_REG_SET_CNT]; member
732 reg_ctx->offset_sclst[i] = VDPU34X_SCALING_LIST_OFFSET(i); in vdpu34x_h264d_init()
739 reg_ctx->sclst_offset = reg_ctx->offset_sclst[0]; in vdpu34x_h264d_init()
946 ctx->sclst_offset = ctx->offset_sclst[i]; in vdpu34x_h264d_gen_regs()
H A Dhal_h264d_vdpu384a.c79 RK_U32 offset_sclst[VDPU384A_FAST_REG_SET_CNT]; member
610 reg_ctx->offset_sclst[i] = VDPU384A_SCALING_LIST_OFFSET(i); in vdpu384a_h264d_init()
618 reg_ctx->sclst_offset = reg_ctx->offset_sclst[0]; in vdpu384a_h264d_init()
818 ctx->sclst_offset = ctx->offset_sclst[i]; in vdpu384a_h264d_gen_regs()
H A Dhal_h264d_vdpu383.c91 RK_U32 offset_sclst[VDPU383_FAST_REG_SET_CNT]; member
654 reg_ctx->offset_sclst[i] = VDPU383_SCALING_LIST_OFFSET(i); in vdpu383_h264d_init()
663 reg_ctx->sclst_offset = reg_ctx->offset_sclst[0]; in vdpu383_h264d_init()
867 ctx->sclst_offset = ctx->offset_sclst[i]; in vdpu383_h264d_gen_regs()
H A Dhal_h264d_vdpu382.c148 RK_U32 offset_sclst[VDPU382_FAST_REG_SET_CNT]; member
753 reg_ctx->offset_sclst[i] = VDPU382_SCALING_LIST_OFFSET(i); in vdpu382_h264d_init()
760 reg_ctx->sclst_offset = reg_ctx->offset_sclst[0]; in vdpu382_h264d_init()
975 ctx->sclst_offset = ctx->offset_sclst[i]; in vdpu382_h264d_gen_regs()