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Searched refs:mb_w (Results 1 – 25 of 25) sorted by relevance

/rockchip-linux_mpp/utils/
H A Dmpp_enc_roi_utils.c193 RK_S32 mb_w = MPP_ALIGN(w, 64) / 64; in vepu54x_h265_set_roi() local
195 RK_S32 ctu_line = mb_w; in vepu54x_h265_set_roi()
201 for (i = 0; i < mb_w; i++) { in vepu54x_h265_set_roi()
226 RK_S32 mb_w = MPP_ALIGN(ctx->w, 16) / 16; in gen_vepu54x_roi() local
228 RK_S32 stride_h = MPP_ALIGN(mb_w, 4); in gen_vepu54x_roi()
288 mpp_assert(pos_x_init >= 0 && pos_x_init < mb_w); in gen_vepu54x_roi()
289 mpp_assert(pos_x_end >= 0 && pos_x_end <= mb_w); in gen_vepu54x_roi()
463 RK_S32 mb_w = MPP_ALIGN(ctx->w, 16) / 16; in gen_vepu580_roi_h264() local
465 RK_S32 stride_h = MPP_ALIGN(mb_w, 4); in gen_vepu580_roi_h264()
674 RK_S32 mb_w = MPP_ALIGN(impl->w, 16) / 16; in mpp_enc_roi_init() local
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H A Dmpi_enc_utils.c1208 RK_U32 mb_w = step_x; in mpi_enc_gen_osd_data() local
1222 RK_U32 region_size = MPP_ALIGN(mb_w * mb_h * 256, 16); in mpi_enc_gen_osd_data()
1227 region->num_mb_x = mb_w; in mpi_enc_gen_osd_data()
1230 region->enable = (mb_w && mb_h); in mpi_enc_gen_osd_data()
1257 mb_w = region->num_mb_x; in mpi_enc_gen_osd_data()
1261 memset(ptr + buf_offset, k, mb_w * mb_h * 256); in mpi_enc_gen_osd_data()
/rockchip-linux_mpp/mpp/hal/vpu/h264e/
H A Dhal_h264e_vepu2_v2.c289 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in setup_intra_refresh() local
309 right = mb_w; in setup_intra_refresh()
319 left = mpp_clip(left, 0, mb_w); in setup_intra_refresh()
320 right = mpp_clip(right, 0, mb_w); in setup_intra_refresh()
350 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in hal_h264e_vepu2_gen_regs_v2() local
358 mb_w = ctx->sps->pic_height_in_mbs; in hal_h264e_vepu2_gen_regs_v2()
400 if (mb_w * mb_h > 3600) in hal_h264e_vepu2_gen_regs_v2()
413 RK_U32 scaler = MPP_MAX(1, 200 / (mb_w + mb_h)); in hal_h264e_vepu2_gen_regs_v2()
510 | VEPU_REG_ROI1_LEFT_MB(mb_w) in hal_h264e_vepu2_gen_regs_v2()
511 | VEPU_REG_ROI1_RIGHT_MB(mb_w); in hal_h264e_vepu2_gen_regs_v2()
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H A Dhal_h264e_vepu1_v2.c300 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in hal_h264e_vepu1_gen_regs_v2() local
308 mb_w = ctx->sps->pic_height_in_mbs; in hal_h264e_vepu1_gen_regs_v2()
339 | VEPU_REG_INTRA_AREA_LEFT(mb_w) in hal_h264e_vepu1_gen_regs_v2()
340 | VEPU_REG_INTRA_AREA_RIGHT(mb_w); in hal_h264e_vepu1_gen_regs_v2()
359 if (mb_w * mb_h > 3600) in hal_h264e_vepu1_gen_regs_v2()
374 RK_U32 scaler = MPP_MAX(1, 200 / (mb_w + mb_h)); in hal_h264e_vepu1_gen_regs_v2()
460 | VEPU_REG_ROI1_LEFT_MB(mb_w) in hal_h264e_vepu1_gen_regs_v2()
461 | VEPU_REG_ROI1_RIGHT_MB(mb_w); in hal_h264e_vepu1_gen_regs_v2()
466 | VEPU_REG_ROI2_LEFT_MB(mb_w) in hal_h264e_vepu1_gen_regs_v2()
467 | VEPU_REG_ROI2_RIGHT_MB(mb_w); in hal_h264e_vepu1_gen_regs_v2()
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H A Dhal_h264e_vepu_v2.c35 RK_S32 mb_w; member
523 p->mb_w = MPP_ALIGN(prep->width, 16) / 16; in h264e_vepu_mbrc_setup()
526 p->mbs = p->mb_w * p->mb_h; in h264e_vepu_mbrc_setup()
/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu541_common.c40 RK_S32 mb_w = MPP_ALIGN(w, 16) / 16; in vepu541_set_one_roi() local
42 RK_S32 stride_h = MPP_ALIGN(mb_w, 4); in vepu541_set_one_roi()
59 pos_x_end = MPP_MIN(pos_x_end, mb_w); in vepu541_set_one_roi()
95 RK_S32 mb_w = MPP_ALIGN(w, 16) / 16; in vepu541_set_roi() local
97 RK_S32 stride_h = MPP_ALIGN(mb_w, 4); in vepu541_set_roi()
/rockchip-linux_mpp/mpp/codec/enc/jpeg/
H A Djpege_api_v2.c258 RK_U32 mb_w = syntax->mcu_hor_cnt; in jpege_proc_hal() local
266 part_rows = (part_mbs + mb_w - 1) / mb_w; in jpege_proc_hal()
/rockchip-linux_mpp/mpp/codec/enc/h265/
H A Dh265e_ps.c463 RK_S32 mb_w = (sps->m_picWidthInLumaSamples + sps->m_maxCUSize - 1) / sps->m_maxCUSize; in h265e_set_pps() local
489 tile_width = (index + 1) * mb_w / (pps->m_nNumTileColumnsMinus1 + 1) - in h265e_set_pps()
490 index * mb_w / (pps->m_nNumTileColumnsMinus1 + 1); in h265e_set_pps()
494 tile_width = mb_w - index * mb_w / (pps->m_nNumTileColumnsMinus1 + 1); in h265e_set_pps()
/rockchip-linux_mpp/mpp/codec/rc/
H A Dvp8e_rc.c62 RK_S32 mb_w = MPP_ALIGN(usr_cfg->width, 16) / 16; in rc_model_v2_vp8_hal_start() local
90 p->start_qp = vp8_initial_qp(info->bit_target, mb_w * mb_h * 16 * 16); in rc_model_v2_vp8_hal_start()
H A Drc_model_v2_smt.c955 RK_S32 mb_w = MPP_ALIGN(p->usr_cfg.width, 16) / 16; in rc_model_v2_smt_start() local
960 qp_out_f0 = cal_smt_first_i_start_qp(p->bits_tgt_upper * ratio, mb_w * mb_h); in rc_model_v2_smt_start()
973 mb_w, mb_h, ratio, p->qp_out); in rc_model_v2_smt_start()
H A Drc_model_v2.c718 RK_S32 mb_w = MPP_ALIGN(usr_cfg->width, 16) / 16; in reenc_calc_cbr_ratio() local
768 RK_U32 tar_bpp = target_bit / (mb_w * mb_h); in reenc_calc_cbr_ratio()
1570 RK_S32 mb_w = MPP_ALIGN(usr_cfg->width, 16) / 16; in rc_model_v2_hal_start() local
1611 info->quality_target = cal_first_i_start_qp(info->bit_target, mb_w * mb_h); in rc_model_v2_hal_start()
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu580_tune.c342 RK_S32 mb_w = MPP_ALIGN(ctx->cfg->prep.width, 64) / 16; in setup_vepu580_qpmap_buf() local
345 = mb_w * mb_h * 8; in setup_vepu580_qpmap_buf()
347 = mb_w * mb_h * 2; in setup_vepu580_qpmap_buf()
349 = mb_w * mb_h; in setup_vepu580_qpmap_buf()
H A Dhal_h264e_vepu580.c1251 RK_S32 mb_w = sps->pic_width_in_mbs; in setup_vepu580_rc_base() local
1257 RK_S32 mb_target_bits_mul_16 = (rc_info->bit_target << 4) / (mb_w * mb_h); in setup_vepu580_rc_base()
1299 mb_target_bits = (mb_target_bits_mul_16 * mb_w) >> 4; in setup_vepu580_rc_base()
1307 regs->reg_base.rc_cfg.rc_ctu_num = mb_w; in setup_vepu580_rc_base()
1438 RK_S32 mb_w = MPP_ALIGN(w, 16) / 16; in vepu580_h264_set_one_roi() local
1440 RK_S32 stride_h = MPP_ALIGN(mb_w, 4); in vepu580_h264_set_one_roi()
1457 pos_x_end = MPP_MIN(pos_x_end, mb_w); in vepu580_h264_set_one_roi()
1486 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in setup_vepu580_intra_refresh() local
1488 RK_U32 w = mb_w * 16; in setup_vepu580_intra_refresh()
1492 RK_U32 stride_h = MPP_ALIGN(mb_w, 4); in setup_vepu580_intra_refresh()
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H A Dhal_h264e_vepu510_tune.c141 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in vepu510_h264e_tune_stat_update() local
143 RK_U32 b16_num = mb_w * mb_h; in vepu510_h264e_tune_stat_update()
H A Dhal_h264e_vepu511.c1161 RK_S32 mb_w = sps->pic_width_in_mbs; in setup_vepu511_rc_base() local
1166 RK_S32 mb_target_bits_mul_16 = (rc_info->bit_target << 4) / (mb_w * mb_h); in setup_vepu511_rc_base()
1206 mb_target_bits = (mb_target_bits_mul_16 * mb_w) >> 4; in setup_vepu511_rc_base()
1214 reg_frm->common.rc_cfg.rc_ctu_num = mb_w; in setup_vepu511_rc_base()
1365 RK_S32 mb_w = MPP_ALIGN(w, 16) / 16; in vepu511_h264_set_one_roi() local
1367 RK_S32 stride_h = MPP_ALIGN(mb_w, 4); in vepu511_h264_set_one_roi()
1384 pos_x_end = MPP_MIN(pos_x_end, mb_w); in vepu511_h264_set_one_roi()
1413 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in setup_vepu511_intra_refresh() local
1415 RK_U32 w = mb_w * 16; in setup_vepu511_intra_refresh()
1420 RK_U32 stride_h = MPP_ALIGN(mb_w, 4); in setup_vepu511_intra_refresh()
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H A Dhal_h264e_vepu510.c1166 RK_S32 mb_w = sps->pic_width_in_mbs; in setup_vepu510_rc_base() local
1172 RK_S32 mb_target_bits_mul_16 = (rc_info->bit_target << 4) / (mb_w * mb_h); in setup_vepu510_rc_base()
1214 mb_target_bits = (mb_target_bits_mul_16 * mb_w) >> 4; in setup_vepu510_rc_base()
1222 reg_frm->common.rc_cfg.rc_ctu_num = mb_w; in setup_vepu510_rc_base()
1365 RK_S32 mb_w = MPP_ALIGN(w, 16) / 16; in vepu510_h264_set_one_roi() local
1367 RK_S32 stride_h = MPP_ALIGN(mb_w, 4); in vepu510_h264_set_one_roi()
1384 pos_x_end = MPP_MIN(pos_x_end, mb_w); in vepu510_h264_set_one_roi()
1413 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in setup_vepu510_intra_refresh() local
1415 RK_U32 w = mb_w * 16; in setup_vepu510_intra_refresh()
1420 RK_U32 stride_h = MPP_ALIGN(mb_w, 4); in setup_vepu510_intra_refresh()
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H A Dhal_h264e_vepu541.c821 RK_S32 mb_w = sps->pic_width_in_mbs; in setup_vepu541_rc_base() local
827 RK_S32 mb_target_bits_mul_16 = (rc_info->bit_target << 4) / (mb_w * mb_h); in setup_vepu541_rc_base()
839 mb_target_bits = (mb_target_bits_mul_16 * mb_w) >> 4; in setup_vepu541_rc_base()
850 regs->reg050.rc_ctu_num = mb_w; in setup_vepu541_rc_base()
1221 RK_S32 mb_w = MPP_ALIGN(width, 16) >> 4; in setup_vepu540_force_slice_split() local
1230 regs->reg087.sli_splt_cnum_m1 = mb_w - 1; in setup_vepu540_force_slice_split()
1807 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in hal_h264e_vepu541_ret_task() local
1809 RK_U32 mbs = mb_w * mb_h; in hal_h264e_vepu541_ret_task()
H A Dhal_h264e_vepu540c.c894 RK_S32 mb_w = sps->pic_width_in_mbs; in setup_vepu540c_rc_base() local
900 RK_S32 mb_target_bits_mul_16 = (rc_info->bit_target << 4) / (mb_w * mb_h); in setup_vepu540c_rc_base()
942 mb_target_bits = (mb_target_bits_mul_16 * mb_w) >> 4; in setup_vepu540c_rc_base()
951 regs->reg_base.rc_cfg.rc_ctu_num = mb_w; in setup_vepu540c_rc_base()
1135 RK_U32 mb_w = MPP_ALIGN(cfg->prep.width, 16) / 16; in setup_vepu540c_split() local
1137 RK_U32 slice_num = (mb_w * mb_h + cfg->split.split_arg - 1) / cfg->split.split_arg; in setup_vepu540c_split()
1690 RK_U32 mb_w = ctx->sps->pic_width_in_mbs; in hal_h264e_vepu540c_ret_task() local
1692 RK_U32 mbs = mb_w * mb_h; in hal_h264e_vepu540c_ret_task()
/rockchip-linux_mpp/mpp/codec/enc/h264/
H A Dh264e_slice.h91 RK_S32 mb_w; member
H A Dh264e_slice.c48 slice->mb_w = sps->pic_width_in_mbs; in h264e_slice_update()
947 for (i = 0; i < slice->mb_w * slice->mb_h; i++) { in h264e_slice_write_pskip()
961 mpp_writer_put_ue(s, slice->mb_w * slice->mb_h); in h264e_slice_write_pskip()
963 mpp_writer_bits(s), slice->mb_w * slice->mb_h); in h264e_slice_write_pskip()
/rockchip-linux_mpp/mpp/hal/vpu/jpege/
H A Dhal_jpege_vepu2_v2.c250 RK_U32 mb_w = MPP_ALIGN(width, 16) / 16; in hal_jpege_vepu2_get_task() local
305 i, part_rows, mb_w * part_rows); in hal_jpege_vepu2_get_task()
311 ctx->syntax.restart_ri = mb_w * part_rows; in hal_jpege_vepu2_get_task()
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu540c.c1161 RK_U32 mb_w = MPP_ALIGN(enc_cfg->prep.width, 64) / 64; in vepu540c_h265_set_split() local
1166 mb_w = mb_w / 2; in vepu540c_h265_set_split()
1168 slice_num = (mb_w * mb_h + cfg->split_arg - 1) / cfg->split_arg; in vepu540c_h265_set_split()
H A Dhal_h265e_vepu510.c1846 RK_U32 mb_w = MPP_ALIGN(enc_cfg->prep.width, 32) / 32; in setup_vepu510_split() local
1851 mb_w = mb_w / 2; in setup_vepu510_split()
1853 slice_num = (mb_w * mb_h + cfg->split_arg - 1) / cfg->split_arg; in setup_vepu510_split()
H A Dhal_h265e_vepu541.c795 RK_S32 mb_w = MPP_ALIGN(w, 64) / 64; in vepu541_h265_set_roi() local
797 RK_S32 ctu_line = mb_w; in vepu541_h265_set_roi()
801 for ( i = 0; i < mb_w; i++) { in vepu541_h265_set_roi()
H A Dhal_h265e_vepu580.c2642 RK_U32 mb_w = MPP_ALIGN(enc_cfg->prep.width, 64) / 64; in vepu580_setup_split() local
2647 mb_w = mb_w / 2; in vepu580_setup_split()
2649 slice_num = (mb_w * mb_h + cfg->split_arg - 1) / cfg->split_arg; in vepu580_setup_split()