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Searched refs:cfg_coeffs (Results 1 – 9 of 9) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu541.c496 const VepuRgb2YuvCfg *cfg_coeffs = get_rgb2yuv_cfg(prep->range, prep->color); in setup_vepu541_prep() local
500 regs->reg018.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu541_prep()
501 regs->reg018.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu541_prep()
502 regs->reg018.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu541_prep()
504 regs->reg019.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu541_prep()
505 regs->reg019.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu541_prep()
506 regs->reg019.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu541_prep()
508 regs->reg020.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; in setup_vepu541_prep()
509 regs->reg020.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in setup_vepu541_prep()
510 regs->reg020.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in setup_vepu541_prep()
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H A Dhal_h264e_vepu540c.c488 const VepuRgb2YuvCfg *cfg_coeffs = get_rgb2yuv_cfg(prep->range, prep->color); in setup_vepu540c_prep() local
492 regs->reg_base.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu540c_prep()
493 regs->reg_base.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu540c_prep()
494 regs->reg_base.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu540c_prep()
496 regs->reg_base.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu540c_prep()
497 regs->reg_base.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu540c_prep()
498 regs->reg_base.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu540c_prep()
500 regs->reg_base.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; in setup_vepu540c_prep()
501 regs->reg_base.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in setup_vepu540c_prep()
502 regs->reg_base.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in setup_vepu540c_prep()
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H A Dhal_h264e_vepu580.c769 const VepuRgb2YuvCfg *cfg_coeffs = get_rgb2yuv_cfg(prep->range, prep->color); in setup_vepu580_prep() local
773 regs->reg_base.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu580_prep()
774 regs->reg_base.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu580_prep()
775 regs->reg_base.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu580_prep()
777 regs->reg_base.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu580_prep()
778 regs->reg_base.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu580_prep()
779 regs->reg_base.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu580_prep()
781 regs->reg_base.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; in setup_vepu580_prep()
782 regs->reg_base.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in setup_vepu580_prep()
783 regs->reg_base.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in setup_vepu580_prep()
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H A Dhal_h264e_vepu510.c785 const VepuRgb2YuvCfg *cfg_coeffs = get_rgb2yuv_cfg(prep->range, prep->color); in setup_vepu510_prep() local
789 reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu510_prep()
790 reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu510_prep()
791 reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu510_prep()
793 reg_frm->common.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu510_prep()
794 reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu510_prep()
795 reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu510_prep()
797 reg_frm->common.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; in setup_vepu510_prep()
798 reg_frm->common.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in setup_vepu510_prep()
799 reg_frm->common.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in setup_vepu510_prep()
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H A Dhal_h264e_vepu511.c762 const VepuRgb2YuvCfg *cfg_coeffs = get_rgb2yuv_cfg(prep->range, prep->color); in setup_vepu511_prep() local
766 reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in setup_vepu511_prep()
767 reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in setup_vepu511_prep()
768 reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in setup_vepu511_prep()
770 reg_frm->common.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu511_prep()
771 reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu511_prep()
772 reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu511_prep()
774 reg_frm->common.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; in setup_vepu511_prep()
775 reg_frm->common.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in setup_vepu511_prep()
776 reg_frm->common.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in setup_vepu511_prep()
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/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu540c.c825 … const VepuRgb2YuvCfg *cfg_coeffs = cfg_coeffs = get_rgb2yuv_cfg(prep_cfg->range, prep_cfg->color); in vepu540c_h265_set_pp_regs() local
829 reg_base->reg0199_src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in vepu540c_h265_set_pp_regs()
830 reg_base->reg0199_src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in vepu540c_h265_set_pp_regs()
831 reg_base->reg0199_src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in vepu540c_h265_set_pp_regs()
833 reg_base->reg0200_src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in vepu540c_h265_set_pp_regs()
834 reg_base->reg0200_src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in vepu540c_h265_set_pp_regs()
835 reg_base->reg0200_src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in vepu540c_h265_set_pp_regs()
837 reg_base->reg0201_src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in vepu540c_h265_set_pp_regs()
838 reg_base->reg0201_src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in vepu540c_h265_set_pp_regs()
839 reg_base->reg0201_src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; in vepu540c_h265_set_pp_regs()
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H A Dhal_h265e_vepu541.c1103 … const VepuRgb2YuvCfg *cfg_coeffs = cfg_coeffs = get_rgb2yuv_cfg(prep_cfg->range, prep_cfg->color); in vepu541_h265_set_pp_regs() local
1107 regs->src_udfy.wght_r2y = cfg_coeffs->_2y.r_coeff; in vepu541_h265_set_pp_regs()
1108 regs->src_udfy.wght_g2y = cfg_coeffs->_2y.g_coeff; in vepu541_h265_set_pp_regs()
1109 regs->src_udfy.wght_b2y = cfg_coeffs->_2y.b_coeff; in vepu541_h265_set_pp_regs()
1111 regs->src_udfu.wght_r2u = cfg_coeffs->_2u.r_coeff; in vepu541_h265_set_pp_regs()
1112 regs->src_udfu.wght_g2u = cfg_coeffs->_2u.g_coeff; in vepu541_h265_set_pp_regs()
1113 regs->src_udfu.wght_b2u = cfg_coeffs->_2u.b_coeff; in vepu541_h265_set_pp_regs()
1115 regs->src_udfv.wght_r2v = cfg_coeffs->_2v.r_coeff; in vepu541_h265_set_pp_regs()
1116 regs->src_udfv.wght_g2v = cfg_coeffs->_2v.g_coeff; in vepu541_h265_set_pp_regs()
1117 regs->src_udfv.wght_b2v = cfg_coeffs->_2v.b_coeff; in vepu541_h265_set_pp_regs()
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H A Dhal_h265e_vepu510.c1471 … const VepuRgb2YuvCfg *cfg_coeffs = cfg_coeffs = get_rgb2yuv_cfg(prep_cfg->range, prep_cfg->color); in vepu510_h265_set_pp_regs() local
1475 reg_frm->common.src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in vepu510_h265_set_pp_regs()
1476 reg_frm->common.src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in vepu510_h265_set_pp_regs()
1477 reg_frm->common.src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in vepu510_h265_set_pp_regs()
1479 reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in vepu510_h265_set_pp_regs()
1480 reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in vepu510_h265_set_pp_regs()
1481 reg_frm->common.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in vepu510_h265_set_pp_regs()
1483 reg_frm->common.src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in vepu510_h265_set_pp_regs()
1484 reg_frm->common.src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in vepu510_h265_set_pp_regs()
1485 reg_frm->common.src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; in vepu510_h265_set_pp_regs()
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H A Dhal_h265e_vepu580.c2035 … const VepuRgb2YuvCfg *cfg_coeffs = cfg_coeffs = get_rgb2yuv_cfg(prep_cfg->range, prep_cfg->color); in vepu580_h265_set_pp_regs() local
2039 reg_base->reg0199_src_udfy.csc_wgt_r2y = cfg_coeffs->_2y.r_coeff; in vepu580_h265_set_pp_regs()
2040 reg_base->reg0199_src_udfy.csc_wgt_g2y = cfg_coeffs->_2y.g_coeff; in vepu580_h265_set_pp_regs()
2041 reg_base->reg0199_src_udfy.csc_wgt_b2y = cfg_coeffs->_2y.b_coeff; in vepu580_h265_set_pp_regs()
2043 reg_base->reg0200_src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in vepu580_h265_set_pp_regs()
2044 reg_base->reg0200_src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in vepu580_h265_set_pp_regs()
2045 reg_base->reg0200_src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in vepu580_h265_set_pp_regs()
2047 reg_base->reg0201_src_udfv.csc_wgt_r2v = cfg_coeffs->_2v.r_coeff; in vepu580_h265_set_pp_regs()
2048 reg_base->reg0201_src_udfv.csc_wgt_g2v = cfg_coeffs->_2v.g_coeff; in vepu580_h265_set_pp_regs()
2049 reg_base->reg0201_src_udfv.csc_wgt_b2v = cfg_coeffs->_2v.b_coeff; in vepu580_h265_set_pp_regs()
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