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Searched refs:_2u (Results 1 – 11 of 11) sorted by relevance

/rockchip-linux_mpp/mpp/hal/rkenc/common/
H A Dvepu5xx_common.c30 ._2u = {.r_coeff = -38, .g_coeff = -74, .b_coeff = 112, .offset = 128},
37 ._2u = {.r_coeff = -26, .g_coeff = -87, .b_coeff = 112, .offset = 128},
47 ._2u = {.r_coeff = -43, .g_coeff = -85, .b_coeff = 128, .offset = 128},
54 ._2u = {.r_coeff = -29, .g_coeff = -99, .b_coeff = 128, .offset = 128},
H A Dvepu5xx_common.h93 VepuRgb2YuvCoeffs _2u; member
/rockchip-linux_mpp/mpp/hal/rkenc/h264e/
H A Dhal_h264e_vepu541.c504 regs->reg019.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu541_prep()
505 regs->reg019.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu541_prep()
506 regs->reg019.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu541_prep()
513 regs->reg021.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu541_prep()
H A Dhal_h264e_vepu540c.c496 regs->reg_base.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu540c_prep()
497 regs->reg_base.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu540c_prep()
498 regs->reg_base.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu540c_prep()
505 regs->reg_base.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu540c_prep()
H A Dhal_h264e_vepu580.c777 regs->reg_base.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu580_prep()
778 regs->reg_base.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu580_prep()
779 regs->reg_base.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu580_prep()
786 regs->reg_base.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu580_prep()
H A Dhal_h264e_vepu510.c793 reg_frm->common.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu510_prep()
794 reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu510_prep()
795 reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu510_prep()
802 reg_frm->common.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu510_prep()
H A Dhal_h264e_vepu511.c770 reg_frm->common.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in setup_vepu511_prep()
771 reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in setup_vepu511_prep()
772 reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in setup_vepu511_prep()
779 reg_frm->common.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in setup_vepu511_prep()
/rockchip-linux_mpp/mpp/hal/rkenc/h265e/
H A Dhal_h265e_vepu540c.c833 reg_base->reg0200_src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in vepu540c_h265_set_pp_regs()
834 reg_base->reg0200_src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in vepu540c_h265_set_pp_regs()
835 reg_base->reg0200_src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in vepu540c_h265_set_pp_regs()
842 reg_base->reg0202_src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in vepu540c_h265_set_pp_regs()
H A Dhal_h265e_vepu541.c1111 regs->src_udfu.wght_r2u = cfg_coeffs->_2u.r_coeff; in vepu541_h265_set_pp_regs()
1112 regs->src_udfu.wght_g2u = cfg_coeffs->_2u.g_coeff; in vepu541_h265_set_pp_regs()
1113 regs->src_udfu.wght_b2u = cfg_coeffs->_2u.b_coeff; in vepu541_h265_set_pp_regs()
1120 regs->src_udfo.ofst_u = cfg_coeffs->_2u.offset; in vepu541_h265_set_pp_regs()
H A Dhal_h265e_vepu510.c1479 reg_frm->common.src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in vepu510_h265_set_pp_regs()
1480 reg_frm->common.src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in vepu510_h265_set_pp_regs()
1481 reg_frm->common.src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in vepu510_h265_set_pp_regs()
1488 reg_frm->common.src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in vepu510_h265_set_pp_regs()
H A Dhal_h265e_vepu580.c2043 reg_base->reg0200_src_udfu.csc_wgt_r2u = cfg_coeffs->_2u.r_coeff; in vepu580_h265_set_pp_regs()
2044 reg_base->reg0200_src_udfu.csc_wgt_g2u = cfg_coeffs->_2u.g_coeff; in vepu580_h265_set_pp_regs()
2045 reg_base->reg0200_src_udfu.csc_wgt_b2u = cfg_coeffs->_2u.b_coeff; in vepu580_h265_set_pp_regs()
2052 reg_base->reg0202_src_udfo.csc_ofst_u = cfg_coeffs->_2u.offset; in vepu580_h265_set_pp_regs()