| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | rockchip_rgb.c | 74 void (*prepare)(struct rockchip_rgb *rgb, int pipe); 75 void (*unprepare)(struct rockchip_rgb *rgb); 158 struct rockchip_rgb *rgb = dev_get_priv(conn->dev); in rockchip_rgb_connector_prepare() local 163 pinctrl_select_state(rgb->dev, "default"); in rockchip_rgb_connector_prepare() 165 if (rgb->funcs && rgb->funcs->prepare) in rockchip_rgb_connector_prepare() 166 rgb->funcs->prepare(rgb, pipe); in rockchip_rgb_connector_prepare() 168 if (rgb->phy) { in rockchip_rgb_connector_prepare() 169 ret = rockchip_phy_set_mode(rgb->phy, PHY_MODE_VIDEO_TTL); in rockchip_rgb_connector_prepare() 171 dev_err(rgb->dev, "failed to set phy mode: %d\n", ret); in rockchip_rgb_connector_prepare() 175 rockchip_phy_power_on(rgb->phy); in rockchip_rgb_connector_prepare() [all …]
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| /rk3399_rockchip-uboot/drivers/video/drm/rk628/ |
| H A D | rk628_rgb.c | 18 rk628->rgb.bt1120_dual_edge = true; in rk628_rgbrx_parse() 23 rk628->rgb.bt1120_yc_swap = true; in rk628_rgbrx_parse() 26 rk628->rgb.bt1120_uv_swap = true; in rk628_rgbrx_parse() 39 "vccio-rgb", &rk628->rgb.vccio_rgb); in rk628_rgbtx_parse() 99 if (rk628->rgb.vccio_rgb) in rk628_rgb_encoder_enable() 100 voltage = regulator_get_value(rk628->rgb.vccio_rgb); in rk628_rgb_encoder_enable() 252 if (rk628->rgb.bt1120_dual_edge) { in rk628_bt1120_decoder_enable() 281 (rk628->rgb.bt1120_yc_swap ? SW_BT1120_YC_SWAP : 0) | in rk628_bt1120_decoder_enable() 282 (rk628->rgb.bt1120_uv_swap ? SW_BT1120_UV_SWAP : 0)); in rk628_bt1120_decoder_enable() 315 if (rk628->rgb.vccio_rgb) in rk628_bt1120_encoder_enable() [all …]
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| /rk3399_rockchip-uboot/drivers/video/ |
| H A D | tegra.c | 343 int rgb; in tegra_lcd_ofdata_to_platdata() local 352 rgb = fdt_subnode_offset(blob, node, "rgb"); in tegra_lcd_ofdata_to_platdata() 353 if (rgb < 0) { in tegra_lcd_ofdata_to_platdata() 355 __func__, dev->name, rgb); in tegra_lcd_ofdata_to_platdata() 359 ret = fdtdec_decode_display_timing(blob, rgb, 0, &priv->timing); in tegra_lcd_ofdata_to_platdata() 375 panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel"); in tegra_lcd_ofdata_to_platdata() 396 int rgb; in tegra_lcd_bind() local 398 rgb = fdt_subnode_offset(blob, node, "rgb"); in tegra_lcd_bind() 399 if ((rgb < 0) || !fdtdec_get_is_enabled(blob, rgb)) in tegra_lcd_bind()
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/video/ |
| H A D | tegra20-dc.txt | 14 Required subnode 'rgb' is as follows: 16 Required properties (rgb) : 59 rgb {
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| H A D | exynos-fb.txt | 53 samsung,rgb-mode: 0(MODE_RGB_P), 1(MODE_BGR_P),
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| /rk3399_rockchip-uboot/arch/arm/dts/ |
| H A D | sama5d3_lcd.dtsi | 59 pinctrl_lcd_rgb444: lcd-rgb-0 { 75 pinctrl_lcd_rgb565: lcd-rgb-1 { 95 pinctrl_lcd_rgb666: lcd-rgb-2 { 117 pinctrl_lcd_rgb666_alt: lcd-rgb-2-alt { 139 pinctrl_lcd_rgb888: lcd-rgb-3 { 167 pinctrl_lcd_rgb888_alt: lcd-rgb-3-alt {
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| H A D | at91sam9x5_lcd.dtsi | 40 pinctrl_lcd_rgb444: lcd-rgb-0 { 56 pinctrl_lcd_rgb565: lcd-rgb-1 { 76 pinctrl_lcd_rgb666: lcd-rgb-2 { 98 pinctrl_lcd_rgb888: lcd-rgb-3 {
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| H A D | rk3326.dtsi | 8 &rgb { 18 lcdc_m1_rgb_pins: lcdc-m1-rgb-pins {
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| H A D | rk3308-evb.dts | 134 rockchip,output = "rgb"; 135 rgb-mode = "p666"; 204 01 00 01 32 /* 02 mcu, 32 rgb */ 368 &rgb {
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| H A D | tegra20-medcom-wide.dts | 28 rgb {
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| H A D | tegra20-tec.dts | 28 rgb {
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| H A D | tegra20-colibri.dts | 25 rgb {
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| H A D | rk1808.dtsi | 136 rgb: rgb { label 137 compatible = "rockchip,rk1808-rgb"; 1514 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1520 lcdc_rgb_den_pin: lcdc-rgb-den-pin { 1526 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1532 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1538 lcdc_rgb_m1_hsync_pin: lcdc-rgb-m1-hsync-pin { 1544 lcdc_rgb_m1_vsync_pin: lcdc-rgb-m1-vsync-pin {
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| H A D | rk3128.dtsi | 629 rgb: rgb { label 630 compatible = "rockchip,rk3128-rgb"; 815 lcdc_rgb_pins: lcdc-rgb-pins {
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| H A D | rk3308.dtsi | 88 route_rgb: route-rgb { 341 rgb: rgb { label 342 compatible = "rockchip,rk3308-rgb";
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| H A D | exynos4210-universal_c210.dts | 72 samsung,rgb-mode = <0>;
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| H A D | exynos4210-trats.dts | 61 samsung,rgb-mode = <0>;
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| H A D | sama5d4.dtsi | 1560 pinctrl_lcd_rgb444: lcd-rgb-0 { 1575 pinctrl_lcd_rgb565: lcd-rgb-1 { 1594 pinctrl_lcd_rgb666: lcd-rgb-2 { 1615 pinctrl_lcd_rgb777: lcd-rgb-3 { 1642 pinctrl_lcd_rgb888: lcd-rgb-4 {
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| H A D | tegra20.dtsi | 91 rgb { 108 rgb {
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| H A D | tegra114.dtsi | 58 rgb { 77 rgb {
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| H A D | rk3506.dtsi | 300 route_rgb: route-rgb { 637 rgb: rgb { label 638 compatible = "rockchip,rk3506-rgb";
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| H A D | rv1106.dtsi | 270 rgb: rgb { label 271 compatible = "rockchip,rv1106-rgb";
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| /rk3399_rockchip-uboot/include/ |
| H A D | ec_commands.h | 835 struct rgb { struct 837 } rgb; member 861 } off, on, init, brightness, seq, reg, rgb, demo, set_params; member
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/gpu/ |
| H A D | nvidia,tegra20-host1x.txt | 125 Each display controller node has a child node, named "rgb", that represents 319 rgb { 334 rgb {
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| /rk3399_rockchip-uboot/board/boundary/nitrogen6x/ |
| H A D | README | 54 wvga-rgb - 800 x 480 RGB (Boundary p/n Nit6X_800x480)
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