xref: /rk3399_rockchip-uboot/arch/arm/dts/tegra20-colibri.dts (revision 336aee50cf55d4d98ddf3a4412c18286e7f0a4c0)
1e57c6e5bSMarcel Ziswiler/dts-v1/;
2e57c6e5bSMarcel Ziswiler
3e57c6e5bSMarcel Ziswiler#include "tegra20.dtsi"
4e57c6e5bSMarcel Ziswiler
5e57c6e5bSMarcel Ziswiler/ {
6e57c6e5bSMarcel Ziswiler	model = "Toradex Colibri T20";
7a7841e7dSMarcel Ziswiler	compatible = "toradex,colibri_t20", "nvidia,tegra20";
8e57c6e5bSMarcel Ziswiler
9e57c6e5bSMarcel Ziswiler	chosen {
10e57c6e5bSMarcel Ziswiler		stdout-path = &uarta;
11e57c6e5bSMarcel Ziswiler	};
12e57c6e5bSMarcel Ziswiler
13e57c6e5bSMarcel Ziswiler	aliases {
14c1faf002SMarcel Ziswiler		i2c0 = "/i2c@7000d000";
15c1faf002SMarcel Ziswiler		i2c1 = "/i2c@7000c000";
16c1faf002SMarcel Ziswiler		i2c2 = "/i2c@7000c400";
1767748a73SStephen Warren		mmc0 = "/sdhci@c8000600";
18d5a24d8bSMarcel Ziswiler		usb0 = "/usb@c5000000";
193f33bd29SMarcel Ziswiler		usb1 = "/usb@c5004000"; /* On-module only, for ASIX */
20d5a24d8bSMarcel Ziswiler		usb2 = "/usb@c5008000";
21e57c6e5bSMarcel Ziswiler	};
22e57c6e5bSMarcel Ziswiler
23ee7d755aSSimon Glass	host1x@50000000 {
24b2ea19b5SMarcel Ziswiler		dc@54200000 {
25b2ea19b5SMarcel Ziswiler			rgb {
26b2ea19b5SMarcel Ziswiler				status = "okay";
27b2ea19b5SMarcel Ziswiler				nvidia,panel = <&lcd_panel>;
2828f224a5SMarcel Ziswiler				display-timings {
2928f224a5SMarcel Ziswiler					timing@0 {
3028f224a5SMarcel Ziswiler						/* VESA VGA */
3128f224a5SMarcel Ziswiler						clock-frequency = <25175000>;
3228f224a5SMarcel Ziswiler						hactive = <640>;
3328f224a5SMarcel Ziswiler						vactive = <480>;
3428f224a5SMarcel Ziswiler						hback-porch = <48>;
3528f224a5SMarcel Ziswiler						hfront-porch = <16>;
3628f224a5SMarcel Ziswiler						hsync-len = <96>;
3728f224a5SMarcel Ziswiler						vback-porch = <31>;
3828f224a5SMarcel Ziswiler						vfront-porch = <11>;
3928f224a5SMarcel Ziswiler						vsync-len = <2>;
4028f224a5SMarcel Ziswiler					};
4128f224a5SMarcel Ziswiler				};
42b2ea19b5SMarcel Ziswiler			};
43b2ea19b5SMarcel Ziswiler		};
44b2ea19b5SMarcel Ziswiler	};
45b2ea19b5SMarcel Ziswiler
46e57c6e5bSMarcel Ziswiler	nand-controller@70008000 {
47e57c6e5bSMarcel Ziswiler		nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
48e57c6e5bSMarcel Ziswiler		nvidia,width = <8>;
49e57c6e5bSMarcel Ziswiler		nvidia,timing = <15 100 25 80 25 10 15 10 100>;
50e57c6e5bSMarcel Ziswiler
51e57c6e5bSMarcel Ziswiler		nand@0 {
52e57c6e5bSMarcel Ziswiler			reg = <0>;
53e57c6e5bSMarcel Ziswiler			compatible = "nand-flash";
54e57c6e5bSMarcel Ziswiler		};
55e57c6e5bSMarcel Ziswiler	};
56e57c6e5bSMarcel Ziswiler
5728f224a5SMarcel Ziswiler	pwm@7000a000 {
5828f224a5SMarcel Ziswiler		status = "okay";
5928f224a5SMarcel Ziswiler	};
6028f224a5SMarcel Ziswiler
61c1faf002SMarcel Ziswiler	/*
62c1faf002SMarcel Ziswiler	 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
63c1faf002SMarcel Ziswiler	 * board)
64c1faf002SMarcel Ziswiler	 */
65c1faf002SMarcel Ziswiler	i2c@7000c000 {
66c1faf002SMarcel Ziswiler		status = "okay";
67*33848eb5SMarcel Ziswiler		clock-frequency = <400000>;
68c1faf002SMarcel Ziswiler	};
69c1faf002SMarcel Ziswiler
70c1faf002SMarcel Ziswiler	/* GEN2_I2C: unused */
71c1faf002SMarcel Ziswiler
72c1faf002SMarcel Ziswiler	/* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
73c1faf002SMarcel Ziswiler	i2c@7000c400 {
74c1faf002SMarcel Ziswiler		status = "okay";
75*33848eb5SMarcel Ziswiler		clock-frequency = <10000>;
76c1faf002SMarcel Ziswiler	};
77c1faf002SMarcel Ziswiler
78c1faf002SMarcel Ziswiler	/*
79c1faf002SMarcel Ziswiler	 * PWR_I2C: power I2C to PMIC and temperature sensor
80c1faf002SMarcel Ziswiler	 */
81c1faf002SMarcel Ziswiler	i2c@7000d000 {
82c1faf002SMarcel Ziswiler		status = "okay";
83c1faf002SMarcel Ziswiler		clock-frequency = <100000>;
84c1faf002SMarcel Ziswiler	};
85c1faf002SMarcel Ziswiler
86d5a24d8bSMarcel Ziswiler	/* EHCI instance 0: USB1_DP/N -> USBC_P/N */
87d5a24d8bSMarcel Ziswiler	usb@c5000000 {
88d5a24d8bSMarcel Ziswiler		status = "okay";
89d5a24d8bSMarcel Ziswiler		dr_mode = "otg";
90d5a24d8bSMarcel Ziswiler	};
91d5a24d8bSMarcel Ziswiler
92d5a24d8bSMarcel Ziswiler	/* EHCI instance 1: ULPI -> USB3340 -> AX88772B */
93d5a24d8bSMarcel Ziswiler	usb@c5004000 {
94d5a24d8bSMarcel Ziswiler		status = "okay";
953f33bd29SMarcel Ziswiler		/* ULPI_RESET */
963f33bd29SMarcel Ziswiler		nvidia,phy-reset-gpio =
973f33bd29SMarcel Ziswiler				<&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
98d5a24d8bSMarcel Ziswiler		/* VBUS_LAN */
99d5a24d8bSMarcel Ziswiler		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
100d5a24d8bSMarcel Ziswiler	};
101d5a24d8bSMarcel Ziswiler
102d5a24d8bSMarcel Ziswiler	/* EHCI instance 2: USB3_DP/N -> USBH_P/N */
103d5a24d8bSMarcel Ziswiler	usb@c5008000 {
104d5a24d8bSMarcel Ziswiler		status = "okay";
105d5a24d8bSMarcel Ziswiler		/* USBH_PEN */
106d5a24d8bSMarcel Ziswiler		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
107d5a24d8bSMarcel Ziswiler	};
108d5a24d8bSMarcel Ziswiler
109e57c6e5bSMarcel Ziswiler	sdhci@c8000600 {
110e57c6e5bSMarcel Ziswiler		status = "okay";
111e57c6e5bSMarcel Ziswiler		bus-width = <4>;
11236a01bddSMarcel Ziswiler		cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
113e57c6e5bSMarcel Ziswiler	};
114b2ea19b5SMarcel Ziswiler
11528f224a5SMarcel Ziswiler	backlight: backlight {
11628f224a5SMarcel Ziswiler		compatible = "pwm-backlight";
11728f224a5SMarcel Ziswiler
11828f224a5SMarcel Ziswiler		brightness-levels = <255 128 64 32 16 8 4 0>;
11928f224a5SMarcel Ziswiler		default-brightness-level = <6>;
12028f224a5SMarcel Ziswiler		/* BL_ON */
12128f224a5SMarcel Ziswiler		enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>;
12228f224a5SMarcel Ziswiler		power-supply = <&reg_3v3>;
12328f224a5SMarcel Ziswiler		/* PWM<A> */
12428f224a5SMarcel Ziswiler		pwms = <&pwm 0 5000000>;
12528f224a5SMarcel Ziswiler	};
12628f224a5SMarcel Ziswiler
127ee7d755aSSimon Glass	clocks {
128ee7d755aSSimon Glass		compatible = "simple-bus";
129ee7d755aSSimon Glass		#address-cells = <1>;
130ee7d755aSSimon Glass		#size-cells = <0>;
131ee7d755aSSimon Glass
132ee7d755aSSimon Glass		clk32k_in: clock@0 {
133ee7d755aSSimon Glass			compatible = "fixed-clock";
134ee7d755aSSimon Glass			reg=<0>;
135ee7d755aSSimon Glass			#clock-cells = <0>;
136ee7d755aSSimon Glass			clock-frequency = <32768>;
137ee7d755aSSimon Glass		};
138ee7d755aSSimon Glass	};
139ee7d755aSSimon Glass
14028f224a5SMarcel Ziswiler	lcd_panel: panel {
14128f224a5SMarcel Ziswiler		/*
14228f224a5SMarcel Ziswiler		 * edt,et057090dhu: EDT 5.7" LCD TFT
14328f224a5SMarcel Ziswiler		 * edt,et070080dh6: EDT 7.0" LCD TFT
14428f224a5SMarcel Ziswiler		 */
14528f224a5SMarcel Ziswiler		compatible = "edt,et057090dhu", "simple-panel";
14628f224a5SMarcel Ziswiler
14728f224a5SMarcel Ziswiler		backlight = <&backlight>;
14891c08afeSSimon Glass	};
14991c08afeSSimon Glass
15028f224a5SMarcel Ziswiler	regulators {
15128f224a5SMarcel Ziswiler		compatible = "simple-bus";
15228f224a5SMarcel Ziswiler		#address-cells = <1>;
15328f224a5SMarcel Ziswiler		#size-cells = <0>;
15428f224a5SMarcel Ziswiler
15528f224a5SMarcel Ziswiler		reg_3v3: regulator@0 {
15628f224a5SMarcel Ziswiler			compatible = "regulator-fixed";
15728f224a5SMarcel Ziswiler			reg = <0>;
15828f224a5SMarcel Ziswiler			regulator-name = "+V3.3";
15928f224a5SMarcel Ziswiler			regulator-min-microvolt = <3300000>;
16028f224a5SMarcel Ziswiler			regulator-max-microvolt = <3300000>;
16128f224a5SMarcel Ziswiler			regulator-always-on;
16228f224a5SMarcel Ziswiler		};
163b2ea19b5SMarcel Ziswiler	};
164e57c6e5bSMarcel Ziswiler};
165f53dcc0eSSimon Glass
166f53dcc0eSSimon Glass&uarta {
167f53dcc0eSSimon Glass	status = "okay";
168f53dcc0eSSimon Glass};
169