| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-sunxi/ |
| H A D | gpio.h | 126 #define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr)) argument
127 #define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr)) argument
128 #define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr)) argument
129 #define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr)) argument
130 #define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr)) argument
131 #define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr)) argument
132 #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) argument
133 #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) argument
134 #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) argument
135 #define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) argument
[all …]
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| /rk3399_rockchip-uboot/drivers/pinctrl/mvebu/ |
| H A D | pinctrl-armada-37xx.c | 101 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \ argument
105 .npins = _nr, \
111 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \ argument
115 .npins = _nr, \
121 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \ argument
125 .npins = _nr, \
131 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \ argument
136 .npins = _nr, \
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3066.c | 95 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
96 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
97 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
98 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
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| H A D | clk_rk3188.c | 93 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
94 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
95 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
96 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
|
| H A D | clk_rk3368.c | 39 #define RK3368_PLL_RATE(_rate, _nr, _nf, _no, _nb) \ argument
42 .nr = _nr, \
106 #define PLL_DIVISORS(hz, _nr, _no) { \ argument
107 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
108 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
109 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
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| H A D | clk_rk3288.c | 42 #define RK3288_PLL_RATE(_rate, _nr, _nf, _no, _nb) \ argument
45 .nr = _nr, \
212 #define PLL_DIVISORS(hz, _nr, _no) {\ argument
213 .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
214 _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
215 (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
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