Searched refs:CAR (Results 1 – 12 of 12) sorted by relevance
43 hex "Board specific Cache-As-RAM (CAR) address"46 This option specifies the board specific Cache-As-RAM (CAR) address.49 hex "Board specific Cache-As-RAM (CAR) size"52 This option specifies the board specific Cache-As-RAM (CAR) size.
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible11 - reg : Should contain CAR registers location and length15 In clock consumers, this cell represents the clock ID exposed by the CAR.17 The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB18 registers. These IDs often match those in the CAR's RST_DEVICES registers,25 The balance of the clocks controlled by the CAR are assigned IDs of 96 and
2 bool "Enable Tegra CAR-based clock driver"6 register access to the Tegra CAR (Clock And Reset controller).
29 Space in bytes in eSRAM used as Cache-As-RAM (CAR).
7 CAR node and the clock number as a parameter:
44 bool "Enable Tegra CAR-based reset driver"48 direct register access to the Tegra CAR (Clock And Reset controller).
377 CAR is disabled.465 start address of the cache-as-RAM (CAR) area and the address varies466 depending on the CPU. Once CAR is set up, read/write memory becomes476 sets the size of the cache-as-RAM (CAR) area. Note that much of the477 CAR space is required by the MRC. The CAR space available to U-Boot485 This is the amount of CAR (Cache as RAM) reserved for use by the
132 Space in bytes in eSRAM used as Cache-As-ARM (CAR).
266 bool "Enable support for the Tegra CAR driver"269 The Tegra CAR (Clock and Reset Controller) is a HW module that
59 (0x01920000) Board specific Cache-As-RAM (CAR) address60 (0x4000) Board specific Cache-As-RAM (CAR) size63 to point to a new board. You can also change the Cache-As-RAM (CAR) related
412 #define CAR 0x40500020 /* CODEC Access Register */ macro
138 ARM RENESAS RMOBILE/R-CAR