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Searched refs:uint64_t (Results 1 – 25 of 754) sorted by relevance

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/rk3399_ARM-atf/plat/qti/qtiseclib/inc/
H A Dqtiseclib_defs.h43 uint64_t x0;
44 uint64_t x1;
45 uint64_t x2;
46 uint64_t x3;
47 uint64_t x4;
48 uint64_t x5;
49 uint64_t x6;
50 uint64_t x7;
51 uint64_t x8;
52 uint64_t x9;
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/rk3399_ARM-atf/bl32/tsp/
H A Dtsp_private.h51 smc_args_t *set_smc_args(uint64_t arg0,
52 uint64_t arg1,
53 uint64_t arg2,
54 uint64_t arg3,
55 uint64_t arg4,
56 uint64_t arg5,
57 uint64_t arg6,
58 uint64_t arg7);
59 smc_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl,
60 uint64_t arg1,
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H A Dtsp_common.c34 smc_args_t *set_smc_args(uint64_t arg0, in set_smc_args()
35 uint64_t arg1, in set_smc_args()
36 uint64_t arg2, in set_smc_args()
37 uint64_t arg3, in set_smc_args()
38 uint64_t arg4, in set_smc_args()
39 uint64_t arg5, in set_smc_args()
40 uint64_t arg6, in set_smc_args()
41 uint64_t arg7) in set_smc_args()
84 smc_args_t *tsp_system_off_main(uint64_t arg0, in tsp_system_off_main()
85 uint64_t arg1, in tsp_system_off_main()
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H A Dtsp_main.c30 uint64_t tsp_main(void) in tsp_main()
57 return (uint64_t) &tsp_vector_table; in tsp_main()
91 smc_args_t *tsp_cpu_off_main(uint64_t arg0, in tsp_cpu_off_main()
92 uint64_t arg1, in tsp_cpu_off_main()
93 uint64_t arg2, in tsp_cpu_off_main()
94 uint64_t arg3, in tsp_cpu_off_main()
95 uint64_t arg4, in tsp_cpu_off_main()
96 uint64_t arg5, in tsp_cpu_off_main()
97 uint64_t arg6, in tsp_cpu_off_main()
98 uint64_t arg7) in tsp_cpu_off_main()
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H A Dtsp_ffa_main.c83 static int ffa_test_relay(uint64_t arg0, in ffa_test_relay()
84 uint64_t arg1, in ffa_test_relay()
85 uint64_t arg2, in ffa_test_relay()
86 uint64_t arg3, in ffa_test_relay()
87 uint64_t arg4, in ffa_test_relay()
88 uint64_t arg5, in ffa_test_relay()
89 uint64_t arg6, in ffa_test_relay()
90 uint64_t arg7) in ffa_test_relay()
107 static int test_memory_send(ffa_endpoint_id16_t sender, uint64_t handle, in test_memory_send()
210 (uint64_t)ptr, in test_memory_send()
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/rk3399_ARM-atf/services/std_svc/rmmd/
H A Drmmd_private.h42 uint64_t c_rt_ctx;
43 uint64_t activation_token;
48 uint64_t rmmd_rmm_sync_entry(rmmd_rmm_context_t *ctx);
49 __dead2 void rmmd_rmm_sync_exit(uint64_t rc);
52 int rmmd_attest_get_platform_token(uint64_t buf_pa, uint64_t *buf_size,
53 uint64_t c_size,
54 uint64_t *remaining_len);
55 int rmmd_attest_get_signing_key(uint64_t buf_pa, uint64_t *buf_size,
56 uint64_t ecc_curve);
57 uint64_t rmmd_el3_token_sign(void *handle, uint64_t x1, uint64_t x2,
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H A Drmmd_keymgmt.c24 bool extract_ide_stream_info(uint64_t ide_stream_info) in extract_ide_stream_info()
46 int rmmd_el3_ide_key_program(uint64_t ecam_address, uint64_t rp_id, in rmmd_el3_ide_key_program()
47 uint64_t ide_stream_info, rp_ide_key_info_t *ide_key_info_ptr, in rmmd_el3_ide_key_program()
48 uint64_t request_id, uint64_t cookie) in rmmd_el3_ide_key_program()
71 int rmmd_el3_ide_key_set_go(uint64_t ecam_address, uint64_t rp_id, in rmmd_el3_ide_key_set_go()
72 uint64_t ide_stream_info, uint64_t request_id, in rmmd_el3_ide_key_set_go()
73 uint64_t cookie) in rmmd_el3_ide_key_set_go()
96 int rmmd_el3_ide_key_set_stop(uint64_t ecam_address, uint64_t rp_id, in rmmd_el3_ide_key_set_stop()
97 uint64_t ide_stream_info, uint64_t request_id, in rmmd_el3_ide_key_set_stop()
98 uint64_t cookie) in rmmd_el3_ide_key_set_stop()
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/rk3399_ARM-atf/plat/arm/board/fvp/
H A Dfvp_ide_keymgmt.c12 int plat_rmmd_el3_ide_key_program(uint64_t ecam_address, uint64_t root_port_id, in plat_rmmd_el3_ide_key_program()
13 uint64_t ide_stream_info, in plat_rmmd_el3_ide_key_program()
14 rp_ide_key_info_t *ide_key_info_ptr, uint64_t request_id, in plat_rmmd_el3_ide_key_program()
15 uint64_t cookie) in plat_rmmd_el3_ide_key_program()
23 int plat_rmmd_el3_ide_key_set_go(uint64_t ecam_address, uint64_t root_port_id, in plat_rmmd_el3_ide_key_set_go()
24 uint64_t ide_stream_info, uint64_t request_id, in plat_rmmd_el3_ide_key_set_go()
25 uint64_t cookie) in plat_rmmd_el3_ide_key_set_go()
33 int plat_rmmd_el3_ide_key_set_stop(uint64_t ecam_address, uint64_t root_port_id, in plat_rmmd_el3_ide_key_set_stop()
34 uint64_t ide_stream_info, uint64_t request_id, in plat_rmmd_el3_ide_key_set_stop()
35 uint64_t cookie) in plat_rmmd_el3_ide_key_set_stop()
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/rk3399_ARM-atf/include/lib/el3_runtime/
H A Dcontext_el2.h20 uint64_t actlr_el2;
21 uint64_t afsr0_el2;
22 uint64_t afsr1_el2;
23 uint64_t amair_el2;
24 uint64_t cnthctl_el2;
25 uint64_t cntvoff_el2;
26 uint64_t cptr_el2;
27 uint64_t dbgvcr32_el2;
28 uint64_t elr_el2;
29 uint64_t esr_el2;
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H A Dcontext_el1.h21 uint64_t spsr_el1;
22 uint64_t elr_el1;
25 uint64_t sctlr_el1;
26 uint64_t tcr_el1;
29 uint64_t cpacr_el1;
30 uint64_t csselr_el1;
31 uint64_t sp_el1;
32 uint64_t esr_el1;
33 uint64_t mair_el1;
34 uint64_t amair_el1;
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/rk3399_ARM-atf/include/services/
H A Dspmd_svc.h15 uint64_t spmd_ffa_smc_handler(uint32_t smc_fid,
16 uint64_t x1,
17 uint64_t x2,
18 uint64_t x3,
19 uint64_t x4,
22 uint64_t flags);
23 uint64_t spmd_smc_handler(uint32_t smc_fid,
24 uint64_t x1,
25 uint64_t x2,
26 uint64_t x3,
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H A Dspm_mm_partition.h26 uint64_t mpidr;
33 uint64_t sp_mem_base;
34 uint64_t sp_mem_limit;
35 uint64_t sp_image_base;
36 uint64_t sp_stack_base;
37 uint64_t sp_heap_base;
38 uint64_t sp_ns_comm_buf_base;
39 uint64_t sp_shared_buf_base;
40 uint64_t sp_image_size;
41 uint64_t sp_pcpu_stack_size;
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H A Del3_spmd_logical_sp.h28 uint64_t func;
29 uint64_t arg1;
30 uint64_t arg2;
31 uint64_t arg3;
32 uint64_t arg4;
33 uint64_t arg5;
34 uint64_t arg6;
35 uint64_t arg7;
36 uint64_t arg8;
37 uint64_t arg9;
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H A Dspm_mm_svc.h115 uint64_t spm_mm_smc_handler(uint32_t smc_fid,
116 uint64_t x1,
117 uint64_t x2,
118 uint64_t x3,
119 uint64_t x4,
122 uint64_t flags);
125 uint64_t spm_mm_sp_call(uint32_t smc_fid,
126 uint64_t x1,
127 uint64_t x2,
128 uint64_t x3);
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/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/drivers/mce/
H A Dnvg.c29 uint64_t nvg_get_version(void) in nvg_get_version()
31 nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_VERSION); in nvg_get_version()
33 return (uint64_t)nvg_get_result(); in nvg_get_version()
45 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time); in nvg_set_wake_time()
64 uint64_t val = 0; in nvg_update_cstate_info()
68 val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) | in nvg_update_cstate_info()
74 val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | in nvg_update_cstate_info()
80 val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | in nvg_update_cstate_info()
90 val |= ((uint64_t)wake_mask & CSTATE_WAKE_MASK_CLEAR) << CSTATE_WAKE_MASK_SHIFT; in nvg_update_cstate_info()
93 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val); in nvg_update_cstate_info()
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/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dzynqmp_pm_svc_main.c112 static uint64_t ttc_fiq_handler(uint32_t id, uint32_t flags, void *handle, in ttc_fiq_handler()
147 static uint64_t __unused __dead2 zynqmp_sgi7_irq(uint32_t id, uint32_t flags, in zynqmp_sgi7_irq()
285 uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, in pm_smc_handler()
286 uint64_t x4, const void *cookie, void *handle, uint64_t flags) in pm_smc_handler()
327 SMC_RET1(handle, (uint64_t)ret); in pm_smc_handler()
332 SMC_RET1(handle, (uint64_t)ret); in pm_smc_handler()
338 uint64_t address = (uint64_t)pm_arg[2] << 32U; in pm_smc_handler()
340 address |= (uint64_t)(pm_arg[1] & (~0x1U)); in pm_smc_handler()
343 SMC_RET1(handle, (uint64_t)ret); in pm_smc_handler()
348 SMC_RET1(handle, (uint64_t)ret); in pm_smc_handler()
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/rk3399_ARM-atf/include/services/trp/
H A Dtrp_helpers.h32 uint64_t regs[TRP_ARGS_END >> 3];
35 trp_args_t *set_smc_args(uint64_t arg0,
36 uint64_t arg1,
37 uint64_t arg2,
38 uint64_t arg3,
39 uint64_t arg4,
40 uint64_t arg5,
41 uint64_t arg6,
42 uint64_t arg7,
43 uint64_t arg8,
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/rk3399_ARM-atf/services/std_svc/drtm/
H A Ddrtm_main.h72 uint64_t tpm_features;
73 uint64_t minimum_memory_requirement;
74 uint64_t dma_prot_features;
75 uint64_t boot_pe_id;
76 uint64_t tcb_hash_features;
77 uint64_t dlme_image_auth_features;
84 uint64_t dlme_paddr;
85 uint64_t dlme_size;
86 uint64_t dlme_img_off;
87 uint64_t dlme_img_ep_off;
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/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dp/
H A Dcdn_dp.c27 static uint64_t *hdcp_key_pdata;
32 uint64_t dp_hdcp_ctrl(uint64_t type) in dp_hdcp_ctrl()
37 hdcp_key_pdata = (uint64_t *)&key; in dp_hdcp_ctrl()
40 if (hdcp_key_pdata == (uint64_t *)(&key + 1)) in dp_hdcp_ctrl()
50 uint64_t dp_hdcp_store_key(uint64_t x1, in dp_hdcp_store_key()
51 uint64_t x2, in dp_hdcp_store_key()
52 uint64_t x3, in dp_hdcp_store_key()
53 uint64_t x4, in dp_hdcp_store_key()
54 uint64_t x5, in dp_hdcp_store_key()
55 uint64_t x6) in dp_hdcp_store_key()
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/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/mce/
H A Dnvg.c22 uint64_t val = 0ULL; in nvg_enter_cstate()
33 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, wake_time); in nvg_enter_cstate()
37 write_actlr_el1(val | (uint64_t)state); in nvg_enter_cstate()
51 uint64_t val = 0ULL; in nvg_update_cstate_info()
57 val |= ((uint64_t)cluster & CLUSTER_CSTATE_MASK) | in nvg_update_cstate_info()
63 val |= (((uint64_t)ccplex & CCPLEX_CSTATE_MASK) << CCPLEX_CSTATE_SHIFT) | in nvg_update_cstate_info()
69 val |= (((uint64_t)system & SYSTEM_CSTATE_MASK) << SYSTEM_CSTATE_SHIFT) | in nvg_update_cstate_info()
70 (((uint64_t)sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) | in nvg_update_cstate_info()
81 val |= ((uint64_t)wake_mask << CSTATE_WAKE_MASK_SHIFT); in nvg_update_cstate_info()
84 nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val); in nvg_update_cstate_info()
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/rk3399_ARM-atf/services/std_svc/rmmd/trp/
H A Dtrp_helpers.c21 trp_args_t *set_smc_args(uint64_t arg0, in set_smc_args()
22 uint64_t arg1, in set_smc_args()
23 uint64_t arg2, in set_smc_args()
24 uint64_t arg3, in set_smc_args()
25 uint64_t arg4, in set_smc_args()
26 uint64_t arg5, in set_smc_args()
27 uint64_t arg6, in set_smc_args()
28 uint64_t arg7, in set_smc_args()
29 uint64_t arg8, in set_smc_args()
30 uint64_t arg9, in set_smc_args()
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/rk3399_ARM-atf/include/plat/common/
H A Dplat_drtm.h24 uint64_t region_address;
25 uint64_t region_size_type;
49 uint64_t plat_drtm_dma_prot_get_max_table_bytes(void);
58 uint64_t plat_drtm_get_min_size_normal_world_dce(void);
59 uint64_t plat_drtm_get_tcb_hash_table_size(void);
60 uint64_t plat_drtm_get_imp_def_dlme_region_size(void);
61 uint64_t plat_drtm_get_tcb_hash_features(void);
62 uint64_t plat_drtm_get_acpi_tables_region_size(void);
63 uint64_t plat_drtm_get_dlme_img_auth_features(void);
66 int plat_set_drtm_error(uint64_t error_code);
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/rk3399_ARM-atf/drivers/arm/gic/v3/
H A Dgic600ae_fmu_helpers.c50 uint64_t status; in wait_until_fmu_is_idle()
94 uint64_t gic_fmu_read_errfr(uintptr_t base, unsigned int n) in gic_fmu_read_errfr()
100 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRFR_LO + n * 64U); in gic_fmu_read_errfr()
102 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRFR_HI + n * 64U) << 32); in gic_fmu_read_errfr()
110 uint64_t gic_fmu_read_errctlr(uintptr_t base, unsigned int n) in gic_fmu_read_errctlr()
116 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRCTLR_LO + n * 64U); in gic_fmu_read_errctlr()
118 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRCTLR_HI + n * 64U) << 32); in gic_fmu_read_errctlr()
126 uint64_t gic_fmu_read_errstatus(uintptr_t base, unsigned int n) in gic_fmu_read_errstatus()
132 uint64_t reg_val = (uint64_t)mmio_read_32(base + GICFMU_ERRSTATUS_LO + n * 64U); in gic_fmu_read_errstatus()
134 reg_val |= ((uint64_t)mmio_read_32(base + GICFMU_ERRSTATUS_HI + n * 64U) << 32); in gic_fmu_read_errstatus()
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/rk3399_ARM-atf/plat/xilinx/common/
H A Dipi.c115 uint64_t idr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_IDR_OFFSET); in ipi_mb_open()
116 uint64_t isr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_ISR_OFFSET); in ipi_mb_open()
132 uint64_t idr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_IDR_OFFSET); in ipi_mb_release()
150 uint64_t obr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_OBR_OFFSET); in ipi_mb_enquire_status()
151 uint64_t isr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_ISR_OFFSET); in ipi_mb_enquire_status()
177 uint64_t trig_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_TRIG_OFFSET); in ipi_mb_notify()
178 uint64_t obr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_OBR_OFFSET); in ipi_mb_notify()
199 uint64_t isr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_ISR_OFFSET); in ipi_mb_ack()
215 uint64_t idr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_IDR_OFFSET); in ipi_mb_disable_irq()
231 uint64_t ier_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_IER_OFFSET); in ipi_mb_enable_irq()
/rk3399_ARM-atf/services/std_svc/spm/el3_spmc/
H A Dspmc_shared_mem.h26 uint64_t handle;
46 uint64_t next_handle;
59 uint64_t total_length,
61 uint64_t address,
65 uint64_t flags);
69 uint64_t handle_low,
70 uint64_t handle_high,
75 uint64_t flags);
81 uint64_t address,
85 uint64_t flags);
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