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67c23966 |
| 23-Jul-2025 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(el3-spmc): fixed x8-x17 register handling for FFA 1.2" into integration
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| #
bb9fc8c0 |
| 05-Feb-2025 |
Jay Monkman <jmonkman@google.com> |
fix(el3-spmc): fixed x8-x17 register handling for FFA 1.2
Changed spmd_smc_switch_state to return all 18 registers for 64 bit calls, and set x8-17 to zero if necessary.
BREAKING CHANGE: Zeroes or f
fix(el3-spmc): fixed x8-x17 register handling for FFA 1.2
Changed spmd_smc_switch_state to return all 18 registers for 64 bit calls, and set x8-17 to zero if necessary.
BREAKING CHANGE: Zeroes or forwards a different set of registers, depending on the FF-A version of the source and destination. E.g. a call from a v1.1 caller to a v1.2 destination will zero out the extended registers, which is different from the old behavior of forwarding everything to EL2 SPMC, but only x0-x7 to the EL3 SPMC.
Change-Id: Ic31755af0fbb117b0ed74565fba9decebab353c4 Signed-off-by: Jay Monkman <jmonkman@google.com> Signed-off-by: Andrei Homescu <ahomescu@google.com>
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| #
4da4a1a6 |
| 07-Feb-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "od/sme" into integration
* changes: fix(fvp): permit enabling SME for SPD=spmd feat(spmd): pass SMCCCv1.3 SVE hint to lower EL
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| #
c925867e |
| 31-Oct-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
feat(spmd): pass SMCCCv1.3 SVE hint to lower EL
A normal world caller can emit an SMC with the SVE hint bit set such that the callee can perform an optimization by omitting to save/restore the SVE c
feat(spmd): pass SMCCCv1.3 SVE hint to lower EL
A normal world caller can emit an SMC with the SVE hint bit set such that the callee can perform an optimization by omitting to save/restore the SVE context. Update the SPMD to pass this information to the SPMC when set by the caller in the SMC flags parameter. For now, restrict this behavior to the SPMC living at S-EL2.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Icf46eb8a391dd3ddd2ee6aff8581a2f1c8a1c274
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| #
65b13bac |
| 22-Apr-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "ffa_el3_spmc" into integration
* changes: feat(spmc): add support for direct req/resp feat(spmc): add support for handling FFA_ERROR ABI feat(spmc): add support for F
Merge changes from topic "ffa_el3_spmc" into integration
* changes: feat(spmc): add support for direct req/resp feat(spmc): add support for handling FFA_ERROR ABI feat(spmc): add support for FFA_MSG_WAIT feat(spmc): add function to determine the return path from the SPMC feat(spmd): enable handling of FF-A SMCs with the SPMC at EL3 feat(spmd): update SPMC init flow to use EL3 implementation feat(spmc): add FF-A secure partition manager core feat(spmc): prevent read only xlat tables with the EL3 SPMC feat(spmc): enable building of the SPMC at EL3 refactor(spm_mm): reorganize secure partition manager code
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| #
bb01a673 |
| 29-Nov-2021 |
Marc Bonnici <marc.bonnici@arm.com> |
feat(spmd): enable handling of FF-A SMCs with the SPMC at EL3
Any FF-A SMC that arrives from the normal world is handled by the SPMD before being forwarded to the SPMC. Similarly any SMC arriving fr
feat(spmd): enable handling of FF-A SMCs with the SPMC at EL3
Any FF-A SMC that arrives from the normal world is handled by the SPMD before being forwarded to the SPMC. Similarly any SMC arriving from the secure world will hit the SPMC first and be forwarded to the SPMD if required, otherwise the SPMC will respond directly.
This allows for the existing flow of handling FF-A ABI's when the SPMC resides at a lower EL to be preserved.
In order to facilitate this flow the spmd_smc_forward function has been split and control is either passed to the SPMC or it is forwarded as before. To allow this the flags and cookie parameters must now also be passed into this method as the SPMC must be able to provide these when calling back into the SPMD handler as appropriate.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com> Change-Id: I84fee8390023295b9689067e14cd25cba23ca39b
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| #
4b0695ac |
| 26-May-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "SPCI is now called PSA FF-A" into integration
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| #
662af36d |
| 07-May-2020 |
J-Alves <joao.alves@arm.com> |
SPCI is now called PSA FF-A
SPCI is renamed as PSA FF-A which stands for Platform Security Architecture Firmware Framework for A class processors. This patch replaces the occurrence of SPCI with PSA
SPCI is now called PSA FF-A
SPCI is renamed as PSA FF-A which stands for Platform Security Architecture Firmware Framework for A class processors. This patch replaces the occurrence of SPCI with PSA FF-A(in documents) or simply FFA(in code).
Change-Id: I4ab10adb9ffeef1ff784641dfafd99f515133760 Signed-off-by: J-Alves <joao.alves@arm.com>
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| #
d95f7a72 |
| 06-Mar-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "spmd-sel2" into integration
* changes: SPMD: add command line parameter to run SPM at S-EL2 or S-EL1 SPMD: smc handler qualify secure origin using booleans SPMD: SPMC
Merge changes from topic "spmd-sel2" into integration
* changes: SPMD: add command line parameter to run SPM at S-EL2 or S-EL1 SPMD: smc handler qualify secure origin using booleans SPMD: SPMC init, SMC handler cosmetic changes SPMD: [tegra] rename el1_sys_regs structure to sys_regs SPMD: Adds partially supported EL2 registers. SPMD: save/restore EL2 system registers.
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| #
0f14d02f |
| 27-Feb-2020 |
Max Shvetsov <maksims.svecovs@arm.com> |
SPMD: SPMC init, SMC handler cosmetic changes
Change-Id: I8881d489994aea667e3dd59932ab4123f511d6ba Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Signed-off-by: Max Shvetsov <maksims.s
SPMD: SPMC init, SMC handler cosmetic changes
Change-Id: I8881d489994aea667e3dd59932ab4123f511d6ba Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
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| #
63aa4094 |
| 11-Feb-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "spmd" into integration
* changes: SPMD: enable SPM dispatcher support SPMD: hook SPMD into standard services framework SPMD: add SPM dispatcher based upon SPCI Beta 0
Merge changes from topic "spmd" into integration
* changes: SPMD: enable SPM dispatcher support SPMD: hook SPMD into standard services framework SPMD: add SPM dispatcher based upon SPCI Beta 0 spec SPMD: add support to run BL32 in TDRAM and BL31 in secure DRAM on Arm FVP SPMD: add support for an example SPM core manifest SPMD: add SPCI Beta 0 specification header file
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| #
bdd2596d |
| 11-Oct-2019 |
Achin Gupta <achin.gupta@arm.com> |
SPMD: add SPM dispatcher based upon SPCI Beta 0 spec
This patch adds a rudimentary SPM dispatcher component in EL3. It does the following:
- Consumes the TOS_FW_CONFIG to determine properties of th
SPMD: add SPM dispatcher based upon SPCI Beta 0 spec
This patch adds a rudimentary SPM dispatcher component in EL3. It does the following:
- Consumes the TOS_FW_CONFIG to determine properties of the SPM core component - Initialises the SPM core component which resides in the BL32 image - Implements a handler for SPCI calls from either security state. Some basic validation is done for each call but in most cases it is simply forwarded as-is to the "other" security state.
Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Change-Id: I7d116814557f7255f4f4ebb797d1619d4fbab590
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