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Searched refs:reset (Results 1 – 25 of 85) sorted by relevance

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/rk3399_ARM-atf/plat/brcm/board/common/
H A Dplatform_common.c70 void __dead2 plat_soft_reset(uint32_t reset) in plat_soft_reset() argument
72 if (reset == SOFT_RESET_L3) { in plat_soft_reset()
73 mmio_setbits_32(CRMU_IHOST_SW_PERSISTENT_REG1, reset); in plat_soft_reset()
78 if (reset != SOFT_SYS_RESET_L1) in plat_soft_reset()
79 reset = SOFT_PWR_UP_RESET_L0; in plat_soft_reset()
81 if (reset == SOFT_PWR_UP_RESET_L0) in plat_soft_reset()
84 if (reset == SOFT_SYS_RESET_L1) in plat_soft_reset()
89 mmio_clrbits_32(CRMU_SOFT_RESET_CTRL, 1 << reset); in plat_soft_reset()
H A Dcmn_plat_util.h41 void plat_soft_reset(uint32_t reset);
/rk3399_ARM-atf/docs/design/
H A Dreset-design.rst10 document which provides greater implementation details around the reset code,
13 General reset code flow
16 The TF-A reset code is implemented in BL1 by default. The following high-level
19 |Default reset code flow|
21 This diagram shows the default, unoptimised reset flow. Depending on the system
29 this case. Please refer to section 6 "Using BL31 entrypoint as the reset
32 Programmable CPU reset address
35 By default, TF-A assumes that the CPU reset address is not programmable.
37 they reset. Further logic is then required to identify whether it is a cold or
40 If the reset vector address (reflected in the reset vector base address register
[all …]
H A Dindex.rst14 reset-design
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm.c47 .reset = spm_reset_rc_bus26m,
55 .reset = spm_reset_rc_syspll,
63 .reset = spm_reset_rc_dram,
71 .reset = spm_reset_rc_cpu_buck_ldo,
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm.c52 .reset = spm_reset_rc_bus26m,
60 .reset = spm_reset_rc_syspll,
68 .reset = spm_reset_rc_dram,
76 .reset = spm_reset_rc_cpu_buck_ldo,
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm.c55 .reset = spm_reset_rc_bus26m,
63 .reset = spm_reset_rc_syspll,
71 .reset = spm_reset_rc_dram,
80 .reset = spm_reset_rc_cpu_buck_ldo,
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm.c104 .reset = spm_reset_rc_bus26m,
113 .reset = spm_reset_rc_syspll,
122 .reset = spm_reset_rc_dram,
131 .reset = spm_reset_rc_cpu_buck_ldo,
/rk3399_ARM-atf/plat/amd/versal2/
H A Dscmi.c213 struct scmi_reset *reset; member
223 .reset = scmi0_reset,
407 return &resource->reset[n]; in find_reset()
417 const struct scmi_reset *reset = find_reset(agent_id, scmi_id); in plat_scmi_rstd_get_name() local
419 if (reset == NULL) { in plat_scmi_rstd_get_name()
423 return reset->name; in plat_scmi_rstd_get_name()
440 const struct scmi_reset *reset = find_reset(agent_id, scmi_id); in plat_scmi_rstd_autonomous() local
442 if (reset == NULL) { in plat_scmi_rstd_autonomous()
452 reset->reset_id, plat_scmi_rstd_get_name(agent_id, scmi_id)); in plat_scmi_rstd_autonomous()
460 const struct scmi_reset *reset = find_reset(agent_id, scmi_id); in plat_scmi_rstd_set_state() local
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/
H A Drk3588_rstd.c73 rk_scmi_rstd_t *reset = rk3588_reset_domain_table; in rockchip_get_reset_domain_table() local
77 if (reset->id == id) in rockchip_get_reset_domain_table()
79 reset++; in rockchip_get_reset_domain_table()
/rk3399_ARM-atf/plat/allwinner/common/
H A Darisc_off.S16 # This routine is meant to be called directly from arisc reset (put the
17 # start address in the reset vector), to be actually triggered by that
64 1: l.lwz r5, 0x1c30(r13) # CPU power-on reset
76 reset: l.sw 0x1c00(r13),r0 # pull down our own reset line label
78 l.j reset # just in case ....
/rk3399_ARM-atf/plat/st/common/
H A Dstm32mp_common.c218 static void reset_uart(uint32_t reset) in reset_uart() argument
222 ret = stm32mp_reset_assert(reset, RESET_TIMEOUT_US_1MS); in reset_uart()
229 ret = stm32mp_reset_deassert(reset, RESET_TIMEOUT_US_1MS); in reset_uart()
273 (dt_uart_info.reset < 0)) { in stm32mp_uart_console_setup()
294 reset_uart((uint32_t)dt_uart_info.reset); in stm32mp_uart_console_setup()
/rk3399_ARM-atf/drivers/renesas/rcar_gen4/pwrc/
H A Dpwrc.c236 uint64_t reset; in rcar_pwrc_setup() local
238 reset = (uint64_t)(&plat_secondary_reset) & 0xFFFFFFFFU; in rcar_pwrc_setup()
239 reset &= RCAR_APMU_RVBARPLC_MASK; in rcar_pwrc_setup()
240 reset |= RCAR_APMU_RVBARPL_VLD; in rcar_pwrc_setup()
261 mmio_write_32(rst_barl, (uint32_t)reset); in rcar_pwrc_setup()
/rk3399_ARM-atf/docs/plat/arm/fvp/
H A Dfvp-aemv8-base.rst4 AArch64 with reset to BL1 entrypoint
28 AArch32 with reset to BL1 entrypoint
56 AArch64 with reset to BL31 entrypoint
91 - Since a FIP is not loaded when using BL31 as reset entrypoint, the
104 reset vector for each core.
111 AArch32 with reset to SP_MIN entrypoint
H A Dfvp-cortex-a32.rst4 With reset to BL1 entrypoint
22 With reset to SP_MIN entrypoint
H A Dfvp-cortex-a57-a53.rst4 With reset to BL1 entrypoint
22 With reset to BL31 entrypoint
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm.c226 .reset = spm_reset_rc_vcore,
235 .reset = spm_reset_rc_bus26m,
243 .reset = spm_reset_rc_syspll,
/rk3399_ARM-atf/plat/xilinx/common/include/
H A Dpm_svc_main.h43 int32_t pm_register_sgi(uint32_t sgi_num, uint32_t reset);
/rk3399_ARM-atf/drivers/st/crypto/
H A Dstm32_rng.c321 if (dt_rng.reset >= 0) { in stm32_rng_init()
323 ret = stm32mp_reset_assert((unsigned long)dt_rng.reset, TIMEOUT_US_1MS); in stm32_rng_init()
330 ret = stm32mp_reset_deassert((unsigned long)dt_rng.reset, TIMEOUT_US_1MS); in stm32_rng_init()
/rk3399_ARM-atf/plat/st/common/include/
H A Dstm32mp_dt.h22 int32_t reset; member
/rk3399_ARM-atf/plat/mediatek/common/lpm/
H A Dmt_lp_rm.c49 if ((rc == NULL) || (rc->reset == NULL)) { in mt_lp_rm_reset_constraint()
53 return rc->reset(cpuid, stateid); in mt_lp_rm_reset_constraint()
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm.c237 .reset = spm_reset_rc_vcore,
246 .reset = spm_reset_rc_bus26m,
255 .reset = spm_reset_rc_syspll,
/rk3399_ARM-atf/plat/mediatek/include/lpm/
H A Dmt_lp_rm.h46 int (*reset)(unsigned int cpu, int stateid); member
/rk3399_ARM-atf/plat/mediatek/common/lpm_v2/
H A Dmt_lp_rm.c48 if ((rc == NULL) || (rc->reset == NULL)) in mt_lp_rm_reset_constraint()
51 return rc->reset(cpuid, stateid); in mt_lp_rm_reset_constraint()
/rk3399_ARM-atf/plat/mediatek/include/lpm_v2/
H A Dmt_lp_rm.h51 int (*reset)(unsigned int cpu, int stateid); member

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