xref: /rk3399_ARM-atf/plat/mediatek/include/lpm/mt_lp_rm.h (revision 79c262327aa8ccc1ae5a0ee7f7ead3bf5ce8e022)
11c5fc9a2SLiju-Clr Chen /*
21c5fc9a2SLiju-Clr Chen  * Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
31c5fc9a2SLiju-Clr Chen  *
41c5fc9a2SLiju-Clr Chen  * SPDX-License-Identifier: BSD-3-Clause
51c5fc9a2SLiju-Clr Chen  */
61c5fc9a2SLiju-Clr Chen 
71c5fc9a2SLiju-Clr Chen #ifndef MT_LP_RM_H
81c5fc9a2SLiju-Clr Chen #define MT_LP_RM_H
91c5fc9a2SLiju-Clr Chen 
101c5fc9a2SLiju-Clr Chen #include <stdbool.h>
111c5fc9a2SLiju-Clr Chen 
121c5fc9a2SLiju-Clr Chen #define MT_RM_STATUS_OK		(0)
131c5fc9a2SLiju-Clr Chen #define MT_RM_STATUS_BAD	(-1)
141c5fc9a2SLiju-Clr Chen #define MT_RM_STATUS_STOP	(-2)
151c5fc9a2SLiju-Clr Chen 
161c5fc9a2SLiju-Clr Chen enum PLAT_MT_LPM_RC_TYPE {
171c5fc9a2SLiju-Clr Chen 	PLAT_RC_UPDATE_CONDITION,
181c5fc9a2SLiju-Clr Chen 	PLAT_RC_STATUS,
191c5fc9a2SLiju-Clr Chen 	PLAT_RC_UPDATE_REMAIN_IRQS,
201c5fc9a2SLiju-Clr Chen 	PLAT_RC_IS_FMAUDIO,
211c5fc9a2SLiju-Clr Chen 	PLAT_RC_IS_ADSP,
221c5fc9a2SLiju-Clr Chen 	PLAT_RC_ENTER_CNT,
231c5fc9a2SLiju-Clr Chen 	PLAT_RC_CLKBUF_STATUS,
241c5fc9a2SLiju-Clr Chen 	PLAT_RC_UFS_STATUS,
251c5fc9a2SLiju-Clr Chen 	PLAT_RC_IS_USB_PERI,
261c5fc9a2SLiju-Clr Chen 	PLAT_RC_IS_USB_INFRA,
271c5fc9a2SLiju-Clr Chen 	PLAT_RC_MAX,
281c5fc9a2SLiju-Clr Chen };
291c5fc9a2SLiju-Clr Chen 
301c5fc9a2SLiju-Clr Chen enum plat_mt_lpm_hw_ctrl_type {
311c5fc9a2SLiju-Clr Chen 	PLAT_AP_MDSRC_REQ,
321c5fc9a2SLiju-Clr Chen 	PLAT_AP_MDSRC_ACK,
331c5fc9a2SLiju-Clr Chen 	PLAT_AP_IS_MD_SLEEP,
341c5fc9a2SLiju-Clr Chen 	PLAT_AP_MDSRC_SETTLE,
351c5fc9a2SLiju-Clr Chen 	PLAT_AP_GPUEB_PLL_CONTROL,
361c5fc9a2SLiju-Clr Chen 	PLAT_AP_GPUEB_GET_PWR_STATUS,
371c5fc9a2SLiju-Clr Chen 	PLAT_AP_HW_CTRL_MAX,
381c5fc9a2SLiju-Clr Chen };
391c5fc9a2SLiju-Clr Chen 
401c5fc9a2SLiju-Clr Chen struct mt_resource_constraint {
411c5fc9a2SLiju-Clr Chen 	int level;
421c5fc9a2SLiju-Clr Chen 	int (*init)(void);
431c5fc9a2SLiju-Clr Chen 	bool (*is_valid)(unsigned int cpu, int stateid);
441c5fc9a2SLiju-Clr Chen 	int (*update)(int stateid, int type, const void *p);
451c5fc9a2SLiju-Clr Chen 	int (*run)(unsigned int cpu, int stateid);
461c5fc9a2SLiju-Clr Chen 	int (*reset)(unsigned int cpu, int stateid);
471c5fc9a2SLiju-Clr Chen 	int (*get_status)(unsigned int type, void *priv);
481c5fc9a2SLiju-Clr Chen 	unsigned int (*allow)(int stateid);
491c5fc9a2SLiju-Clr Chen };
501c5fc9a2SLiju-Clr Chen 
511c5fc9a2SLiju-Clr Chen struct mt_resource_manager {
52b0208c73SLiju-Clr Chen 	int (*update)(struct mt_resource_constraint **con, unsigned int num,
531c5fc9a2SLiju-Clr Chen 		      int stateid, void *priv);
541c5fc9a2SLiju-Clr Chen 	struct mt_resource_constraint **consts;
551c5fc9a2SLiju-Clr Chen };
561c5fc9a2SLiju-Clr Chen 
571c5fc9a2SLiju-Clr Chen extern int mt_lp_rm_register(struct mt_resource_manager *rm);
58*a321337bSLiju-Clr Chen extern int mt_lp_rm_do_constraint(unsigned int constraint_id, unsigned int cpuid, int stateid);
59*a321337bSLiju-Clr Chen extern int mt_lp_rm_find_constraint(unsigned int idx, unsigned int cpuid,
601c5fc9a2SLiju-Clr Chen 				    int stateid, void *priv);
61*a321337bSLiju-Clr Chen extern int mt_lp_rm_find_and_run_constraint(unsigned int idx, unsigned int cpuid,
62*a321337bSLiju-Clr Chen 					    int stateid, void *priv);
63*a321337bSLiju-Clr Chen extern int mt_lp_rm_reset_constraint(unsigned int idx, unsigned int cpuid, int stateid);
641c5fc9a2SLiju-Clr Chen extern int mt_lp_rm_do_update(int stateid, int type, void const *p);
651c5fc9a2SLiju-Clr Chen extern int mt_lp_rm_get_status(unsigned int type, void *priv);
661c5fc9a2SLiju-Clr Chen 
671c5fc9a2SLiju-Clr Chen #endif /* MT_LP_RM_H */
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