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Searched refs:refdiv (Results 1 – 5 of 5) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/scmi/
H A Drk3568_clk.c130 uint32_t refdiv; member
143 .refdiv = _refdiv, \
318 (div->refdiv << RK3568_PLLCON1_REFDIV_SHIFT)); in rk3568_apll_set_rate()
349 unsigned int fbdiv, postdiv1, refdiv, postdiv2; in rk3568_apll_get_rate() local
365 refdiv = (mmio_read_32(CRU_BASE + RK3568_PLLCON(1)) >> in rk3568_apll_get_rate()
373 rate64 = rate64 / refdiv; in rk3568_apll_get_rate()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Ddfs.c28 {.mhz = 928, .refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1},
29 {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1},
30 {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1},
31 {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1},
32 {.mhz = 600, .refdiv = 1, .fbdiv = 50, .postdiv1 = 2, .postdiv2 = 1},
33 {.mhz = 528, .refdiv = 1, .fbdiv = 66, .postdiv1 = 3, .postdiv2 = 1},
34 {.mhz = 400, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1},
35 {.mhz = 300, .refdiv = 1, .fbdiv = 50, .postdiv1 = 4, .postdiv2 = 1},
36 {.mhz = 200, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2},
1714 uint32_t refdiv, postdiv1, fbdiv, postdiv2; in ddr_get_rate() local
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H A Dsuspend.c700 uint32_t refdiv, postdiv2, postdiv1, fbdiv; in dmc_suspend() local
715 refdiv = REFDIV_DEC(dpll_data[1]); in dmc_suspend()
718 (refdiv * postdiv1 * postdiv2)) * MHz; in dmc_suspend()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/soc/
H A Dsoc.h125 uint32_t refdiv; member
/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32mp2.c740 uint32_t fracin, fbdiv, refdiv; in clk_get_pll_fvco() local
750 refdiv = mmio_read_32(pllxcfgr2) & RCC_PLLxCFGR2_FREFDIV_MASK; in clk_get_pll_fvco()
757 denominator = (uint64_t)refdiv << 24; in clk_get_pll_fvco()
760 fvco = (unsigned long)(refclk * fbdiv / refdiv); in clk_get_pll_fvco()
927 uint32_t reg, fbdiv, refdiv; in clk_get_pll1_fvco() local
932 refdiv = (reg & A35_SS_PLL_FREQ1_REFDIV_MASK) >> A35_SS_PLL_FREQ1_REFDIV_SHIFT; in clk_get_pll1_fvco()
934 return (unsigned long)(refclk * fbdiv / refdiv); in clk_get_pll1_fvco()
1600 static void stm32mp2_a35_pll1_config(uint32_t fbdiv, uint32_t refdiv, uint32_t postdiv1, in stm32mp2_a35_pll1_config() argument
1608 (refdiv << A35_SS_PLL_FREQ1_REFDIV_SHIFT) & in stm32mp2_a35_pll1_config()