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Searched refs:r2 (Results 1 – 25 of 60) sorted by relevance

123

/rk3399_ARM-atf/plat/st/stm32mp1/
H A Dstm32mp1_helper.S210 ldr r2, =DEBUG_UART_RST_BIT
211 str r2, [r1]
214 ands r2, r0, r2
216 str r2, [r1, #4] /* RSTCLR register */
219 ands r2, r0, r2
223 ldr r2, [r1]
225 orr r2, r2, #DEBUG_UART_TX_GPIO_BANK_CLK_EN
226 str r2, [r1]
229 ldr r2, [r1, #GPIO_MODE_OFFSET]
230 bic r2, r2, #(GPIO_MODE_MASK << GPIO_TX_SHIFT)
[all …]
/rk3399_ARM-atf/lib/libc/aarch32/
H A Dmemset.S28 subs r2, r2, #1
40 cmp r2, #16
48 subs r2, r2, #32
53 lsls r2, r2, #28 /* C = r2[4]; N = r2[3]; Z = r2[3:0] */
57 lsls r2, r2, #2 /* C = r2[2]; N = r2[1]; Z = r2[1:0] */
61 lsls r2, r2, #1 /* N = Z = r2[0] */
65 less_16:lsls r2, r2, #29 /* C = r2[3]; N = r2[2]; Z = r2[2:0] */
69 lsls r2, r2, #2 /* C = r2[1]; N = Z = r2[0] */
/rk3399_ARM-atf/include/arch/aarch32/
H A Dsmccc_macros.S28 bic r2, r4, #SCR_NS_BIT
29 stcopr r2, SCR
36 mrs r2, spsr
37 stm r0!, {r2, sp, lr}
40 mrs r2, spsr
41 stm r0!, {r2, sp, lr}
44 mrs r2, spsr
45 stm r0!, {r2, sp, lr}
48 mrs r2, spsr
49 stm r0!, {r2, sp, lr}
[all …]
/rk3399_ARM-atf/drivers/ti/uart/aarch32/
H A D16550_console.S47 cmp r2, #0
52 lsl r2, r2, #4
53 udiv r2, r1, r2
54 and r1, r2, #0xff /* w1 = DLL */
55 lsr r2, r2, #8
56 and r2, r2, #0xff /* w2 = DLLM */
61 str r2, [r0, #UARTDLLM] /* program DLLM */
62 mov r2, #~UARTLCR_DLAB
63 and r3, r3, r2
153 1: ldr r2, [r1, #UARTLSR]
[all …]
/rk3399_ARM-atf/lib/xlat_tables_v2/aarch32/
H A Denable_mmu.S34 ldr r2, [r0, #(MMU_CFG_TCR << 3)]
35 stcopr r2, TTBCR
39 ldr r2, [r0, #((MMU_CFG_TTBR0 << 3) + 4)]
40 stcopr16 r1, r2, TTBR0_64
44 mov r2, #0
45 stcopr16 r1, r2, TTBR1_64
57 ldr r2, =(SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT)
58 orr r1, r1, r2
91 ldr r2, [r0, #(MMU_CFG_TCR << 3)]
92 stcopr r2, HTCR
[all …]
/rk3399_ARM-atf/drivers/arm/css/sds/aarch32/
H A Dsds_helpers.S23 ldr r2, =SDS_REGION_SIGNATURE
28 cmp r2, r3
40 ldrh r2, [r0]
41 cmp r2, #SDS_AP_CPU_INFO_STRUCT_ID
54 ldr r2, [r0,#4]
56 ubfx r2, r2, #SDS_HEADER_STRUCT_SIZE_SHIFT, #SDS_HEADER_STRUCT_SIZE_WIDTH
58 add r2, r2, #SDS_HEADER_SIZE
59 add r0, r0, r2
/rk3399_ARM-atf/drivers/renesas/common/ddr/ddr_a/
H A Dddr_init_d3.c26 uint32_t i, r2, r3, r5, r6, r7, r12; in init_ddr_d3_1866() local
155 r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9; in init_ddr_d3_1866()
156 r3 = (r2 << 16) + (r2 << 8) + r2; in init_ddr_d3_1866()
157 r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2; in init_ddr_d3_1866()
194 r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; in init_ddr_d3_1866()
197 mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); in init_ddr_d3_1866()
199 r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; in init_ddr_d3_1866()
201 mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); in init_ddr_d3_1866()
204 r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; in init_ddr_d3_1866()
206 mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); in init_ddr_d3_1866()
[all …]
H A Dddr_init_v3m.c17 uint32_t i, r2, r5, r6, r7, r12; in init_ddr_v3m_1600() local
203 r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); in init_ddr_v3m_1600()
206 mmio_write_32(DBSC_DBPDRGD_0, ((r7 + 1) & 0x7) | r2); in init_ddr_v3m_1600()
208 r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); in init_ddr_v3m_1600()
210 mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); in init_ddr_v3m_1600()
213 r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); in init_ddr_v3m_1600()
215 mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); in init_ddr_v3m_1600()
218 r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00); in init_ddr_v3m_1600()
220 mmio_write_32(DBSC_DBPDRGD_0, r2 | in init_ddr_v3m_1600()
276 r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8); in init_ddr_v3m_1600()
[all …]
H A Dddr_init_e3.c37 uint32_t i, r2, r5, r6, r7, r12; in init_ddr() local
88 r2 = mmio_read_32(0xE6790614); in init_ddr()
89 mmio_write_32(0xE6790614, r2 | 0x3); /* MCS1_N/MODT1 are activated. */ in init_ddr()
386 r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; in init_ddr()
388 mmio_write_32(DBSC_DBPDRGD_0, r2 | ((r7 + 0x1) & 0x7)); in init_ddr()
390 r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; in init_ddr()
392 mmio_write_32(DBSC_DBPDRGD_0, r2 | r6); in init_ddr()
395 r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFFF8; in init_ddr()
397 mmio_write_32(DBSC_DBPDRGD_0, r2 | r7); in init_ddr()
399 r2 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFFFFFF00; in init_ddr()
[all …]
/rk3399_ARM-atf/plat/qti/msm8916/aarch32/
H A Duartdm_console.S74 mov r2, #65536
79 subs r2, r2, #1
135 ldr r2, [r1, #UART_DM_SR]
136 tst r2, #UART_DM_SR_TXRDY
140 mov r2, #'\r'
141 str r2, [r1, #UART_DM_TF]
144 ldr r2, [r1, #UART_DM_SR]
145 tst r2, #UART_DM_SR_TXRDY
179 ldr r2, [r1, #UART_DM_SR]
180 tst r2, #UART_DM_SR_TXEMT
H A Dmsm8916_helpers.S120 ldr r2, [r1, #APCS_TCM_START_ADDR]
121 and r2, r2, #~APCS_TCM_REDIRECT_EN_0
122 str r2, [r1, #APCS_TCM_START_ADDR]
/rk3399_ARM-atf/plat/arm/board/fvp/aarch32/
H A Dfvp_helpers.S53 ldcopr r2, MPIDR
55 str r2, [r1, #PSYSR_OFF]
56 ldr r2, [r1, #PSYSR_OFF]
57 ubfx r2, r2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH
58 cmp r2, #WKUP_PPONR
60 cmp r2, #WKUP_GICREQ
134 ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
138 mla r1, r2, r3, r1
/rk3399_ARM-atf/lib/aarch32/
H A Dmisc_helpers.S57 zeroreg1 .req r2 /* Source register filled with 0 */
153 cmp r2, #4
157 subs r2, r2, #4
165 subs r2, r2, #1
234 and r2, lr, r1
235 subs r0, r2, r6 /* Diff(S) = Current Address - Compiled Address */
240 ldr r2, =__GOT_END__
241 add r2, r2, r0
262 cmp r1, r2
268 ldr r2, =__RELA_END__
[all …]
H A Dcache_helpers.S26 dcache_line_size r2, r3
28 sub r3, r2, #1
32 add r0, r0, r2
85 ldcopr r2, CLIDR
86 ubfx r3, r2, \shift, \fw
100 mov r12, r2, LSR r10 // extract cache type bits from clidr
193 ldcopr r2, CLIDR
/rk3399_ARM-atf/drivers/arm/pl011/aarch32/
H A Dpl011_console.S48 cmp r2, #0
59 softudiv r0,r1,r2,r3
60 mov r2, r0
63 udiv r2, r1, r2
66 lsr r1, r2, #6
70 and r1, r2, #0x3f
144 ldr r2, [r1, #UARTFR]
145 tst r2, #PL011_UARTFR_TXFF
147 mov r2, #0xD
148 str r2, [r1, #UARTDR]
[all …]
/rk3399_ARM-atf/bl32/sp_min/aarch32/
H A Dentrypoint.S71 mov r11, r2
119 mov r2, r11
185 mov r2, sp /* handle */
186 ldr sp, [r2, #SMC_CTX_SP_MON]
190 mov r6, r2
202 mov r2, r6
205 ldr r0, [r2, #SMC_CTX_SCR]
213 ldr r0, [r2, #SMC_CTX_GPREG_R0] /* smc_fid */
219 str r0, [r2, #SMC_CTX_GPREG_R0]
220 mov r0, r2
[all …]
/rk3399_ARM-atf/lib/cpus/aarch32/
H A Dcortex_a57.S72 mov r2, lr
74 mov lr, r2
120 mov r2, lr
122 mov lr, r2
151 mov r2, lr
160 bx r2
201 mov r2, lr
203 mov lr, r2
232 mov r2, lr
234 mov lr, r2
[all …]
/rk3399_ARM-atf/drivers/st/uart/aarch32/
H A Dstm32_console.S63 cmp r2, #0
76 lsr r3, r2, #1
78 udiv r3, r3, r2
83 lsr r3, r2, #1
85 udiv r3, r3, r2
100 mov r2, #USART_TIMEOUT
102 subs r2, r2, #1
170 ldr r2, [r1, #USART_ISR]
171 tst r2, #USART_ISR_TXE
/rk3399_ARM-atf/lib/locks/exclusive/aarch32/
H A Dspinlock.S
/rk3399_ARM-atf/drivers/brcm/emmc/
H A Demmc_csl_sdcmd.c169 card->csd.mmc.structure = (resp.data.r2.rsp4 >> 22) & 0x3; in sd_cmd9()
170 card->csd.mmc.csdSpecVer = (resp.data.r2.rsp4 >> 18) & 0x0f; in sd_cmd9()
171 card->csd.mmc.taac = (resp.data.r2.rsp4 >> 8) & 0xff; in sd_cmd9()
172 card->csd.mmc.nsac = resp.data.r2.rsp4 & 0xff; in sd_cmd9()
173 card->csd.mmc.speed = resp.data.r2.rsp3 >> 24; in sd_cmd9()
174 card->csd.mmc.classes = (resp.data.r2.rsp3 >> 12) & 0xfff; in sd_cmd9()
175 card->csd.mmc.rdBlkLen = (resp.data.r2.rsp3 >> 8) & 0xf; in sd_cmd9()
176 card->csd.mmc.rdBlkPartial = (resp.data.r2.rsp3 >> 7) & 0x01; in sd_cmd9()
177 card->csd.mmc.wrBlkMisalign = (resp.data.r2.rsp3 >> 6) & 0x1; in sd_cmd9()
178 card->csd.mmc.rdBlkMisalign = (resp.data.r2.rsp3 >> 5) & 0x1; in sd_cmd9()
[all …]
/rk3399_ARM-atf/plat/arm/board/a5ds/aarch32/
H A Da5ds_helpers.S28 mov_imm r2, A5DS_HOLD_BASE
31 str r3, [r2, r0]
36 ldr r1, [r2, r0]
117 ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
121 mla r1, r2, r3, r1
/rk3399_ARM-atf/lib/compiler-rt/builtins/arm/
H A Daeabi_uldivmod.S31 movs r0, r2
32 movs r2, r6
38 ldr r2, [sp, #8]
H A Daeabi_ldivmod.S31 movs r0, r2
32 movs r2, r6
38 ldr r2, [sp, #8]
H A Daeabi_memset.S18 mov r1, r2
19 mov r2, r3
34 mov r2, r1
/rk3399_ARM-atf/lib/psci/
H A Dpsci_main.c467 uint32_t r2 = (uint32_t)x2; in psci_smc_handler() local
480 ret = (u_register_t)psci_cpu_suspend(r1, r2, r3); in psci_smc_handler()
484 ret = (u_register_t)psci_cpu_on(r1, r2, r3); in psci_smc_handler()
488 ret = (u_register_t)psci_affinity_info(r1, r2); in psci_smc_handler()
504 ret = (u_register_t)psci_node_hw_state(r1, r2); in psci_smc_handler()
508 ret = (u_register_t)psci_system_suspend(r1, r2); in psci_smc_handler()
533 ret = psci_stat_residency(r1, r2); in psci_smc_handler()
537 ret = psci_stat_count(r1, r2); in psci_smc_handler()
545 ret = psci_mem_chk_range(r1, r2); in psci_smc_handler()
550 ret = psci_system_reset2(r1, r2); in psci_smc_handler()

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