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Searched refs:parents (Results 1 – 12 of 12) sorted by relevance

/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dpm_api_clock.c238 int32_t (*parents)[]; member
833 .parents = &((int32_t []) {CLK_APLL_PRE_SRC, CLK_NA_PARENT}),
841 .parents = &((int32_t []) {
859 .parents = &((int32_t []) {CLK_APLL_INT, CLK_NA_PARENT}),
867 .parents = &((int32_t []) {
879 .parents = &((int32_t []) {
897 .parents = &((int32_t []) {
909 .parents = &((int32_t []) {CLK_DPLL_PRE_SRC, CLK_NA_PARENT}),
917 .parents = &((int32_t []) {
935 .parents = &((int32_t []) {CLK_DPLL_INT, CLK_NA_PARENT}),
[all …]
H A Dpm_api_clock.h308 uint32_t *parents);
H A Dzynqmp_pm_api_sys.c1143 uint32_t *parents) in pm_clock_get_parents() argument
1145 return pm_api_clock_get_parents(clock_id, index, parents); in pm_clock_get_parents()
/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32-core.c280 const struct parent_cfg *parents = &priv->parents[pid & MUX_PARENT_MASK]; in clk_mux_set_parent() local
281 const struct mux_cfg *mux = parents->mux; in clk_mux_set_parent()
309 const struct parent_cfg *parents; in _clk_stm32_set_parent() local
328 parents = &priv->parents[pid & MUX_PARENT_MASK]; in _clk_stm32_set_parent()
330 for (sel = 0; sel < parents->num_parents; sel++) { in _clk_stm32_set_parent()
331 if (parents->id_parents[sel] == (uint16_t)clkp) { in _clk_stm32_set_parent()
366 parent = &priv->parents[mux_id]; in clk_mux_get_parent()
404 parent = &priv->parents[mux_id]; in _clk_stm32_get_parent()
452 parent = &priv->parents[mux_id]; in _clk_stm32_get_parent_by_index()
H A Dclk-stm32-core.h68 const struct parent_cfg *parents; member
H A Dstm32mp1_clk.c72 const struct mux_cfg *parents; member
223 mux = &priv->parents[mux_id]; in clk_mux_get_parent()
232 const struct mux_cfg *mux = &priv->parents[pid]; in clk_mux_set_parent()
2640 .parents = parent_mp15,
H A Dclk-stm32mp13.c2010 .parents = parent_mp13,
H A Dclk-stm32mp2.c2508 .parents = parent_mp2,
/rk3399_ARM-atf/fdts/
H A Drtsm_ve-motherboard.dtsi132 …assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz…
/rk3399_ARM-atf/tools/cot_dt2c/cot_dt2c/
H A Dcot_parser.py661 filename.parent.mkdir(exist_ok=True, parents=True)
/rk3399_ARM-atf/docs/design/
H A Dpsci-pd-tree.rst187 * domains i.e. leaf nodes and all other power domains which are parents of a
/rk3399_ARM-atf/docs/
H A Dchange-log.md10214 - Added support for using additional clocks as parents