| /rk3399_ARM-atf/plat/arm/board/fvp/ |
| H A D | fvp_gicv3.c | 76 gic_data.gicd_base = (uintptr_t)FCONF_GET_PROPERTY(hw_config, in fvp_gic_driver_pre_init()
79 arm_gicr_base_addrs[0] = FCONF_GET_PROPERTY(hw_config, gicv3_config, in fvp_gic_driver_pre_init()
82 gic_data.interrupt_props = FCONF_GET_PROPERTY(hw_config, in fvp_gic_driver_pre_init()
84 gic_data.interrupt_props_num = FCONF_GET_PROPERTY(hw_config, in fvp_gic_driver_pre_init()
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| H A D | fvp_console.c | 38 uart_base = FCONF_GET_PROPERTY(hw_config, uart_serial_config, in arm_console_runtime_init()
40 uart_clk = FCONF_GET_PROPERTY(hw_config, uart_serial_config, in arm_console_runtime_init()
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| H A D | fvp_topology.c | 43 cluster_count = FCONF_GET_PROPERTY(hw_config, topology, plat_cluster_count); in plat_get_power_domain_tree_desc()
44 cpus_per_cluster = FCONF_GET_PROPERTY(hw_config, topology, cluster_cpu_count); in plat_get_power_domain_tree_desc()
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| H A D | fvp_common.c | 789 num_banks = FCONF_GET_PROPERTY(hw_config, dram_layout, num_banks); in plat_rmmd_load_manifest()
888 bank_ptr[i].base = FCONF_GET_PROPERTY(hw_config, dram_layout, dram_bank[i].base); in plat_rmmd_load_manifest()
889 bank_ptr[i].size = FCONF_GET_PROPERTY(hw_config, dram_layout, dram_bank[i].size); in plat_rmmd_load_manifest()
930 num_ncoh_regions = FCONF_GET_PROPERTY(hw_config, pci_props, num_ncoh_regions); in plat_rmmd_load_manifest()
936 FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].base); in plat_rmmd_load_manifest()
938 FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].size); in plat_rmmd_load_manifest()
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| H A D | fvp_bl31_setup.c | 167 counter_base_frequency = FCONF_GET_PROPERTY(hw_config, cpu_timer, clock_freq); in plat_get_syscnt_freq2()
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| /rk3399_ARM-atf/plat/arm/board/fvp/sp_min/ |
| H A D | fvp_sp_min_setup.c | 17 static uintptr_t hw_config __unused;
42 hw_config = (uintptr_t)arg2; in plat_arm_sp_min_early_platform_setup()
98 INFO("SP_MIN FCONF: HW_CONFIG address = %p\n", (void *)hw_config); in sp_min_plat_arch_setup()
99 fconf_populate("HW_CONFIG", hw_config); in sp_min_plat_arch_setup()
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| /rk3399_ARM-atf/plat/mediatek/common/ |
| H A D | mtk_bl31_setup.c | 84 arg = bl31_fw_config.hw_config; in get_mtk_bl31_fw_config()
104 u_register_t hw_config, u_register_t plat_params_from_bl2) in bl31_early_platform_setup2() argument
131 bl31_fw_config.hw_config = (void *)hw_config; in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/include/plat/marvell/armada/a3k/common/ |
| H A D | plat_marvell.h | 73 uintptr_t hw_config,
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| /rk3399_ARM-atf/include/plat/marvell/armada/a8k/common/ |
| H A D | plat_marvell.h | 89 uintptr_t hw_config,
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| /rk3399_ARM-atf/tools/cot_dt2c/tests/ |
| H A D | test_invalid_missing_attribute.dtsi | 54 hw_config {
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| H A D | test_invalid_undefined_parent.dtsi | 58 hw_config {
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| H A D | test_invalid_missing_root.dtsi | 113 hw_config {
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| /rk3399_ARM-atf/plat/marvell/armada/common/ |
| H A D | marvell_bl31_setup.c | 66 uintptr_t hw_config, in marvell_bl31_early_platform_setup() argument
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| /rk3399_ARM-atf/fdts/ |
| H A D | stm32mp1-cot-descriptors.dtsi | 99 hw_config {
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| H A D | cca_cot_descriptors.dts | 139 hw_config {
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| H A D | dualroot_cot_descriptors.dts | 181 hw_config {
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| H A D | tbbr_cot_descriptors.dts | 192 hw_config {
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| /rk3399_ARM-atf/plat/brcm/common/ |
| H A D | brcm_bl31_setup.c | 86 uintptr_t hw_config, in brcm_bl31_early_platform_setup() argument
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| /rk3399_ARM-atf/drivers/arm/ethosn/ |
| H A D | ethosn_smc.c | 28 FCONF_GET_PROPERTY(hw_config, ethosn_config, num_devices)
31 FCONF_GET_PROPERTY(hw_config, ethosn_device, dev_idx)
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| /rk3399_ARM-atf/drivers/auth/tbbr/ |
| H A D | tbbr_cot_bl2.c | 88 static const auth_img_desc_t hw_config = { variable
673 [HW_CONFIG_ID] = &hw_config,
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| /rk3399_ARM-atf/plat/arm/board/juno/ |
| H A D | juno_tbbr_cot_bl2.c | 749 static const auth_img_desc_t hw_config = { variable
766 [HW_CONFIG_ID] = &hw_config,
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| /rk3399_ARM-atf/docs/components/fconf/ |
| H A D | index.rst | 31 - GICv3 properties: hw_config.gicv3_config.gicr_base
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| /rk3399_ARM-atf/docs/ |
| H A D | change-log.md | 9735 - Added support to use hw_config in BL31
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