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Searched refs:cpu (Results 1 – 25 of 208) sorted by relevance

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/rk3399_ARM-atf/plat/mediatek/mt8192/
H A Dplat_pm.c62 static void plat_cpu_pwrdwn_common(unsigned int cpu, in plat_cpu_pwrdwn_common() argument
65 assert(cpu == plat_my_core_pos()); in plat_cpu_pwrdwn_common()
67 plat_mt_pm_invoke_no_check(pwr_cpu_dwn, cpu, state); in plat_cpu_pwrdwn_common()
76 gicv3_cpuif_disable(cpu); in plat_cpu_pwrdwn_common()
77 gicv3_rdistif_off(cpu); in plat_cpu_pwrdwn_common()
79 ptp3_deinit(cpu); in plat_cpu_pwrdwn_common()
82 static void plat_cpu_pwron_common(unsigned int cpu, in plat_cpu_pwron_common() argument
85 assert(cpu == plat_my_core_pos()); in plat_cpu_pwron_common()
87 plat_mt_pm_invoke_no_check(pwr_cpu_on, cpu, state); in plat_cpu_pwron_common()
98 gicv3_rdistif_on(cpu); in plat_cpu_pwron_common()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8195/
H A Dplat_pm.c62 static void plat_cpu_pwrdwn_common(unsigned int cpu, in plat_cpu_pwrdwn_common() argument
65 assert(cpu == plat_my_core_pos()); in plat_cpu_pwrdwn_common()
67 plat_mt_pm_invoke_no_check(pwr_cpu_dwn, cpu, state); in plat_cpu_pwrdwn_common()
76 gicv3_cpuif_disable(cpu); in plat_cpu_pwrdwn_common()
77 gicv3_rdistif_off(cpu); in plat_cpu_pwrdwn_common()
80 static void plat_cpu_pwron_common(unsigned int cpu, in plat_cpu_pwron_common() argument
83 assert(cpu == plat_my_core_pos()); in plat_cpu_pwron_common()
85 plat_mt_pm_invoke_no_check(pwr_cpu_on, cpu, state); in plat_cpu_pwron_common()
90 ptp3_core_init(cpu); in plat_cpu_pwron_common()
99 gicv3_rdistif_on(cpu); in plat_cpu_pwron_common()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8186/
H A Dplat_pm.c40 static inline int plat_mt_pm_invoke(int (*func)(unsigned int cpu, in plat_mt_pm_invoke() argument
42 int cpu, const psci_power_state_t *state) in plat_mt_pm_invoke()
47 ret = func(cpu, state); in plat_mt_pm_invoke()
56 static void plat_cpu_pwrdwn_common(unsigned int cpu, in plat_cpu_pwrdwn_common() argument
59 assert(cpu == plat_my_core_pos()); in plat_cpu_pwrdwn_common()
62 (void)plat_mt_pm_invoke(plat_mt_pm->pwr_cpu_dwn, cpu, state); in plat_cpu_pwrdwn_common()
71 gicv3_cpuif_disable(cpu); in plat_cpu_pwrdwn_common()
72 gicv3_rdistif_off(cpu); in plat_cpu_pwrdwn_common()
75 static void plat_cpu_pwron_common(unsigned int cpu, in plat_cpu_pwron_common() argument
78 assert(cpu == plat_my_core_pos()); in plat_cpu_pwron_common()
[all …]
/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhisi_ipc.c37 int hisi_cpus_pd_in_cluster_besides_curr(unsigned int cpu, in hisi_cpus_pd_in_cluster_besides_curr() argument
48 if (cpu == i) in hisi_cpus_pd_in_cluster_besides_curr()
59 int hisi_cpus_powered_off_besides_curr(unsigned int cpu) in hisi_cpus_powered_off_besides_curr() argument
64 return (val == (0x8 << (cpu * 4))); in hisi_cpus_powered_off_besides_curr()
97 void hisi_ipc_cpu_on_off(unsigned int cpu, unsigned int cluster, in hisi_ipc_cpu_on_off() argument
104 offset = cluster * 16 + cpu * 4; in hisi_ipc_cpu_on_off()
106 offset = cluster * 16 + cpu * 4 + 1; in hisi_ipc_cpu_on_off()
116 hisi_ipc_send(cpu_ipc_num[cluster][cpu]); in hisi_ipc_cpu_on_off()
119 void hisi_ipc_cpu_on(unsigned int cpu, unsigned int cluster) in hisi_ipc_cpu_on() argument
121 hisi_ipc_cpu_on_off(cpu, cluster, HISI_IPC_PM_ON); in hisi_ipc_cpu_on()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spmc/
H A Dmtspmc.c18 void mcucfg_disable_gic_wakeup(unsigned int cluster, unsigned int cpu) in mcucfg_disable_gic_wakeup() argument
20 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_disable_gic_wakeup()
23 void mcucfg_enable_gic_wakeup(unsigned int cluster, unsigned int cpu) in mcucfg_enable_gic_wakeup() argument
25 mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_enable_gic_wakeup()
27 mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_CLR, BIT(cpu)); in mcucfg_enable_gic_wakeup()
30 void mcucfg_set_bootaddr(unsigned int cluster, unsigned int cpu, uintptr_t bootaddr) in mcucfg_set_bootaddr() argument
34 mmio_write_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR), bootaddr); in mcucfg_set_bootaddr()
37 uintptr_t mcucfg_get_bootaddr(unsigned int cluster, unsigned int cpu) in mcucfg_get_bootaddr() argument
41 return (uintptr_t)mmio_read_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR)); in mcucfg_get_bootaddr()
44 void mcucfg_init_archstate(unsigned int cluster, unsigned int cpu, bool arm64) in mcucfg_init_archstate() argument
[all …]
H A Dmtspmc.h14 void spm_poweron_cpu(unsigned int cluster, unsigned int cpu);
15 void spm_poweroff_cpu(unsigned int cluster, unsigned int cpu);
20 bool spm_get_cpu_powerstate(unsigned int cluster, unsigned int cpu);
24 void mcucfg_init_archstate(unsigned int cluster, unsigned int cpu, bool arm64);
25 void mcucfg_set_bootaddr(unsigned int cluster, unsigned int cpu, uintptr_t bootaddr);
26 uintptr_t mcucfg_get_bootaddr(unsigned int cluster, unsigned int cpu);
28 void mcucfg_disable_gic_wakeup(unsigned int cluster, unsigned int cpu);
29 void mcucfg_enable_gic_wakeup(unsigned int cluster, unsigned int cpu);
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/constraints/
H A Dmt_spm_rc_internal.h18 bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
20 int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
21 int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
24 bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
27 int spm_run_rc_dram(unsigned int cpu, int state_id);
28 int spm_reset_rc_dram(unsigned int cpu, int state_id);
31 bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
34 int spm_run_rc_syspll(unsigned int cpu, int state_id);
35 int spm_reset_rc_syspll(unsigned int cpu, int state_id);
38 bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/constraints/
H A Dmt_spm_rc_internal.h20 bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
22 int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
23 int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
26 bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
29 int spm_run_rc_dram(unsigned int cpu, int state_id);
30 int spm_reset_rc_dram(unsigned int cpu, int state_id);
33 bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
36 int spm_run_rc_syspll(unsigned int cpu, int state_id);
37 int spm_reset_rc_syspll(unsigned int cpu, int state_id);
40 bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/constraints/
H A Dmt_spm_rc_internal.h22 bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
24 int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
25 int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
28 bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
31 int spm_run_rc_dram(unsigned int cpu, int state_id);
32 int spm_reset_rc_dram(unsigned int cpu, int state_id);
35 bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
38 int spm_run_rc_syspll(unsigned int cpu, int state_id);
39 int spm_reset_rc_syspll(unsigned int cpu, int state_id);
42 bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spmc/
H A Dmtspmc.c18 void mcucfg_disable_gic_wakeup(unsigned int cluster, unsigned int cpu) in mcucfg_disable_gic_wakeup() argument
20 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_disable_gic_wakeup()
23 void mcucfg_enable_gic_wakeup(unsigned int cluster, unsigned int cpu) in mcucfg_enable_gic_wakeup() argument
25 mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_enable_gic_wakeup()
28 void mcucfg_set_bootaddr(unsigned int cluster, unsigned int cpu, uintptr_t bootaddr) in mcucfg_set_bootaddr() argument
32 mmio_write_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR), bootaddr); in mcucfg_set_bootaddr()
35 uintptr_t mcucfg_get_bootaddr(unsigned int cluster, unsigned int cpu) in mcucfg_get_bootaddr() argument
39 return (uintptr_t)mmio_read_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR)); in mcucfg_get_bootaddr()
42 void mcucfg_init_archstate(unsigned int cluster, unsigned int cpu, bool arm64) in mcucfg_init_archstate() argument
51 mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
[all …]
H A Dmtspmc.h14 void spm_poweron_cpu(unsigned int cluster, unsigned int cpu);
15 void spm_poweroff_cpu(unsigned int cluster, unsigned int cpu);
20 bool spm_get_cpu_powerstate(unsigned int cluster, unsigned int cpu);
24 void mcucfg_init_archstate(unsigned int cluster, unsigned int cpu, bool arm64);
25 void mcucfg_set_bootaddr(unsigned int cluster, unsigned int cpu, uintptr_t bootaddr);
26 uintptr_t mcucfg_get_bootaddr(unsigned int cluster, unsigned int cpu);
28 void mcucfg_disable_gic_wakeup(unsigned int cluster, unsigned int cpu);
29 void mcucfg_enable_gic_wakeup(unsigned int cluster, unsigned int cpu);
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spmc/
H A Dmtspmc.c18 void mcucfg_disable_gic_wakeup(uint32_t cluster, uint32_t cpu) in mcucfg_disable_gic_wakeup() argument
20 mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_disable_gic_wakeup()
23 void mcucfg_enable_gic_wakeup(uint32_t cluster, uint32_t cpu) in mcucfg_enable_gic_wakeup() argument
25 mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu)); in mcucfg_enable_gic_wakeup()
28 void mcucfg_set_bootaddr(uint32_t cluster, uint32_t cpu, uintptr_t bootaddr) in mcucfg_set_bootaddr() argument
32 mmio_write_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR), bootaddr); in mcucfg_set_bootaddr()
35 uintptr_t mcucfg_get_bootaddr(uint32_t cluster, uint32_t cpu) in mcucfg_get_bootaddr() argument
39 return (uintptr_t)mmio_read_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR)); in mcucfg_get_bootaddr()
42 void mcucfg_init_archstate(uint32_t cluster, uint32_t cpu, bool arm64) in mcucfg_init_archstate() argument
51 mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu)); in mcucfg_init_archstate()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spmc/
H A Dmtspmc.c40 void spm_enable_cpu_auto_off(int cluster, int cpu) in spm_enable_cpu_auto_off() argument
42 uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK); in spm_enable_cpu_auto_off()
48 void spm_disable_cpu_auto_off(int cluster, int cpu) in spm_disable_cpu_auto_off() argument
50 uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK); in spm_disable_cpu_auto_off()
56 void spm_set_cpu_power_off(int cluster, int cpu) in spm_set_cpu_power_off() argument
58 mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON); in spm_set_cpu_power_off()
73 void mcucfg_set_bootaddr(int cluster, int cpu, uintptr_t bootaddr) in mcucfg_set_bootaddr() argument
81 assert(cpu >= 0 && cpu < 4); in mcucfg_set_bootaddr()
82 reg = mp2_bootreg[cpu]; in mcucfg_set_bootaddr()
84 reg = per_cpu(cluster, cpu, MCUCFG_BOOTADDR); in mcucfg_set_bootaddr()
[all …]
H A Dmtspmc.h23 void spm_poweron_cpu(int cluster, int cpu);
24 void spm_poweroff_cpu(int cluster, int cpu);
29 int spm_get_cpu_powerstate(int cluster, int cpu);
33 void spm_enable_cpu_auto_off(int cluster, int cpu);
34 void spm_disable_cpu_auto_off(int cluster, int cpu);
35 void spm_set_cpu_power_off(int cluster, int cpu);
38 void mcucfg_init_archstate(int cluster, int cpu, int arm64);
39 void mcucfg_set_bootaddr(int cluster, int cpu, uintptr_t bootaddr);
40 uintptr_t mcucfg_get_bootaddr(int cluster, int cpu);
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/constraints/
H A Dmt_spm_rc_internal.h33 bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
36 int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
37 int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
41 bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
44 int spm_run_rc_syspll(unsigned int cpu, int state_id);
45 int spm_reset_rc_syspll(unsigned int cpu, int state_id);
49 bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
52 int spm_run_rc_bus26m(unsigned int cpu, int state_id);
53 int spm_reset_rc_bus26m(unsigned int cpu, int state_id);
57 bool spm_is_valid_rc_vcore(unsigned int cpu, int state_id);
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/constraints/
H A Dmt_spm_rc_internal.h28 bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
31 int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
32 int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
36 bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
39 int spm_run_rc_dram(unsigned int cpu, int state_id);
40 int spm_reset_rc_dram(unsigned int cpu, int state_id);
44 bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
47 int spm_run_rc_syspll(unsigned int cpu, int state_id);
48 int spm_reset_rc_syspll(unsigned int cpu, int state_id);
52 bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/drivers/flowctrl/
H A Dflowctrl.c86 unsigned int i, cpu = read_mpidr() & MPIDR_CPU_MASK; in tegra_fc_ccplex_pgexit_lock() local
99 if (i == cpu) in tegra_fc_ccplex_pgexit_lock()
125 int cpu = mpidr & MPIDR_CPU_MASK; in tegra_fc_cpu_powerdn() local
127 VERBOSE("CPU%d powering down...\n", cpu); in tegra_fc_cpu_powerdn()
128 tegra_fc_prepare_suspend(cpu, 0); in tegra_fc_cpu_powerdn()
136 int cpu = mpidr & MPIDR_CPU_MASK; in tegra_fc_cluster_idle() local
141 tegra_fc_cc4_ctrl(cpu, 0); in tegra_fc_cluster_idle()
149 tegra_fc_prepare_suspend(cpu, val); in tegra_fc_cluster_idle()
157 int cpu = mpidr & MPIDR_CPU_MASK; in tegra_fc_cluster_powerdn() local
162 tegra_fc_cc4_ctrl(cpu, 0); in tegra_fc_cluster_powerdn()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/constraints/
H A Dmt_spm_rc_internal.h33 int spm_is_valid_rc_cpu_buck_ldo(int cpu, int state_id);
37 int spm_run_rc_cpu_buck_ldo(int cpu, int state_id);
38 int spm_reset_rc_cpu_buck_ldo(int cpu, int state_id);
42 bool spm_is_valid_rc_syspll(uint32_t cpu, int state_id);
45 int spm_run_rc_syspll(uint32_t cpu, int state_id);
46 int spm_reset_rc_syspll(uint32_t cpu, int state_id);
50 bool spm_is_valid_rc_bus26m(uint32_t cpu, int state_id);
53 int spm_run_rc_bus26m(uint32_t cpu, int state_id);
54 int spm_reset_rc_bus26m(uint32_t cpu, int state_id);
58 bool spm_is_valid_rc_vcore(uint32_t cpu, int state_id);
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/mcdi/
H A Dmt_cpu_pm.c23 static int pwr_state_prompt(unsigned int cpu, const psci_power_state_t *state) in pwr_state_prompt() argument
28 static int pwr_state_reflect(unsigned int cpu, const psci_power_state_t *state) in pwr_state_reflect() argument
30 mtk_cpc_core_on_hint_clr(cpu); in pwr_state_reflect()
39 static int pwr_cpu_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwron() argument
44 static int pwr_cpu_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwrdwn() argument
52 static int pwr_cluster_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cluster_pwron() argument
57 static int pwr_cluster_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cluster_pwrdwn() argument
62 static int pwr_mcusys_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_mcusys_pwron() argument
73 static int pwr_mcusys_pwron_finished(unsigned int cpu, in pwr_mcusys_pwron_finished() argument
82 mt_lp_rm_reset_constraint(plat_mt_lp_cpu_rc, cpu, state_id); in pwr_mcusys_pwron_finished()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/mcdi/
H A Dmt_cpu_pm.c23 static int pwr_state_prompt(unsigned int cpu, const psci_power_state_t *state) in pwr_state_prompt() argument
28 static int pwr_state_reflect(unsigned int cpu, const psci_power_state_t *state) in pwr_state_reflect() argument
30 mtk_cpc_core_on_hint_clr(cpu); in pwr_state_reflect()
39 static int pwr_cpu_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwron() argument
44 static int pwr_cpu_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwrdwn() argument
52 static int pwr_cluster_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cluster_pwron() argument
57 static int pwr_cluster_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cluster_pwrdwn() argument
62 static int pwr_mcusys_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_mcusys_pwron() argument
73 static int pwr_mcusys_pwron_finished(unsigned int cpu, in pwr_mcusys_pwron_finished() argument
82 mt_lp_rm_reset_constraint(plat_mt_lp_cpu_rc, cpu, state_id); in pwr_mcusys_pwron_finished()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/mcdi/
H A Dmt_cpu_pm.c23 static int pwr_state_prompt(unsigned int cpu, const psci_power_state_t *state) in pwr_state_prompt() argument
28 static int pwr_state_reflect(unsigned int cpu, const psci_power_state_t *state) in pwr_state_reflect() argument
30 mtk_cpc_core_on_hint_clr(cpu); in pwr_state_reflect()
39 static int pwr_cpu_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwron() argument
44 static int pwr_cpu_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cpu_pwrdwn() argument
52 static int pwr_cluster_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_cluster_pwron() argument
57 static int pwr_cluster_pwrdwn(unsigned int cpu, const psci_power_state_t *state) in pwr_cluster_pwrdwn() argument
62 static int pwr_mcusys_pwron(unsigned int cpu, const psci_power_state_t *state) in pwr_mcusys_pwron() argument
73 static int pwr_mcusys_pwron_finished(unsigned int cpu, in pwr_mcusys_pwron_finished() argument
82 mt_lp_rm_reset_constraint(plat_mt_lp_cpu_rc, cpu, state_id); in pwr_mcusys_pwron_finished()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8195/include/
H A Dplat_mtk_lpm.h28 int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state);
29 int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state);
31 int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state);
32 int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state);
34 int (*pwr_cluster_on)(unsigned int cpu,
36 int (*pwr_cluster_dwn)(unsigned int cpu,
39 int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state);
40 int (*pwr_mcusys_on_finished)(unsigned int cpu,
42 int (*pwr_mcusys_dwn)(unsigned int cpu,
/rk3399_ARM-atf/plat/mediatek/mt8192/include/
H A Dplat_mtk_lpm.h28 int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state);
29 int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state);
31 int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state);
32 int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state);
34 int (*pwr_cluster_on)(unsigned int cpu,
36 int (*pwr_cluster_dwn)(unsigned int cpu,
39 int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state);
40 int (*pwr_mcusys_on_finished)(unsigned int cpu,
42 int (*pwr_mcusys_dwn)(unsigned int cpu,
/rk3399_ARM-atf/drivers/renesas/rcar_gen4/pwrc/
H A Dpwrc.c105 int cpu; in rcar_pwrc_core_pos() local
107 cpu = plat_core_pos_by_mpidr(mpidr); in rcar_pwrc_core_pos()
108 if (cpu < 0) { in rcar_pwrc_core_pos()
113 return (uint32_t)cpu; in rcar_pwrc_core_pos()
118 uint32_t cluster, cpu; in rcar_pwrc_cpuon() local
122 cpu = rcar_pwrc_core_pos(mpidr); in rcar_pwrc_cpuon()
131 mmio_clrbits_32(rcar_apmu_pwrctrlc(cpu), RCAR_APMU_PWRCTRLC_PCHPDNEN); in rcar_pwrc_cpuon()
132 while (mmio_read_32(rcar_apmu_pwrctrlc(cpu)) & RCAR_APMU_PWRCTRLC_PCHPDNEN) in rcar_pwrc_cpuon()
135 mmio_setbits_32(rcar_apmu_pwrctrlc(cpu), RCAR_APMU_PWRCTRLC_WUP_REQ); in rcar_pwrc_cpuon()
138 while ((mmio_read_32(rcar_apmu_pwrctrlc(cpu)) & RCAR_APMU_PWRCTRLC_WUP_REQ) == in rcar_pwrc_cpuon()
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/rk3399_ARM-atf/plat/mediatek/mt8186/include/
H A Dplat_mtk_lpm.h28 int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state);
29 int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state);
31 int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state);
32 int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state);
34 int (*pwr_cluster_on)(unsigned int cpu,
36 int (*pwr_cluster_dwn)(unsigned int cpu,
39 int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state);
40 int (*pwr_mcusys_on_finished)(unsigned int cpu,
42 int (*pwr_mcusys_dwn)(unsigned int cpu,

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