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/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spm/
H A Dspm_pmic_wrap.c50 } _[NR_PMIC_WRAP_CMD]; member
59 ._[CMD_0] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(70000),},
60 ._[CMD_1] = {BUCK_VCORE_ELR0, VOLT_TO_PMIC_VAL(80000),},
61 ._[CMD_2] = {BUCK_VPROC12_CON0, 0x3,},
62 ._[CMD_3] = {BUCK_VPROC12_CON0, 0x1,},
63 ._[CMD_4] = {BUCK_VPROC11_CON0, 0x3,},
64 ._[CMD_5] = {BUCK_VPROC11_CON0, 0x1,},
65 ._[CMD_6] = {TOP_SPI_CON0, 0x1,},
66 ._[CMD_7] = {TOP_SPI_CON0, 0x0,},
67 ._[CMD_8] = {BUCK_VPROC12_CON0, 0x0,},
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_pmic_wrap.c47 } _[NR_PMIC_WRAP_CMD]; member
56 ._[CMD_0] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(72500),},
57 ._[CMD_1] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(65000),},
58 ._[CMD_2] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(60000),},
59 ._[CMD_3] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(57500),},
60 ._[CMD_4] = {TOP_SPI_CON0, 0x1,},
61 ._[CMD_5] = {TOP_SPI_CON0, 0x0,},
62 ._[CMD_6] = {BUCK_TOP_CON1, 0x0,},
63 ._[CMD_7] = {BUCK_TOP_CON1, 0xf,},
64 ._[CMD_8] = {TOP_CON, 0x3,},
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm_pmic_wrap.c52 } _[NR_PMIC_WRAP_CMD]; member
61 ._[CMD_0] = {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(75000)),},
62 ._[CMD_1] = {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(65000)),},
63 ._[CMD_2] = {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(60000)),},
64 ._[CMD_3] = {BUCK_VGPU11_ELR0, _BITS_(6, 0, VOLT_TO_PMIC_VAL(55000)),},
65 ._[CMD_4] = {TOP_SPI_CON0, _BITS_(0, 0, 1),},
66 ._[CMD_5] = {TOP_SPI_CON0, _BITS_(0, 0, 0),},
67 ._[CMD_6] = {BUCK_TOP_CON1, 0x0,}, /* MT6315-3: VMD NO LP */
68 ._[CMD_7] = {BUCK_TOP_CON1, 0xF,}, /* MT6315-3: VMD LP */
69 ._[CMD_8] = {TOP_CON, 0x3,}, /* MT6315-3: PMIC NO LP */
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_pmic_wrap.c47 } _[NR_PMIC_WRAP_CMD]; member
56 ._[CMD_0] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(75000),},
57 ._[CMD_1] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(65000),},
58 ._[CMD_2] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(60000),},
59 ._[CMD_3] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(55000),},
60 ._[CMD_4] = {TOP_SPI_CON0, 0x1,},
61 ._[CMD_5] = {TOP_SPI_CON0, 0x0,},
62 ._[CMD_6] = {BUCK_TOP_CON1, 0x0,},
63 ._[CMD_7] = {BUCK_TOP_CON1, 0xf,},
64 ._[CMD_8] = {TOP_CON, 0x3,},
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/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_pmic_wrap.c34 } _[NR_PMIC_WRAP_CMD]; member
53 ._[CMD_0] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(80000), },
54 ._[CMD_1] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(80000), },
55 ._[CMD_2] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(80000), },
56 ._[CMD_3] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(80000), },
57 ._[CMD_4] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(80000), },
58 ._[CMD_5] = { TOP_SPI_CON0_66, 0x1, },
59 ._[CMD_6] = { TOP_SPI_CON0_66, 0x0, },
73 ._[CMD_0] = { BUCK_VCORE_ELR0_57, VOLT_TO_PMIC_VAL_57(80000), },
74 ._[CMD_1] = { BUCK_VCORE_ELR0_57, VOLT_TO_PMIC_VAL_57(75000), },
[all …]
/rk3399_ARM-atf/docs/about/
H A Dmaintainers.rst25 :|G|: `danh-arm`_
27 :|G|: `soby-mathew`_
29 :|G|: `sandrine-bailleux-arm`_
31 :|G|: `AlexeiFedorov`_
33 :|G|: `manish-pandey-arm`_
35 :|G|: `mardyk01`_
37 :|G|: `odeprez`_
39 :|G|: `bipinravi-arm`_
41 :|G|: `joannafarley-arm`_
43 :|G|: `jwerner-chromium`_
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H A Dcontact.rst22 - `TF-A development`_
23 - `TF-A-Tests development`_
25 You can see a `summary of all the lists`_ on the TrustedFirmware.org website.
32 topic within the community. More details can be found `here`_.
39 Bug reports may be filed on the `issue tracker`_ on Github. Using this tracker
48 .. _`issue tracker`: https://github.com/TrustedFirmware-A/trusted-firmware-a/issues
49 .. _`TF-A development`: https://lists.trustedfirmware.org/mailman3/lists/tf-a.lists.trustedfirmware…
50 .. _`TF-A-Tests development`: https://lists.trustedfirmware.org/mailman3/lists/tf-a-tests.lists.tru…
51 .. _`summary of all the lists`: https://lists.trustedfirmware.org/mailman3/lists/
/rk3399_ARM-atf/include/lib/cpus/aarch64/
H A Dcpu_macros.S214 .quad check_erratum_\_cpu\()_\_id
266 .pushsection .text.asm.erratum_\_cpu\()_\_id\()_wa, "ax"
270 bl check_erratum_\_cpu\()_\_id
273 cbz x0, erratum_\_cpu\()_\_id\()_skip_reset
286 func erratum_\_cpu\()_\_id\()_wa
295 b erratum_\_cpu\()_\_id\()_skip_runtime
302 bl check_erratum_\_cpu\()_\_id
303 cbz x0, erratum_\_cpu\()_\_id\()_skip_runtime
311 erratum_\_cpu\()_\_id\()_skip_reset:
332 erratum_\_cpu\()_\_id\()_skip_runtime:
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/rk3399_ARM-atf/plat/mediatek/include/drivers/pmic/
H A Dpmic_set_lowpower.h113 _chip##_RG_BUCK_##_name##_##_user##_OP_CFG_ADDR, \
117 _chip##_RG_BUCK_##_name##_##_user##_OP_MODE_ADDR, \
121 _chip##_RG_BUCK_##_name##_##_user##_OP_EN_ADDR, \
146 _chip##_RG_LDO_##_name##_##_user##_OP_CFG_ADDR, \
150 _chip##_RG_LDO_##_name##_##_user##_OP_MODE_ADDR, \
154 _chip##_RG_LDO_##_name##_##_user##_OP_EN_ADDR, \
162 struct spmi_device *sdev = lowpower_sdev[_chip##_##_slvid##_SLAVE]; \
165 _chip##_RG_BUCK_##_name##_##_user##_OP_CFG_ADDR, \
169 _chip##_RG_BUCK_##_name##_##_user##_OP_MODE_ADDR, \
173 _chip##_RG_BUCK_##_name##_##_user##_OP_EN_ADDR, \
[all …]
H A Dmt6359p_set_lowpower.h41 pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_CFG_ADDR, \
44 pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_MODE_ADDR, \
47 pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_EN_ADDR, \
59 pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_##_user##_OP_CFG_ADDR, \
62 pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_##_user##_OP_EN_ADDR, \
/rk3399_ARM-atf/docs/security_advisories/
H A Dsecurity-advisory-tfv-6.rst8 | CVE ID | `CVE-2017-5753`_ / `CVE-2017-5715`_ / `CVE-2017-5754`_ / |
9 | | `CVE-2018-3640`_ / `CVE-2018-3639`_ / `CVE-2022-23960`_ |
22 | Fix Version | `Pull Request #1214`_, `Pull Request #1228`_, |
23 | | `Pull Request #1240`_ and `Pull Request #1405`_ |
30 `Google Project Zero`_. To understand the background and wider impact of these
32 Update`_.
34 Variant 1 (`CVE-2017-5753`_)
40 Variant 2 (`CVE-2017-5715`_)
66 `Pull Request #1240`_ and `Pull Request #1405`_ optimise the earlier fixes by
67 implementing a specified `CVE-2017-5715`_ workaround SMC
[all …]
H A Dsecurity-advisory-tfv-11.rst7 | CVE ID | `CVE-2023-49100`_ |
19 | Fix Version | `a7eff3477`_ "fix(sdei): ensure that interrupt ID is valid" |
21 | Credit | Christian Lindenmeier `@_chli_`_ |
22 | | Marcel Busch `@0ddc0de`_ |
23 | | `IT Security Infrastructures Lab`_ |
33 Refer to SDEI_INTERRUPT_BIND in the `SDEI Specification`_ for further details.
85 .. _@_chli_: https://twitter.com/_chli_
86 .. _@0ddc0de: https://twitter.com/0ddc0de
H A Dsecurity-advisory-tfv-7.rst10 | CVE ID | `CVE-2018-3639`_ |
22 | Fix Version | `Pull Request #1392`_, `Pull Request #1397`_ |
29 identified by `Google Project Zero`_. To understand the background and wider
31 Processor Security Update`_.
39 (SDEI)`_. Also, the TF-A project does not have visibility of all
46 approaches in `Pull Request #1392`_ and `Pull Request #1397`_. Both approaches
84 interfaces for mitigating cache speculation vulnerabilities`_.
H A Dsecurity-advisory-tfv-9.rst10 | CVE ID | `CVE-2022-23960`_ |
26 | Fix Version | `Gerrit topic #spectre_bhb`_ |
35 systems, please refer to the `Arm Processor Security Update`_. The whitepaper
40 `CVE-2022-23960`_
97 Convention specification`_ for more details.
99 `Gerrit topic #spectre_bhb`_ This patchset implements the Spectre-BHB loop
105 `CVE-2022-23960`_ workaround SMC(``SMCCC_ARCH_WORKAROUND_3``) for use by normal
107 in the `SMCCC Calling Convention specification`_. The specification and
H A Dsecurity-advisory-tfv-2.rst8 | CVE ID | `CVE-2017-7564`_ |
20 | Fix Version | 15 Feb 2017 `Pull Request #841`_ |
29 be seen in the implementation of the ``el3_arch_init_common`` `AArch64 macro`_ .
37 Earlier versions of TF (prior to `commit 495f3d3`_) did not assign this bit.
53 image or integrate the `AArch32 equivalent`_ of the ``el3_arch_init_common``
H A Dsecurity-advisory-tfv-13.rst11 | CVE ID | `CVE-2024-7881`_ |
24 | Fix Version | `Gerrit topic #ar/smccc_arch_wa_4`_ |
25 | | Also see mitigation guidance in the `Official Arm Advisory`_ |
79 Specification`_ for more details.
86 refer to the full `Official Arm Advisory`_.
H A Dsecurity-advisory-tfv-5.rst8 | CVE ID | `CVE-2017-15031`_ |
20 | Fix Version | `Pull Request #1127`_ (merged on 18 October 2017) |
22 | | `Commit e290a8fcbc`_ (merged on 23 August 2019) |
24 | | `Commit c3e8b0be9b`_ (merged on 27 September 2019) |
/rk3399_ARM-atf/
H A Dreadme.rst5 for `Arm A-Profile architectures`_ (Armv8-A and Armv7-A), including an Exception
6 Level 3 (EL3) `Secure Monitor`_. It provides a suitable starting point for
12 - `Power State Coordination Interface (PSCI)`_
13 - `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT)`_
14 - `SMC Calling Convention`_
15 - `System Control and Management Interface (SCMI)`_
16 - `Software Delegated Exception Interface (SDEI)`_
31 To find out more about Trusted Firmware-A, please `view the full documentation`_
32 that is available through `trustedfirmware.org`_.
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/
H A Dmt_cpu_pm.h74 _p.rvbaraddr_l = CORE_RVBRADDR_##_cl##_##_c##_L; \
75 _p.rvbaraddr_h = CORE_RVBRADDR_##_cl##_##_c##_H; \
76 _p.pwr.ppu_pwpr = CORE_PPU_PWPR_##_cl##_##_c; \
77 _p.pwr.ppu_pwsr = CORE_PPU_PWSR_##_cl##_##_c; \
78 _p.pwr.ppu_dcdr0 = CORE_PPU_DCDR0_##_cl##_##_c; \
79 _p.pwr.ppu_dcdr1 = CORE_PPU_DCDR1_##_cl##_##_c; })
/rk3399_ARM-atf/docs/
H A Dindex.rst27 software for `Armv7-A and Armv8-A`_, including a `Secure Monitor`_ executing
31 - The `Power State Coordination Interface (PSCI)`_
32 - `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT)`_
33 - `SMC Calling Convention`_
34 - `System Control and Management Interface (SCMI)`_
35 - `Software Delegated Exception Interface (SDEI)`_
36 - `PSA FW update specification`_
H A Dlicense.rst56 - The libc source code is derived from `FreeBSD`_ and `SCC`_. FreeBSD uses
86 See the original `Linux MIT license`_.
88 - Some source files originating from the `Open Profile for DICE`_ project.
91 code must also be made under the terms of `Apache License 2.0`_.
96 - Some source files originating from the `pydevicetree`_ project.
99 code must also be made under the terms of `Apache License 2.0`_.
113 - Some source files originating from the `edk2`_ project.
122 - Some source files originating from the `mbed OS`_ project.
125 code must also be made under the terms of `Apache License 2.0`_.
/rk3399_ARM-atf/docs/components/
H A Drealm-management-extension.rst6 `Arm Confidential Compute Architecture (Arm CCA)`_. TF-A supports RME starting
16 Root world. In the realm world, a Realm Management Monitor firmware (`RMM`_)
46 Realm-world firmware (`RMM`_) is loaded by BL2 in the Realm physical address
72 world. It initializes the `RMM`_ and handles Realm Management Interface (RMI)
75 There is a contract between `RMM`_ and RMMD that defines the arguments that the
77 This contract is defined in the `RMM`_ Boot Interface, which can be found at
81 to `RMM`_. This can be found at :ref:`runtime_services_and_interface`.
95 platform is by the use of `Shrinkwrap`_.
110 - R-EL2 (`RMM`_)
111 - S-EL2 (`SPM`_ / Hafnium) in a 4-worlds configuration
[all …]
H A Dsecure-partition-manager.rst38 #. S-EL2 SPMC based on the FF-A specification `[1]`_, enabling virtualization in
39 the secure world, managing multiple S-EL1 or S-EL0 partitions `[5]`_.
41 without virtualization in the secure world `[6]`_.
43 single S-EL0 partition `[2]`_.
85 and exhaustive list of registers is visible at `[4]`_.
90 (see `[3]`_). It
221 BL32 image. The SPMC manifest is loaded by BL2 as the ``TOS_FW_CONFIG`` image `[7]`_.
235 .. _[1]:
239 .. _[2]:
243 .. _[3]:
[all …]
/rk3399_ARM-atf/docs/plat/arm/morello/
H A Dindex.rst5 The platform port present at `site <https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git>`_
8 …ility architecture specific changes will be added `here <https://git.morello-project.org/morello>`_
10 …s available at `info <https://developer.arm.com/architectures/cpu-architecture/a-profile/morello>`_
32 …r.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads>`_.
/rk3399_ARM-atf/docs/getting_started/
H A Dprerequisites.rst15 `TrustedFirmware.org`_. To clone this repository from the server, run the following
34 mbed TLS\ [#f1]_ 3.6.5
35 Node.js [#f2]_ 20.11.1
38 QCBOR\ [#f3]_ 1.2
39 Sphinx\ [#f2]_ 5.3.0
55 the table above. This can be installed from the `Arm Developer website`_.
89 Arm Development Studio (`Arm-DS`_)
110 For installation instructions, see the `official Poetry documentation`_.
136 scripts, you can use the `Node Version Manager`_. To install both NVM and an
151 Release 20.01`_. Alternatively, you can build the binaries from source using
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