1*868b2d60SZhigang Qin /*
2*868b2d60SZhigang Qin * Copyright (c) 2025, Mediatek Inc. All rights reserved.
3*868b2d60SZhigang Qin * SPDX-License-Identifier: BSD-3-Clause
4*868b2d60SZhigang Qin */
5*868b2d60SZhigang Qin
6*868b2d60SZhigang Qin #ifndef MT6359P_SET_LOWPOWER_H
7*868b2d60SZhigang Qin #define MT6359P_SET_LOWPOWER_H
8*868b2d60SZhigang Qin
9*868b2d60SZhigang Qin #include <stdint.h>
10*868b2d60SZhigang Qin
11*868b2d60SZhigang Qin #include "mt6359p_lowpower_reg.h"
12*868b2d60SZhigang Qin #include <pmic_wrap_init_common.h>
13*868b2d60SZhigang Qin
14*868b2d60SZhigang Qin #define OP_MODE_MU (0)
15*868b2d60SZhigang Qin #define OP_MODE_LP (1)
16*868b2d60SZhigang Qin
17*868b2d60SZhigang Qin #define HW_OFF (0)
18*868b2d60SZhigang Qin #define HW_ON (0)
19*868b2d60SZhigang Qin #define HW_LP (1)
20*868b2d60SZhigang Qin
21*868b2d60SZhigang Qin enum {
22*868b2d60SZhigang Qin HW0 = 0,
23*868b2d60SZhigang Qin HW1,
24*868b2d60SZhigang Qin HW2,
25*868b2d60SZhigang Qin HW3,
26*868b2d60SZhigang Qin HW4,
27*868b2d60SZhigang Qin HW5,
28*868b2d60SZhigang Qin HW6,
29*868b2d60SZhigang Qin HW7,
30*868b2d60SZhigang Qin HW8,
31*868b2d60SZhigang Qin HW9,
32*868b2d60SZhigang Qin HW10,
33*868b2d60SZhigang Qin HW11,
34*868b2d60SZhigang Qin HW12,
35*868b2d60SZhigang Qin HW13,
36*868b2d60SZhigang Qin HW14,
37*868b2d60SZhigang Qin };
38*868b2d60SZhigang Qin
39*868b2d60SZhigang Qin #define PMIC_BUCK_SET_LP(_chip, _name, _user, _en, _mode, _cfg) \
40*868b2d60SZhigang Qin { \
41*868b2d60SZhigang Qin pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_CFG_ADDR, \
42*868b2d60SZhigang Qin 1 << _user, \
43*868b2d60SZhigang Qin (_cfg & 0x1) ? 1 << _user : 0); \
44*868b2d60SZhigang Qin pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_MODE_ADDR, \
45*868b2d60SZhigang Qin 1 << _user, \
46*868b2d60SZhigang Qin _mode ? 1 << _user : 0); \
47*868b2d60SZhigang Qin pmic_wrap_update_bits(_chip##_RG_BUCK_##_name##_##_user##_OP_EN_ADDR, \
48*868b2d60SZhigang Qin 1 << _user, \
49*868b2d60SZhigang Qin _en ? 1 << _user : 0); \
50*868b2d60SZhigang Qin }
51*868b2d60SZhigang Qin
52*868b2d60SZhigang Qin #define PMIC_LDO_SET_LP(_chip, _name, _user, _en, _mode, _cfg) \
53*868b2d60SZhigang Qin { \
54*868b2d60SZhigang Qin if (_user <= HW2) { \
55*868b2d60SZhigang Qin pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_OP_MODE_ADDR, \
56*868b2d60SZhigang Qin 1 << (_user + _chip##_RG_LDO_##_name##_OP_MODE_SHIFT), \
57*868b2d60SZhigang Qin _mode ? 1 << (_user + _chip##_RG_LDO_##_name##_OP_MODE_SHIFT) : 0); \
58*868b2d60SZhigang Qin } \
59*868b2d60SZhigang Qin pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_##_user##_OP_CFG_ADDR, \
60*868b2d60SZhigang Qin 1 << _user, \
61*868b2d60SZhigang Qin (_cfg & 0x1) ? 1 << _user : 0); \
62*868b2d60SZhigang Qin pmic_wrap_update_bits(_chip##_RG_LDO_##_name##_##_user##_OP_EN_ADDR, \
63*868b2d60SZhigang Qin 1 << _user, \
64*868b2d60SZhigang Qin _en ? 1 << _user : 0); \
65*868b2d60SZhigang Qin }
66*868b2d60SZhigang Qin
pmic_wrap_update_bits(uint32_t reg,uint32_t mask,uint32_t val)67*868b2d60SZhigang Qin static inline int pmic_wrap_update_bits(uint32_t reg, uint32_t mask, uint32_t val)
68*868b2d60SZhigang Qin {
69*868b2d60SZhigang Qin uint32_t orig = 0;
70*868b2d60SZhigang Qin int ret = 0;
71*868b2d60SZhigang Qin
72*868b2d60SZhigang Qin ret = pwrap_read(reg, &orig);
73*868b2d60SZhigang Qin if (ret < 0)
74*868b2d60SZhigang Qin return ret;
75*868b2d60SZhigang Qin
76*868b2d60SZhigang Qin orig &= ~mask;
77*868b2d60SZhigang Qin orig |= val & mask;
78*868b2d60SZhigang Qin
79*868b2d60SZhigang Qin ret = pwrap_write(reg, orig);
80*868b2d60SZhigang Qin return ret;
81*868b2d60SZhigang Qin }
82*868b2d60SZhigang Qin
83*868b2d60SZhigang Qin #endif /* MT6359P_MT6359P_SET_LOWPOWER_H */
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